CN110729999A - Mode control circuit and apparatus - Google Patents
Mode control circuit and apparatus Download PDFInfo
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- CN110729999A CN110729999A CN201910843307.0A CN201910843307A CN110729999A CN 110729999 A CN110729999 A CN 110729999A CN 201910843307 A CN201910843307 A CN 201910843307A CN 110729999 A CN110729999 A CN 110729999A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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Abstract
The embodiment of the invention provides a mode control circuit and a device. The circuit includes: the circuit comprises a detection circuit, a latch circuit and a pull-up and pull-down circuit, wherein the pull-up and pull-down circuit comprises a voltage pull-up circuit and a voltage pull-down circuit; the detection circuit is used for detecting whether the DVDD is powered down or not; the latch circuit is used for controlling the voltage of the first output end of the latch circuit and the voltage of the second output end of the latch circuit to be associated with the pull-up and pull-down circuit after the DVDD is powered down; the voltage pull-up circuit is used for pulling up the voltage of the first output end of the latch circuit to be the power supply voltage of the normally-charged area, so that the first output end of the latch circuit outputs a control signal for controlling the controlled circuit to enter a power-down mode; the voltage pull-Down circuit is used for pulling Down the voltage of the second output end of the latch circuit to the ground, so that a controlled circuit such as an ADC circuit enters a Power Down mode after being powered Down by DVDD, thereby avoiding unnecessary Power consumption of the controlled circuit and preventing the input end of the controlled circuit from leaking electricity.
Description
Technical Field
The present invention relates to communications technologies, and in particular, to a mode control circuit and a device.
Background
Analog-to-Digital converters (ADCs) are often used in battery voltage monitoring, key recognition, sensors, etc. the ADCs may be integrated into a plurality of processing chips for enabling and controlling the respective processing chips. In the above-mentioned battery voltage monitoring, key identification, sensor and other scenarios, when both the digital power supply and the analog power supply of the chip are powered down, since the digital power supply is a power supply that generates a signal for controlling the ADC operating mode, after the DVDD of the chip is powered down, the current mode of the ADC enters an uncertain state, for example, after the DVDD is powered down, the ADC is still in a normal operating mode (normal), thereby generating corresponding power consumption. As shown in fig. 1, when both the digital power supply DVDD and the analog power supply AVDD of the ADC are powered down, the current mode of the ADC enters an uncertain state, and since the potential of an N-well inside the ADC changes from a high voltage to zero, a substrate of a P-type Metal-Oxide-semiconductor field Effect Transistor (MOSFET) serving as a transmission gate does not have a high voltage, so that a PN junction is biased forward, and a current flowing from an input terminal of the ADC to the inside of the ADC is reversed (in the figure, an ADC CORE is an ADC CORE), so as to form a current loop from a Device Under Test (DUT) to the N-well inside the ADC, thereby causing a leakage current in a standby state.
Therefore, how to ensure that the ADC circuit can correctly enter the Power Down mode when the DVDD is powered Down and no leakage at the ADC input end is generated is a technical problem to be solved urgently.
Disclosure of Invention
The embodiment of the invention provides a mode control circuit and mode control equipment, which are used for solving the technical problems that in the prior art, an ADC (analog to digital converter) circuit cannot accurately enter a Power Down mode when being powered off under DVDD (digital video display device), so that corresponding Power consumption is generated, and the input of the ADC circuit leaks electricity.
In a first aspect, an embodiment of the present invention provides a mode control circuit, including: the circuit comprises a detection circuit, a latch circuit and a pull-up and pull-down circuit, wherein the pull-up and pull-down circuit comprises a voltage pull-up circuit and a voltage pull-down circuit; wherein,
the first input end of the detection circuit is connected with a digital power supply DVDD, the second input end of the detection circuit is connected with a power-down control input end, the first output end of the detection circuit is connected with the first control end of the latch circuit, the second output end of the detection circuit is connected with the second control end of the latch circuit, the power-down control input end is connected with the third control end of the latch circuit, the first end of the voltage pull-up circuit is connected with a power supply of a normally charged area, the second end of the voltage pull-up circuit is connected with the first output end of the latch circuit, the first end of the voltage pull-down circuit is connected with the second output end of the latch circuit, and the second end of the voltage pull-down circuit is grounded;
the detection circuit is used for detecting whether the DVDD is powered down or not;
the latch circuit is used for controlling the voltage of the first output end of the latch circuit and the voltage of the second output end of the latch circuit to be associated with the pull-up and pull-down circuit after the DVDD power-down is detected by the detection circuit;
the voltage pull-up circuit is used for pulling up the voltage of the first output end of the latch circuit to be the power supply voltage of the normally-charged area so as to control the voltage of the first output end of the latch circuit and the voltage of the second output end of the latch circuit to enter a locking state, and the first output end of the latch circuit outputs a control signal for controlling the controlled circuit to enter a power-down mode;
the voltage pull-down circuit is used for pulling down the voltage of the second output end of the latch circuit to the ground so as to control the voltage of the first output end of the latch circuit and the voltage of the second output end of the latch circuit to enter a locking state.
The controlled circuit can be an ADC circuit in a chip, and can also be a dual-power supply circuit. The Power Down mode may be a Power Down mode, a sleep mode, a standby mode, or the like. The above references to pull-down or pull-up refer to the raising or lowering of the voltage.
Through the mode control circuit provided by the first aspect, after the detection circuit detects that the DVDD is powered Down, the voltages of the first output end of the latch circuit and the second output end of the latch circuit are automatically triggered to be associated with the pull-up and pull-Down circuit, so that the voltage of the first output end of the latch circuit and the voltage of the second output end of the latch circuit enter a locking state under the action of the pull-up and pull-Down circuit, the first output end of the latch circuit outputs a control signal for controlling the controlled circuit to enter a Power-Down mode, and the controlled circuit is controlled to enter a Power Down mode. The circuit provided by the embodiment of the invention can enable a controlled circuit such as an ADC circuit to enter a Power Down mode after being powered off under DVDD, thereby avoiding unnecessary Power consumption generated by the controlled circuit; in addition, the circuit provided by the embodiment of the invention can trigger the subsequent controlled circuit to automatically enter a Power Down mode after the DVDD is powered off only by connecting the corresponding detection circuit under the DVDD, and an additional trigger circuit such as a circuit for generating an isolation signal Viso is not required to be added outside the DVDD, so that the circuit cost and the circuit complexity are reduced; furthermore, the mode control circuit in the embodiment can be connected with a power supply of a normally-on region, and the reverse bias of a PN junction of a PMOS tube serving as a transmission gate is ensured, so that the leakage of the input end of the mode control circuit is avoided, and the reliability of the circuit is ensured.
In one possible design, the detection circuit includes a first switch tube and an inverter; a first input terminal of the detection circuit is connected to the digital power source DVDD, a second input terminal of the detection circuit is connected to the power-down control input terminal, a first output terminal of the detection circuit is connected to the first control terminal of the latch circuit, and a second output terminal of the detection circuit is connected to the second control terminal of the latch circuit, which specifically includes:
a grid electrode of the first switching tube is connected with the power-down control input end, a source electrode of the first switching tube is connected with a first control end of the latch circuit, and a drain electrode of the first switching tube is respectively connected with the DVDD and a first input end of the phase inverter;
and the second input end of the phase inverter is connected with the power-down control input end, and the output end of the phase inverter is connected with the second control end of the latch circuit.
In one possible design, the inverter includes a second switching tube and a third switching tube; the drain electrode of the first switch tube is connected with the first input end of the phase inverter, the second input end of the phase inverter is connected with the power-down control input end, the output end of the phase inverter is connected with the second control end of the latch circuit, and the method specifically comprises the following steps:
the drain electrode of the first switch tube is connected with the source electrode of the second switch tube, the grid electrode of the second switch tube and the grid electrode of the third switch tube are respectively connected with the power-down control input end, the drain electrode of the second switch tube is connected with the drain electrode of the third switch tube and respectively connected with the second control end of the latch circuit, and the source electrode of the third switch tube is grounded.
In one possible design, the voltage pull-up circuit includes a fourth switching tube, and the voltage pull-down circuit includes a fifth switching tube; a first end of the voltage pull-up circuit is connected to a power supply of the normally-on region, a second end of the voltage pull-up circuit is connected to the first output end of the latch circuit, a first end of the voltage pull-down circuit is connected to the second output end of the latch circuit, and a second end of the voltage pull-down circuit is grounded, specifically:
the source electrode of the fourth switching tube is connected with the power supply of the normally-on region, the grid electrode of the fourth switching tube is connected with the drain electrode of the fourth switching tube, and the drain electrode of the fourth switching tube is connected with the first output end of the latch circuit;
the grid electrode of the fifth switching tube is connected with the drain electrode of the fifth switching tube, the source electrode of the fifth switching tube is grounded, and the drain electrode of the fifth switching tube is connected with the second output end of the latch circuit.
In one possible design, the latch circuit includes a first switch circuit, a second switch circuit, and a latch circuit; the first switching circuit comprises a sixth switching tube and a seventh switching tube, the second switching circuit comprises an eighth switching tube and a ninth switching tube, and the latch circuit comprises a tenth switching tube and an eleventh switching tube;
a grid electrode of the sixth switching tube and a grid electrode of the eighth switching tube are respectively connected with a source electrode of the first switching tube, a source electrode of the sixth switching tube is connected with a drain electrode of the seventh switching tube, a drain electrode of the sixth switching tube is connected with a drain electrode of the tenth switching tube, a grid electrode of the seventh switching tube is respectively connected with a drain electrode of the second switching tube and a drain electrode of the third switching tube, and a source electrode of the seventh switching tube is grounded;
the source electrode of the eighth switching tube is connected with the drain electrode of the ninth switching tube, the drain electrode of the eighth switching tube is connected with the drain electrode of the eleventh switching tube, the grid electrode of the ninth switching tube is connected with the power-down control input end, and the source electrode of the ninth switching tube is grounded;
the source electrode of the tenth switching tube and the source electrode of the eleventh switching tube are respectively connected with a power supply of a normally-on region, the grid electrode of the tenth switching tube is connected with the drain electrode of the eleventh switching tube, the drain electrode of the tenth switching tube is respectively connected with the drain electrode of the fourth switching tube and the grid electrode of the eleventh switching tube, and the drain electrode of the eleventh switching tube is connected with the drain electrode of the fifth switching tube.
In one possible design, the first switching circuit further includes a twelfth switching tube, and the second switching circuit further includes a thirteenth switching tube;
the drain electrode of the sixth switching tube is connected with the drain electrode of the tenth switching tube, and specifically:
the drain electrode of the sixth switching tube is connected with the source electrode of the twelfth switching tube, the drain electrode of the twelfth switching tube is connected with the drain electrode of the tenth switching tube, and the grid electrode of the twelfth switching tube is connected with the grid electrode of the seventh switching tube;
the drain electrode of the eighth switching tube is connected with the drain electrode of the eleventh switching tube, and specifically:
the drain electrode of the eighth switching tube is connected with the source electrode of the thirteenth switching tube, the drain electrode of the thirteenth switching tube is connected with the drain electrode of the eleventh switching tube, and the gate electrode of the thirteenth switching tube is connected with the gate electrode of the ninth switching tube.
Through the mode control circuit provided by each possible design, a controlled circuit such as an ADC (analog-to-digital converter) circuit can enter a Power Down mode after being powered off under DVDD (digital video display), so that unnecessary Power consumption of the controlled circuit is avoided, and the overall Power consumption overhead of a system is saved; in addition, the circuit provided by the embodiment of the invention can automatically trigger the subsequent controlled circuit to automatically enter a Power Down mode after the DVDD is powered off only by connecting the corresponding detection circuit under the DVDD under the state without an external control signal, and an additional trigger circuit is not required to be added outside the DVDD, so that the circuit cost and the circuit complexity are reduced; furthermore, the mode control circuit provided by the embodiment of the invention does not generate leakage current under the condition of power supply under DVDD, and ensures the reliability of the whole circuit.
In a second aspect, an embodiment of the present invention provides an apparatus, including a controlled circuit, further including: a mode control circuit as claimed in any one of claims 1 to 6;
the mode control circuit is connected with the controlled circuit.
The beneficial effects of the device provided by the second aspect can be found in the possible designs of the first aspect and the first aspect, and are not described herein again.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of a chip entering a sleep state according to an embodiment of the present invention;
FIG. 2 is a schematic block diagram of the mode control circuit applied to the ADC circuit according to the embodiment of the present invention;
FIG. 3 is a circuit diagram of a first embodiment of a mode control circuit according to the present invention;
fig. 4 is a circuit diagram of a second embodiment of a mode control circuit according to the present invention;
fig. 5 is a circuit diagram of a third embodiment of a mode control circuit according to the present invention;
fig. 6 is a circuit diagram of a fourth embodiment of a mode control circuit according to the present invention;
fig. 7 is a schematic diagram of an embodiment of an apparatus according to an embodiment of the present invention.
Description of reference numerals:
10: a detection circuit; 11: a latch circuit; 12: a pull-up and pull-down circuit;
101: a first input of the detection circuit; 102: a second input of the detection circuit;
13: a power down control input; 103: a first output terminal of the detection circuit;
104: a second output terminal of the detection circuit; 111: a first control terminal of a latch circuit;
112: a second control terminal of the latch circuit; 113: a third control terminal of the latch circuit;
114: a first output of the latch circuit; 115: a second output of the latch circuit;
121: a voltage pull-up circuit; 122: a voltage pull-down circuit;
1211: a first terminal of a circuit pull-up circuit; 1212: a second terminal of the voltage pull-up circuit;
1221: a first terminal of a voltage pull-down circuit; 1222: a second terminal of the voltage pull-down circuit;
105: an inverter; 1051: a first input of an inverter;
1052: a second input of the inverter; 1053: an output terminal of the inverter;
m1: a first switch tube; m2: a second switching tube; m3: a third switching tube;
m4: a fourth switching tube; m5: a fifth switching tube; m6: a sixth switching tube;
m7: a seventh switching tube; m8: an eighth switching tube; m9: a ninth switching tube;
m10: a tenth switching tube; m11: an eleventh switching tube; m12: a twelfth switching tube;
m13: a thirteenth switching tube; 116: a first switching circuit; 117: a second switching circuit;
118: a latch circuit; 20: a controlled circuit; 21: a mode control circuit;
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The mode control circuit related to the embodiment of the invention can be used for controlling any controlled circuit which enters an uncertain state after a digital power supply DVDD is powered down, such as an ADC (analog-to-digital converter) circuit in a chip or a dual-power supply circuit. The mode control circuit can control the controlled circuit to enter a power-down mode along with the power-down of the DVDD after the DVDD is powered down, so that extra power consumption is avoided. Taking the controlled circuit as an ADC circuit as an example, the schematic block diagram of the mode control circuit acting on the ADC circuit can be seen in fig. 2, the mode control circuit and the digital power supply DVDD, and the analog power supply AVDD are power supplies in a normally-on region, and provide an analog power supply voltage for the mode control circuit after the DVDD is powered off, so as to ensure that the PN junction of the PMOS transistor in fig. 2 is reversely biased, and the input terminal of the ADC circuit does not generate a leakage current. It should be noted that the signal for controlling the ADC circuit to enter the Power Down mode is generated by the digital Power supply DVDD, and the ADC circuit in the prior art enters the indeterminate state after the DVDD is powered Down, but in the embodiment of the present invention, the ADC circuit automatically enters the Power Down mode after the DVDD is powered Down, which is described in detail in the following embodiments.
In addition, the embodiment of the invention relates to a Power-Down mode which can be a Power Down mode; the related Power Down control input terminal may be a Power Down control input terminal, and when the digital Power supply DVDD in the circuit in which the mode control circuit according to the embodiment of the present invention is located is powered Down, the voltage at the Power Down control input terminal is a low potential. Optionally, when the digital power supply DVDD in the circuit in which the mode control circuit according to the embodiment of the present invention is located is charged, the voltage at the power-down control input terminal may be a high potential or a low potential. When the DVDD is electrified and the voltage at the Power-Down control input end is a high potential, the output of the mode control circuit is a high potential, the controlled circuit is controlled to enter a Power Down mode, and when the DVDD is electrified and the voltage at the Power-Down control input end is a low potential, the output of the mode control circuit is a low potential, and the controlled circuit is controlled to normally work.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 3 is a circuit diagram of a first embodiment of a mode control circuit according to the present invention. The present embodiment relates to a specific process of ensuring that the first output terminal 114 of the latch circuit 11 outputs the control signal to control the controlled circuit to enter the Power Down mode through the latch circuit 11 and the pull-up and pull-Down circuit 12 after the detection circuit 10 detects the DVDD Power-Down. As shown in fig. 3, the mode control circuit may include: a detection circuit 10, a latch circuit 11, and a pull-down circuit 12, the pull-down circuit 12 including a voltage pull-up circuit 121 and a voltage pull-down circuit 122.
A first input end 101 of the detection circuit 10 is connected to a digital power DVDD, a second input end 102 of the detection circuit 10 is connected to a power-down control input end 13, a first output end 103 of the detection circuit 10 is connected to a first control end 111 of the latch circuit 11, a second output end 104 of the detection circuit 10 is connected to a second control end 112 of the latch circuit 11, the power-down control input end 13 is connected to a third control end 113 of the latch circuit 11, a first end 1211 of the voltage pull-up circuit 121 is connected to a power supply of a normally-on region, a second end 1212 of the voltage pull-up circuit 121 is connected to a first output end 114 of the latch circuit 11, a first end 1222 1 of the voltage pull-down circuit 122 is connected to a second output end 115 of the latch circuit 11, and a second end 1222 of the voltage pull-down circuit 122 is grounded;
the detection circuit 10 is configured to detect whether the DVDD is powered down; the latch circuit 11 is configured to control the voltage at the first output terminal 114 of the latch circuit 11 and the voltage at the second output terminal 115 of the latch circuit 11 to be associated with the pull-up/pull-down circuit 12 after the DVDD power-down is detected by the detection circuit 10; the voltage pull-up circuit 121 is configured to pull up a voltage at the first output terminal 114 of the latch circuit 11 to be a power supply voltage in a normally-on region, so as to control the voltage at the first output terminal 114 of the latch circuit 11 and the voltage at the second output terminal 115 of the latch circuit 11 to enter a dead-lock state, and enable the first output terminal 114 of the latch circuit 11 to output a control signal for controlling the controlled circuit to enter a power-down mode; the voltage pull-down circuit 122 is configured to pull down the voltage of the second output terminal 115 of the latch circuit 11 to ground, so as to control the voltage of the first output terminal 114 of the latch circuit 11 and the voltage of the second output terminal 115 of the latch circuit 11 to enter a dead-lock state.
Specifically, since the detection circuit 10 is directly connected to the DVDD, the detection circuit 10 can detect whether the DVDD is powered down. When the detection circuit 10 detects the DVDD power-down, it can be known that the controlled circuit at the back end has entered an indeterminate state, and that the voltage at the power-down control input terminal 13 connected to the second input terminal 102 of the detection circuit 10 is low. Thus, the detection circuit 10 triggers the latch circuit 11 to control the voltage of the first output terminal 114 of the latch circuit 11 and the voltage of the second output terminal 115 of the latch circuit 11 in association with the pull-up/down circuit 12 through the voltage of the first output terminal 103 of the detection circuit 10 and the voltage of the second output terminal 104 of the detection circuit 10 and the voltage of the power-down control input terminal 13. Alternatively, the association referred to herein may be: after the voltage level of the first output terminal 114 of the latch circuit 11 and the voltage level of the second output terminal 115 of the latch circuit 11 are powered down by DVDD, the pull-up action of the voltage pull-up circuit 121 and the pull-down action of the voltage pull-down circuit 122 may be controlled, which may not be controlled by the power-down control input terminal 13. Optionally, the detection circuit 10 detects whether the DVDD is powered down, and may detect whether the DVDD is powered down through a simple switching tube, for example, a PMOS tube may detect whether the DVDD is powered down, which is low in cost.
Therefore, when the latch circuit 11 controls the voltage of the first output terminal 114 of the latch circuit 11 and the voltage of the second output terminal 115 of the latch circuit 11 to be associated with the pull-up/pull-down circuit 12, the voltage pull-up circuit 121 pulls up the voltage of the first output terminal 114 of the latch circuit 11, and the voltage pull-down circuit 122 pulls down the voltage of the second output terminal 115 of the latch circuit 11, thereby ensuring that the voltage of the first output terminal 114 of the latch circuit 11 and the voltage of the second output terminal 115 of the latch circuit 11 enter a dead-lock state. It should be noted that the "latch-up state" referred to herein means that the voltage pull-up circuit 121 and the voltage pull-down circuit 122 interact with each other, the voltage pull-up circuit 121 continuously pulls up the voltage of the first output terminal 114 of the latch circuit 11 to the power supply voltage of the normal power up region under the action of the voltage pull-down circuit 122 continuously pulling down the voltage of the second output terminal 115 of the latch circuit 11, and, the voltage pull-down circuit 122 continuously pulls down the voltage of the second output terminal 115 of the latch circuit 11 to the ground by the voltage pull-up circuit 121 continuously pulling up the voltage of the first output terminal 114 of the latch circuit 11, so that the latch circuit 11 enters the latch state, thereby causing the first output terminal 114 of the latch circuit 11 to output a control signal for controlling the controlled circuit into the Power Down mode by the control signal. The control signal has the same potential as the first output terminal 114 of the latch circuit 11, i.e. the first output terminal 114 of the latch circuit 11 is connected to the controlled circuit.
Optionally, the voltage pull-up circuit 121 may be any circuit having a pull-up function, and the specific form of the voltage pull-up circuit 121 is not limited in this embodiment as long as it can pull up the voltage at the first output terminal 114 of the latch circuit 11 to the power supply voltage in the normal power-up region; the voltage pull-down circuit 122 may be any circuit having a pull-down function, and the specific form of the voltage pull-down circuit 122 is not limited in this embodiment as long as it can pull down the voltage of the second output terminal 115 of the latch circuit 11 to a low potential.
In the mode control circuit provided in the embodiment of the present invention, after the detection circuit detects that the DVDD is powered Down, the voltages of the first output terminal of the latch circuit and the second output terminal of the latch circuit are automatically triggered to be associated with the pull-up and pull-Down circuit, so that the voltage of the first output terminal of the latch circuit and the voltage of the second output terminal of the latch circuit enter a deadlock state under the action of the pull-up and pull-Down circuit, and thus the first output terminal of the latch circuit outputs a control signal for controlling the controlled circuit to enter a Power-Down mode, and the controlled circuit is controlled to enter a Power-Down mode. The circuit provided by the embodiment of the invention can enable a controlled circuit such as an ADC circuit to enter a Power Down mode after being powered off under DVDD, thereby avoiding unnecessary Power consumption generated by the controlled circuit; in addition, the circuit provided by the embodiment of the invention can trigger the subsequent controlled circuit to automatically enter a Power Down mode after the DVDD is powered off only by connecting the corresponding detection circuit under the DVDD, and an additional trigger circuit such as a circuit for generating an isolation signal Viso is not required to be added outside the DVDD, so that the circuit cost and the circuit complexity are reduced; furthermore, the mode control circuit in the embodiment can be connected with a power supply of a normally-on region, and the reverse bias of a PN junction of a PMOS tube serving as a transmission gate is ensured, so that the leakage of the input end of the mode control circuit is avoided, and the reliability of the circuit is ensured.
Fig. 4 is a circuit diagram of a second embodiment of a mode control circuit according to the present invention. The present embodiment relates to a specific implementation of the detection circuit 10. On the basis of the above embodiment, the above detection circuit 10 may include a first switching tube M1 and an inverter 105. The first switch M1 may be a PMOS transistor. The aforementioned first input terminal 101 of the detection circuit 10 is connected to the digital power DVDD, the second input terminal 102 of the detection circuit 10 is connected to the power-down control input terminal 13, the first output terminal 103 of the detection circuit 10 is connected to the first control terminal 111 of the latch circuit 11, and the second output terminal 104 of the detection circuit 10 is connected to the second control terminal 112 of the latch circuit 11, and specifically includes: the gate of the first switch transistor M1 is connected to the power-down control input terminal 13, the source of the first switch transistor M1 is connected to the first control terminal 111 of the latch circuit 11, and the drain of the first switch transistor M1 is connected to the DVDD and the first input terminal 1051 of the inverter 105, respectively; the second input 1052 of the inverter 105 is connected to the power down control input 13, and the output 1053 of the inverter 105 is connected to the second control terminal 112 of the latch circuit 11.
Specifically, the inverter 105 in the present embodiment may be any inverter 105, for example, a logic not gate circuit, or a circuit with an inverting function built by corresponding switching tubes, as long as the inverter can invert the voltage at the power-down control input terminal 13. The inverter 105 in the detection circuit 10 shown in fig. 4 is only an example, and the form of the inverter 105 is not limited in the present invention.
Taking fig. 4 as an example, in fig. 4, the inverter 105 includes a second switching tube M2 and a third switching tube M3, the first input end 1051 of the inverter 105 is the source of the second switching tube M2, the second input end 1052 of the inverter 105 is the gate of the second switching tube M2 and the gate of the third switching tube M3 (the second input end 1052 of the inverter 105 and the second input end 102 of the detection circuit 10 are the same port), and the output end 1053 of the inverter 105 is the drain of the second switching tube M2 and the drain of the third switching tube M3 (the output end 1053 of the inverter 105 and the second output end 104 of the detection circuit 10 are the same port). Then, the "the drain of the first switch tube M1 is connected to the first input end 1051 of the inverter 105, the second input end 1052 of the inverter 105 is connected to the power-down control input end 13, and the output end 1053 of the inverter 105 is connected to the second control end 112 of the latch circuit 11" may specifically be: the drain of the first switching tube M1 is connected to the source of the second switching tube M2, the gate of the second switching tube M2 and the gate of the third switching tube M3 are respectively connected to the power-down control input terminal 13, the drain of the second switching tube M2 is connected to the drain of the third switching tube M3 and respectively connected to the second control terminal 112 of the latch circuit 11, and the source of the third switching tube M3 is grounded.
In the detection circuit 10 of fig. 4, after the DVDD is powered down, the voltage at the power-down control input terminal 13 is at the low potential, so that the low potential becomes the high potential after being inverted by the inverter 105 composed of the second switching tube M2 and the third switching tube M3, that is, both the drain of the second switching tube M2 and the drain of the third switching tube M3 are at the high potential, and the high potential is output to the first control terminal 111 of the latch circuit 11; after DVDD is powered down, the voltage (Vctrl) at the source of the first switching tube M1 is continuously pulled down and output to the second control terminal 112 of the latch circuit 11 at the rear end. Accordingly, the low voltage at the power-down control input terminal 13 is also output to the third control terminal 113 of the latch circuit 11. That is, the two output terminals of the detection circuit 10 and the power-down control input terminal 13 cooperate to trigger and control the operating state of the latch circuit 11 at the rear end.
Fig. 5 is a circuit diagram of a third embodiment of a mode control circuit according to the present invention. The present embodiment relates to a possible implementation of the voltage pull-up circuit 121 and the voltage pull-down circuit 122. Based on the embodiment shown in fig. 4, in fig. 5, the voltage pull-up circuit 121 includes a fourth switching tube M4, and the voltage pull-down circuit 122 includes a fifth switching tube M5, so that the first end 1211 of the voltage pull-up circuit 121 is a source of the fourth switching tube M4, the second end 1212 of the voltage pull-up circuit 121 is a drain of the fourth switching tube M4, the first end 1221 of the voltage pull-down circuit 122 is a drain of the fifth switching tube M5, and the second end 1222 of the voltage pull-down circuit 122 is a source of the fifth switching tube M5. Therefore, the first end 1211 of the voltage pull-up circuit 121 is connected to a power supply of a normally-on region, the second end 1212 of the voltage pull-up circuit 121 is connected to the first output end 114 of the latch circuit 11, the first end 1221 of the voltage pull-down circuit 122 is connected to the second output end 115 of the latch circuit 11, and the second end 1222 of the voltage pull-down circuit 122 is connected to ground, which may specifically be:
the source of the fourth switching tube M4 is connected to the power supply of the normally-on region, the gate of the fourth switching tube M4 is connected to the drain of the fourth switching tube M4, and the drain of the fourth switching tube M4 is connected to the first output terminal 114 of the latch circuit 11; the gate of the fifth switch transistor M5 is connected to the drain of the fifth switch transistor M5, the source of the fifth switch transistor M5 is grounded, and the drain of the fifth switch transistor M5 is connected to the second output terminal 115 of the latch circuit 11.
Specifically, in this embodiment, after the DVDD is powered down, the voltage of the first output terminal 114 of the latch circuit 11 and the voltage of the second output terminal 115 of the latch circuit 11 may be associated with the voltage pull-up circuit 121 and the voltage pull-down circuit 122, instead of being controlled by the voltage of the power-down control terminal, under the enabling action of the voltage of the detection circuit 10 and the power-down control input terminal 13 by the latch circuit 11. Therefore, when the fifth switch transistor M5 is turned on, the second output terminal 115 of the latch circuit 11 is turned on to ground, and then the voltage of the second output terminal 115 of the latch circuit 11 is low, the fifth switch transistor M5 functions to pull down the second output terminal 115 of the latch circuit 11; in addition, the fourth switch transistor M4 continuously pulls down the voltage at the second output terminal 115 of the latch circuit 11 by the fifth switch transistor M5, the fourth switch transistor M4 continuously pulls up the power supply voltage in the normally-on region of the voltage at the first output terminal 114 of the latch circuit 11, meanwhile, the fifth switch transistor M5 continues to pull up the voltage at the first output terminal 114 of the latch circuit 11 through the fourth switch transistor M4, and the fifth switch transistor M5 continues to pull down the voltage at the second output terminal 115 of the latch circuit 11 to ground, so as to work repeatedly, thereby bringing the latch circuit 11 into a dead-lock state, eventually ensuring that the voltage at the first output 114 of the latch circuit 11 is high, thereby outputting a control signal (i.e. a voltage signal at the Power Down Output terminal in fig. 5) for controlling the controlled circuit to enter the Power Down mode, so that the controlled circuit enters the Power Down mode after being powered off under DVDD.
Fig. 6 is a circuit diagram of a fourth embodiment of a mode control circuit according to the present invention. The present embodiment relates to a specific implementation of the mode control circuit. On the basis of the above embodiment, in fig. 6, the latch circuit 11 may include the first switch circuit 116, the second switch circuit 117, and the latch circuit 118; the first switch circuit 116 may include a sixth switch tube M6 and a seventh switch tube M7, the second switch circuit 117 may include an eighth switch tube M8 and a ninth switch tube M9, and the latch circuit 118 includes a tenth switch tube M10 and an eleventh switch tube M11.
The grid electrode of the sixth switching tube M6 and the grid electrode of the eighth switching tube M8 are respectively connected with the source electrode of the first switching tube M1, the source electrode of the sixth switching tube M6 is connected with the drain electrode of the seventh switching tube M7, the drain electrode of the sixth switching tube M6 is connected with the drain electrode of the tenth switching tube M10, the grid electrode of the seventh switching tube M7 is respectively connected with the drain electrode of the second switching tube M2 and the drain electrode of the third switching tube M3, and the source electrode of the seventh switching tube M7 is grounded; the source of the eighth switching tube M8 is connected with the drain of the ninth switching tube M9, the drain of the eighth switching tube M8 is connected with the drain of the eleventh switching tube M11, the gate of the ninth switching tube M9 is connected with the power-down control input terminal 13, and the source of the ninth switching tube M9 is grounded; a source of the tenth switching tube M10 and a source of the eleventh switching tube M11 are respectively connected to a power supply of the normally-on region, a gate of the tenth switching tube M10 is connected to a drain of the eleventh switching tube M11, a drain of the tenth switching tube M10 is respectively connected to a drain of the fourth switching tube M4 and a gate of the eleventh switching tube M11, and a drain of the eleventh switching tube M11 is connected to a drain of the fifth switching tube M5.
Optionally, the first switch circuit 116 may further include a twelfth switch tube M12, and the second switch circuit 117 may further include a thirteenth switch tube M13; the drain of the sixth switching tube M6 is connected to the drain of the tenth switching tube M10, specifically, the drain of the sixth switching tube M6 may be connected to the source of the twelfth switching tube M12, the drain of the twelfth switching tube M12 is connected to the drain of the tenth switching tube M10, the gate of the twelfth switching tube M12 is connected to the gate of the seventh switching tube M7, that is, the sixth switching tube M6 is connected to the tenth switching tube M10 through the twelfth switching tube M12; the drain of the eighth switch transistor M8 is connected to the drain of the eleventh switch transistor M11, which may be: the drain of the eighth switching tube M8 is connected to the source of the thirteenth switching tube M13, the drain of the thirteenth switching tube M13 is connected to the drain of the eleventh switching tube M11, and the gate of the thirteenth switching tube M13 is connected to the gate of the ninth switching tube M9, that is, the eighth switching tube M8 is connected to the eleventh switching tube M11 through the tenth switching tube M13.
Specifically, for example, the first switch circuit 116 includes a sixth switch tube M6, a seventh switch tube M7 and a twelfth switch tube M12, the second switch circuit 117 includes an eighth switch tube M8, a ninth switch tube M9 and a thirteenth switch tube M13, the first control end 111 of the latch circuit 11 is the gate of the sixth switch tube M6 and the gate of the eighth switch tube M8, the second control end 112 of the latch circuit 11 is the gate of the seventh switch tube M7 and the gate of the twelfth switch tube M12, the third control end 113 of the latch circuit 11 is the gate of the ninth switch tube M9 and the gate of the thirteenth switch tube M13, the first output end 114 of the latch circuit 11 is the drain of the fourth switch tube M4 and the drain of the tenth switch tube M10 (the drain of the first output end 114 of the latch circuit 11 is the X point 115 in fig. 6), and the drain of the second output end 114 of the tenth switch tube M10 (the drain of the latch circuit 11 is the eleventh switch tube M896 and the drain of the eleventh switch tube M8536 in fig. 6) A dot).
After the DVDD is powered down, the voltage (Vctrl) of the source of the first switching tube M1 is continuously pulled down, and since the gate of the sixth switching tube M6 and the gate of the eighth switching tube M8 are both connected to the source of the first switching tube M1, and the sixth switching tube M6 and the eighth switching tube M8 are both NMOS tubes, when the voltage (Vctrl) of the source of the first switching tube M1 is continuously pulled down, the voltages of the gate of the sixth switching tube M6 and the gate of the eighth switching tube M8 are both low, so that the sixth switching tube M6 and the eighth switching tube M8 are both turned off, and in addition, the first switching circuit 116 and the second switching circuit 117 are both turned off, and the first switching circuit 116 and the second switching circuit 117 are both in a high-impedance state, so that the fourth switching tube M4 and the fifth switching tube M5 are pulled down. That is, since the first switch circuit 116 and the second switch circuit 117 are both in a high-impedance state, the pull-up and pull-down actions of the fourth switch transistor M4 and the fifth switch transistor M5 are stronger than those of the first switch circuit 116 and the second switch circuit 117, and therefore, the latch circuit 118 formed by the tenth switch transistor M10 and the eleventh switch transistor M11 can be effectively locked by the fourth switch transistor M4 and the fifth switch transistor M5. At this time, the potentials at the point X and the point Y are controlled by the fourth switching tube M4 and the fifth switching tube M5.
The latch circuit 118 is locked as described herein, and can be explained in two ways: when DVDD is powered down, the voltage at the power-down control input terminal 13 and the voltage at the DVDD are both pulled down to the vicinity of GND (ground), so that the voltage states of the first output terminal 114 of the latch circuit 11 and the second output terminal 115 of the latch circuit 11 are uncertain, that is, the potential at the point X and the potential at the point Y are actually unknown states, and it is assumed that two states are provided:
the first method comprises the following steps: suppose that after the DVDD is powered down, the X point is at a low potential and the Y point is at a high potential.
When the point X is a low potential, the fourth switching tube M4 is turned on, pulling up the potential of the point X to the power voltage of the normally-on region, and when the point Y is a high potential, the fifth switching tube M5 is turned on, so that the potential of the point Y is pulled down to the ground by the fifth switching tube M5, and at this time, the potential of the point Y becomes a low potential. Since the gate of the tenth switching transistor M10 is connected to the point Y, the gate voltage of the tenth switching transistor M10 is low (the tenth switching transistor M10 is a PMOS transistor), so that the tenth switching transistor M10 is turned on, and the potential at the point X is continuously pulled up to the power supply voltage of the normally-on region (at this time, the fourth switching transistor M4 is turned off); since the gate of the eleventh switch transistor M11 is connected to the X point, at this time, the voltage of the gate of the eleventh switch transistor M11 is at a high potential (the eleventh switch transistor M11 is a PMOS transistor), so the eleventh switch transistor M11 is turned off, the Y point potential is continuously pulled Down by the fifth switch transistor M5, and the X point potential is continuously pulled up again, and the latch circuit 118 enters a dead-lock state, so that the potential at the X point is ensured to be high, the potential at the Y point is ensured to be low, and further the control signal (Power Down Output) Output by the X point is at a high potential, and the controlled circuit is controlled to enter a Power Down mode.
And the second method comprises the following steps: suppose that after the DVDD is powered down, the X point is at a high potential and the Y point is at a low potential.
When the point X is high potential, the fourth switching tube M4 is turned off, when the point Y is low potential, the fifth switching tube M5 is also turned off, at the moment, the fourth switching tube M4 loses the pull-up effect, the fifth switching tube M5 loses the pull-down effect, at the moment, the eleventh switching tube M11 is turned off, the tenth switching tube M10 is turned on, the potential of the point X is continuously high potential, the potential of the point Y is always low potential, and at the moment, the latch also enters a locking state.
In any of the latch states, the potential of the first output terminal 114 of the latch circuit 11 is always high, and the potential of the second output terminal 115 of the latch circuit 11 is always low, so that the first output terminal 114 of the latch circuit 11 is enabled to output the control signal for controlling the controlled circuit.
In addition, when the fourth switching tube M4 and the fifth switching tube M5 pull the potential (point X) of the first output terminal 114 of the latch circuit 11 and the potential (point Y) of the second output terminal 115 of the latch circuit 11 up and down to the right respectively, that is, the potential at point X is 1 and the potential at point Y is 0, the source of the fourth switching tube M4 and the drain of the fourth switching tube M4 are equal to each other, so that no leakage current is generated, and the source of the fifth switching tube M5 and the drain of the fifth switching tube M5 are also equal to each other, so that no leakage current is generated.
On the other hand, the mode control circuit according to the embodiment of the present invention does not affect the normal operation of the controlled circuit, and is specifically described in two cases:
the first method comprises the following steps: when the DVDD is charged, the voltage at the Power-Down control input terminal 13 is a high potential, and the controlled circuit is controlled to enter a Power Down mode.
Since the gate of the ninth switching tube M9 and the gate of the thirteenth switching tube M13 are connected to the power-down control input terminal 13 (both the ninth switching tube M9 and the thirteenth switching tube M13 are NMOS tubes), the ninth switching tube M9 and the thirteenth switching tube M13 are turned on; meanwhile, the voltage at the power-down control input terminal 13 passes through the inverter 105 formed by the second switch transistor M2 and the third switch transistor M3, so that the voltages at the gates of the seventh switch transistor M7 and the twelfth switch transistor M12 are at a low potential (the seventh switch transistor M7 and the twelfth switch transistor M12 are NMOS transistors), and thus the seventh switch transistor M7 and the twelfth switch transistor M12 are turned off. When DVDD is charged, the voltages at the gates of the sixth switching tube M6 and the eighth switching tube M8 are high (both the sixth switching tube M6 and the eighth switching tube M8 are NMOS tubes), and therefore, the sixth switching tube M6 and the eighth switching tube M8 are turned on. That is, the first switch circuit 116 is turned off to be in a high impedance state, and the second switch circuit 117 is turned on, which results in the potential at the Y point being at a low potential (the fifth switch tube M5 is turned off); and as the potential at the point Y causes the tenth switching tube M10 to be turned on, the potential at the point X is a high potential (at this time, the fourth switching tube M4 is turned off), that is, the pull-up and pull-down actions of the fourth switching tube M4 and the fifth switching tube M5 are both disabled, and the potential at the point X is influenced by the voltage at the power-down control input terminal 13. That is, when the voltage at the Power-Down control input terminal 13 is high, the potential at the point X is high, and a high-level control signal is output, so that the controlled circuit enters the Power Down mode. That is, the fourth switching tube M4 and the fifth switching tube M5 do not affect the normal control of the whole circuit.
And the second method comprises the following steps: when the DVDD is charged, the voltage at the power-down control input terminal 13 is at a low potential, and the controlled circuit is controlled to enter a working mode.
Since the gate of the ninth switching tube M9 and the gate of the thirteenth switching tube M13 are connected to the power-down control input terminal 13 (both the ninth switching tube M9 and the thirteenth switching tube M13 are NMOS tubes), the ninth switching tube M9 and the thirteenth switching tube M13 are turned off; meanwhile, the voltage at the power-down control input terminal 13 passes through the inverter 105 formed by the second switch transistor M2 and the third switch transistor M3, so that the voltages at the gates of the seventh switch transistor M7 and the twelfth switch transistor M12 are high (the seventh switch transistor M7 and the twelfth switch transistor M12 are NMOS transistors), and thus the seventh switch transistor M7 and the twelfth switch transistor M12 are turned on. When DVDD is charged, the voltages at the gates of the sixth switching tube M6 and the eighth switching tube M8 are high (both the sixth switching tube M6 and the eighth switching tube M8 are NMOS tubes), and therefore, the sixth switching tube M6 and the eighth switching tube M8 are turned on. That is, the first switch circuit 116 is turned on, the second switch circuit 117 is turned off to a high impedance state, which results in the potential at the point X being at a low potential (the fourth switch tube M4 is turned on), but since the impedance of the fourth switch tube M4 is greater than that of the first switch circuit 116, the pull-up action of the fourth switch tube M4 is less than that of the first switch circuit 116, so the potential at the point X remains at a low potential; and since the eleventh switch tube M11 is turned on by the low potential at the point X, the potential at the point Y becomes high, and the fifth switch tube M5 is turned on at this time, and the potential at the point Y is pulled down to the low potential again. At this time, the potential of the point X is influenced by the voltage of the power-down control input terminal 13, and a low-potential control signal is ensured to be output, so that the controlled circuit enters a working mode, that is, the normal operation of the whole circuit is not influenced by the fourth switching tube M4 and the fifth switching tube M5.
In addition, when the DVDD charging controlled circuit normally operates (i.e., the point X is a low potential, and the point Y is a high potential), the fourth switching tube M4 and the fifth switching tube M5 are both turned on, and although a small amount of leakage current is generated, the leakage current is generated when the ADC normally operates, and therefore the ADC is not affected to enter the Power Down mode.
In the mode control circuit provided in the embodiment of the present invention, after detecting that the DVDD is powered Down, the voltage of the first output terminal of the latch circuit and the voltage of the second output terminal of the latch circuit enter a dead-lock state under the action of the pull-up and pull-Down circuit, so that the first output terminal of the latch circuit outputs a control signal for controlling the controlled circuit to enter a Power-Down mode, and the controlled circuit is controlled to enter a Power Down mode. The circuit provided by the embodiment of the invention can enable a controlled circuit such as an ADC circuit to enter a Power Down mode after being powered off under DVDD, thereby avoiding unnecessary Power consumption generated by the controlled circuit and saving the overall Power consumption overhead of a system; in addition, the circuit provided by the embodiment of the invention can automatically trigger the subsequent controlled circuit to automatically enter a Power Down mode after the DVDD is powered off only by connecting the corresponding detection circuit under the DVDD under the state without an external control signal, and an additional trigger circuit is not required to be added outside the DVDD, so that the circuit cost and the circuit complexity are reduced; furthermore, the mode control circuit provided by the embodiment of the invention does not generate leakage current under the condition of power supply under DVDD, and ensures the reliability of the whole circuit.
Fig. 7 is a schematic diagram of an embodiment of an apparatus according to an embodiment of the present invention. As shown in fig. 7, the apparatus may include a controlled circuit 20 and the mode control circuit 21 in the above embodiment, wherein the mode control circuit 21 is connected to the controlled circuit 20 and is used for controlling the controlled circuit 20 to automatically enter the PowerDown mode after being powered down by DVDD. Alternatively, the controlled circuit 20 may be the ADC circuit in fig. 2, or may be a dual power supply circuit, or may be other circuits to be controlled.
For the device provided in the embodiment of the present invention, specific processes and advantageous effects of controlling the controlled circuit to automatically enter the Power Down mode after being powered off from the DVDD may be found in the above embodiment of the mode control circuit, and details are not described herein.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (11)
1. A mode control circuit, comprising: the latch circuit comprises a first control end, a first output end and a second output end, and the pull-up and pull-down circuit comprises a voltage pull-up circuit and a voltage pull-down circuit; wherein,
the detection circuit is coupled with a first control end which is connected with a digital power supply DVDD and the latch circuit, a first output end of the latch is coupled with the voltage pull-up circuit, and a second output end of the latch circuit is coupled with the voltage pull-down circuit;
the detection circuit is configured to control the first control terminal of the latch circuit when the DVDD is powered down, so that the first output terminal of the latch circuit is pulled up to a high level by the voltage pull-up circuit, and the second output terminal of the latch circuit is pulled down to a low level by the voltage pull-down circuit.
2. The circuit of claim 1, wherein the detection circuit comprises a first switch tube, a drain of the first switch tube is coupled to the DVDD, and a source of the first switch tube is coupled to the first control terminal of the latch circuit;
when the DVDD is powered down, the source voltage of the first switching tube is pulled down, so that the first control end of the latch circuit is at a low level.
3. The circuit of claim 1 or 2, wherein the latch control circuit comprises: a first switch circuit and a second switch circuit, a first output terminal of the latch circuit being grounded through the first switch circuit, a second output terminal of the latch circuit being grounded through the second switch circuit, a first control terminal of the latch circuit being coupled to the first switch circuit and the second switch circuit;
when the first control end of the latch circuit is at a low level, the first switch circuit and the second switch circuit are both switched off, so that the voltage of the first output end of the latch circuit is pulled up to the power supply voltage of a normally-on region by the voltage pull-up circuit, and the second output end of the latch circuit is pulled down to a low level by the voltage pull-down circuit.
4. The circuit of claim 3, wherein the first switch circuit comprises a sixth switch tube, the second switch circuit comprises an eighth switch tube, the sixth switch tube and the eighth switch tube are both NMOS tubes, the first control terminal of the latch circuit is coupled to the gates of the sixth switch tube and the eighth switch tube, and the sixth switch tube and the eighth switch tube are both turned off when the first control terminal of the latch circuit is at a low level.
5. The circuit of claim 3 or 4, wherein the detection circuit further comprises: the first switching circuit further comprises a seventh switching tube and a twelfth switching tube, and the second switching circuit further comprises a ninth switching tube and a thirteenth switching tube;
the input end of the phase inverter is connected with the power-down control input end, the output end of the phase inverter is coupled with the grids of the seventh switching tube and the twelfth switching tube, and the power-down control input end is coupled with the grids of the ninth switching tube and the thirteenth switching tube.
6. The circuit according to claim 5, wherein the inverter comprises a second switching tube and a third switching tube, a source electrode of the second switching tube is connected with a drain electrode of the first switching tube, a gate electrode of the second switching tube is connected with a gate electrode of the third switching tube and leads out an input end of the inverter, a drain electrode of the second switching tube is connected with a drain electrode of the third switching tube and leads out an output end of the inverter, and a source electrode of the third switching tube is grounded.
7. The circuit of claim 6, wherein the source of the seventh switching tube is grounded, the drain of the seventh switching tube is connected to the source of the sixth switching tube, the drain of the sixth switching tube is connected to the source of the twelfth switching tube, and the drain of the twelfth switching tube is connected to the first output terminal of the latch circuit;
the source electrode of the ninth switching tube is grounded, the drain electrode of the ninth switching tube is connected with the source electrode of the eighth switching tube, the drain electrode of the eighth switching tube is connected with the source electrode of the thirteenth switching tube, and the drain electrode of the thirteenth switching tube is connected with the second output end of the latch circuit.
8. The circuit according to any one of claims 1 to 7, wherein the voltage pull-up circuit comprises a fourth switching tube, the voltage pull-down circuit comprises a fifth switching tube, a source electrode of the fourth switching tube is connected with a power supply of the normally-on region, and a grid electrode of the fourth switching tube is connected with a drain electrode of the fourth switching tube and connected to the first output end of the latch circuit;
the source electrode of the fifth switching tube is grounded, and the grid electrode of the fifth switching tube is connected with the drain electrode of the fifth switching tube and connected to the second output end of the latch circuit.
9. The circuit according to any one of claims 1 to 8, wherein the latch circuit further comprises a latch circuit, the latch circuit comprises a tenth switching tube and an eleventh switching tube, a source of the tenth switching tube and a source of the eleventh switching tube are respectively connected with a power supply of a normally-on region, a gate of the tenth switching tube is connected with a drain of the eleventh switching tube, a gate of the eleventh switching tube is connected with a drain of the tenth switching tube, a first output end of the latch circuit is led out from the drain of the tenth switching tube, and a second output end of the latch circuit is led out from the drain of the eleventh switching tube.
10. An apparatus comprising controlled circuitry, further comprising: a mode control circuit as claimed in any one of claims 1 to 9;
the mode control circuit is connected with the controlled circuit.
11. The apparatus of claim 10, the controlled circuit comprising: an analog-to-digital converter (ADC) circuit or a dual power supply circuit.
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| CN111179868A (en) * | 2020-01-21 | 2020-05-19 | 南京中电熊猫平板显示科技有限公司 | Reset signal potential maintaining circuit and method |
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| JP2003338747A (en) * | 2003-06-30 | 2003-11-28 | Yamaha Corp | Semiconductor integrated circuit |
| US20060018146A1 (en) * | 2004-07-26 | 2006-01-26 | Lai Fang-Shi | Power management circuit and memory cell |
| KR20080067039A (en) * | 2007-01-15 | 2008-07-18 | 삼성전자주식회사 | Level shifter for low power consumption |
| JP2014187508A (en) * | 2013-03-22 | 2014-10-02 | Lapis Semiconductor Co Ltd | Semiconductor device and power-down control method |
| CN104638887A (en) * | 2015-01-30 | 2015-05-20 | 北京时代民芯科技有限公司 | Output driving circuit capable of realizing output high level conversion |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111179868A (en) * | 2020-01-21 | 2020-05-19 | 南京中电熊猫平板显示科技有限公司 | Reset signal potential maintaining circuit and method |
| CN111179868B (en) * | 2020-01-21 | 2021-11-23 | 南京京东方显示技术有限公司 | Reset signal potential maintaining circuit and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110729999B (en) | 2024-04-09 |
| CN105846821B (en) | 2019-09-20 |
| CN105846821A (en) | 2016-08-10 |
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