CN103986241B - The integrated circuit of digital power lock control - Google Patents

The integrated circuit of digital power lock control Download PDF

Info

Publication number
CN103986241B
CN103986241B CN201410246672.0A CN201410246672A CN103986241B CN 103986241 B CN103986241 B CN 103986241B CN 201410246672 A CN201410246672 A CN 201410246672A CN 103986241 B CN103986241 B CN 103986241B
Authority
CN
China
Prior art keywords
numerical value
control
signal
voltage
order
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410246672.0A
Other languages
Chinese (zh)
Other versions
CN103986241A (en
Inventor
詹姆斯.R.隆柏格
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Via Technologies Inc
Original Assignee
Via Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/202,313 external-priority patent/US9450580B2/en
Application filed by Via Technologies Inc filed Critical Via Technologies Inc
Publication of CN103986241A publication Critical patent/CN103986241A/en
Application granted granted Critical
Publication of CN103986241B publication Critical patent/CN103986241B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Power Sources (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The integrated circuit of a kind of digital power lock control.This digital power brake system performs power gating, and retain voltage level in order to the voltage of a lock control supply bus is reduced to a state, state retains the digital state that voltage level maintains a functional circuit, and reduces leakage current.Digital power brake system comprises multiple lock control device and a power gating system.Each lock control device has multiple current terminal and a control end.Current terminal is coupled to integration supply bus and lock control supplies between bus.Control end controlled by the position of a digital control numerical value.Power gating system adjusts numerical digit continuously and controls numerical value, retains voltage level in order to the voltage of lock control supply bus is reduced to state.Adjustment gain and/or adjustment cycle may be changed, as reached special value at digital control numerical value or reaching specific voltage level at the voltage of lock control supply bus.In ad hoc structure, by the many parameters of programming, in order to reach the function of adjustment.

Description

The integrated circuit of digital power lock control
Technical field
The present invention relates to a kind of power gating, in particular to a kind of lock control service voltage digitally controlling a circuit, this circuit comprises fast and gently downgrades service voltage, the service voltage downgraded is enough to make the state of this circuit maintenance itself and reduce leakage current, and under recovery operation, fast and voltage of gently increasing supply.
Background technology
The power that complementary MOS (COMS) circuitry consumes is less, and more intensive compared to the integrated circuit of other pattern, therefore CMOS technology becomes type main in digital circuit.Cmos circuit has the combination of the device (NMOS) of N-type passage and the device (PMOS) of P type passage or multiple transistor, according to the difference of design, size, material and processing procedure, the critical voltage that the grid of each transistor is corresponding with having between source electrode.The design and manufacture technology of integrated circuit decreases operating voltage and plant bulk.When plant bulk and voltage level reduce, the passage length of each device and oxidated layer thickness all can be reduced.In manufacture process, if when changing grid material, can critical voltage be reduced, but can increase leakage current.When leakage current refers to that the voltage when between grid and source electrode is less than the critical voltage of CMOS device, the streaming current between drain electrode and source electrode.In known dynamic environment framework, leakage current causes 15% ~ 30% of total-power loss.
In the specific time cycle and/or on other occasions, the local circuit of cmos circuit or cmos circuit may not need normal work, thus idle.Because the leakage current of flowing consumes valuable power, therefore, give idle circuit be really waste and inefficent if maintain full power supply.For CMOS technology, by the voltage that base stage (bulk) voltage or matrix (body) that reduce CMOS device connect, leakage current can be reduced.But for the CMOS technology of current 40nm and 28nm, known method cannot reduce leakage current effectively.
Summary of the invention
The invention provides the integrated circuit of a kind of digital power lock control, it comprises an integration supply bus, lock control supply bus, a functional circuit, at least one programmable device and a digital power control system.Functional circuit has a voltage supply input, in order to couple lock control supply bus.Programmable device stores at least one programming Control parameter.Digital power control system comprises lock control device and a power gating system.Each lock control device have a current terminal to and a control end.Each current terminal to be coupled to integrate supply bus and lock control supply between bus.The digital control numerical value of power gating Systematical control one, in order to control lock control device.Power gating system controls numerical value by adjustment numerical digit, to perform a power gating operation, in order to make the voltage of lock control supply bus relevant with integrating the voltage supplying bus.Operate by programming Control parameter adjustment power gating.
Power gating system may comprise a power gating device.This power gating device, according to programming Control parameter, is selected in many difference gain values, in order under power gating, reduces the voltage of lock control supply bus.Power gating system may comprise a power gating device.Power gating device, according to programming Control parameter, is selected in many totalling gain values, in order under power gating, increases the voltage of lock control supply bus.Power gating system may comprise a power gating device.Power gating device, according to programming Control parameter, recovers to select in gain values at many totallings, in order under recovery operation, increases the voltage of lock control supply bus.
Power gating system may comprise a power gating device.Power gating device, according to programming Control parameter, is selected in much stopping numerical value, when digital control numerical value reaches a selection stopping numerical value, stops a recovery operation.
Power gating system may comprise a clock controller.Clock controller provides a clock signal, controls a resize ratio of numerical value in order to control figure.Clock controller according to programming Control parameter, may change adjustment and compares, and in order to when the voltage of lock control supply bus reaches each voltage level, changes the cycle of clock signal.Clock controller according to programming Control parameter, may select a fixed cycle of clock signal, in order under a recovery operation, increases the voltage of lock control supply bus.
Power gating system may comprise a digital adjuster.Many continuous setup cycles each after, digital adjuster whole in-one digital adjustment numerical value and digital control numerical value, in order to change the voltage of lock control supply bus.Power gating system may also comprise a gain selection logic.Gain selection logic, according to programming Control parameter, selects one as numeral adjustment numerical value from many displacement result of digital control numerical value.Gain selection logic may comprise a difference and select logic and to add up selection logic.Under power gating, difference selects logic according to a difference gain values able to programme, selects one to select different difference adjustment numerical value as one from many displacement result of digital control numerical value.Under power gating, add up and select logic according to a totalling gain values able to programme, from many displacement result of digital control numerical value, select one to select to add up adjustment numerical value as one.Gain selection logic may comprise a recovery gain selection logic.Under a recovery operation, recover gain selection logic according to a recovery gain values able to programme, from many displacement result of digital control numerical value, select one to select to add up adjustment numerical value as one.
Power gating system may comprise a clock generator.Clock generator produces a clock signal, and in order to control the continuous setup cycle, the cycle of clock signal depends on a time domination number value.Power gating system may comprise a temporal decoder.Temporal decoder, according to programming Control parameter, provides and regulation time control numerical value.Temporal decoder may comprise a transducer and a clock cycle selector.Digital control numerical value is changed into time controling numerical value by transducer, and when digital control numerical value is adjusted, regulation time controls numerical value.When the voltage of lock control supply bus reaches a voltage level, clock period selection device, according to programming Control parameter, selects one from many displacement result of time controling numerical value.When digital control numerical value reaches each of much programming numerical value, temporal decoder may control numerical value by regulation time, and programming numerical value depends on programming Control parameter.Temporal decoder may comprise a transducer, a clock shifter and a clock cycle selector.Transducer converts digital control numerical value to time controling numerical value, and when digital control numerical value is adjusted, regulation time controls numerical value.Clock shifter, according to digital control numerical value and programming Control parameter, provides at least shift value.When digital control numerical value reaches shift value, clock period selection device displacement time controls numerical value.
When time controling numerical value during action according to programming Control parameter, may be maintained a fixed numbers, make clock signal have a fixed cycle by temporal decoder.Temporal decoder, according to programming Control numerical value, selects one from multiple fixed cycle numerical value.
Programmable device may be made up of a fuse array or a memory.Controling parameters is programmed to fuse array or memory.One power on or boundary scan time, programmable memory.
Accompanying drawing explanation
Fig. 1 is that one of many core microprocessors of the present invention may embodiment.
Fig. 2 is that the kernel of Fig. 1 of the present invention may embodiment with one of corresponding power supply brake system.
Fig. 3 is that one of gating circuit of the present invention may embodiment.
Fig. 4 is that one of the side block of Fig. 3 of the present invention may embodiment.
Fig. 5 is that one of the lock square of the high-order portion of the processing controls word of Fig. 4 of the present invention may embodiment.
Fig. 6 is that one of the lock square of the low portion of the processing controls word of Fig. 4 of the present invention may embodiment.
Fig. 7 A and Fig. 7 B is that one of the power gating system of Fig. 2 of the present invention may embodiment.
Fig. 8 is that one of the power gating device of Fig. 7 A of the present invention and Fig. 7 B may embodiment.
Fig. 9 A and Fig. 9 B is that one of the increment control algorithm word adjuster of Fig. 8 of the present invention may embodiment.
Figure 10 A and Figure 10 B is that one of the integral traffic control word adjuster of Fig. 8 of the present invention may embodiment.
Figure 11 is that one of the control word logic of Fig. 8 of the present invention may embodiment.
Figure 12 is that one of the temporal decoder of Fig. 7 B of the present invention may embodiment.
Figure 13 is that one of the clock shifter of Figure 12 of the present invention may embodiment.
Figure 14 is that one of the default clock selection circuit of Figure 12 of the present invention may embodiment.
Figure 15 is that one of the fixing recovered clock selection circuit of Figure 12 of the present invention may embodiment.
Figure 16 A and Figure 16 B is that one of the clock period selection device of Figure 12 of the present invention may embodiment.
Figure 17 is the possibility embodiment additionally adjusting gain according to critical voltage of the present invention, and wherein critical voltage is represented by a comparison signal.
[symbol description]
100: microprocessor; 101 ~ 104: kernel;
105 ~ 108: power supply brake system; 109: integrate supply bus;
110: power-supply controller of electric; 112: mode adjustment square;
114: fuse array; 116: memory;
201: power gating system; 206: lock control supply bus;
301: side block; 401,403: lock square;
EESDCLK: clock signal; PGATE1: power gating signal;
FSB<3:0>: Front Side Bus numerical value; PG_KILL_CORE1: signal;
PGOOD1: power supply ready signal; PGATE<1:4>: control signal group;
701: recover logic; 703:OR logic;
705: voltage compare group; 707: clock generator;
709: frequency divider; 711: clock selecting square;
712: temporal decoder; 713: power gating device;
PG16: position; CMP1 ~ CMPN: comparative result;
PG_TIME<19:0>: time numerical value; CB<15:0>: anti-phase removing numerical value;
S<15:0>: setting numerical value; D<15:0>: value data;
CB: anti-phase removing input; S: set input;
D: data input pin; CK: input end of clock;
801: increment control algorithm word adjuster; 803: integral traffic control word adjuster;
805: Parasites Fauna; 807: control word logic;
901: current limliting; 913,1005: adder;
905: subtracter; 911: add value decoder;
1001,1109: bank of latches; 1017:V_DOWN decoder;
1201: single focus decoder; 1203: clock shifter;
1205: preset clock selection circuit; 1209: clock period selection device;
1207: fixing recovered clock selection circuit;
PGATE1 ~ PGATE4: power gating signal;
VDD, VSS, VDD0, VSS0, VDD1: voltage;
PG_VREF<1:N>: set of reference voltages;
V_DOWN<4:0>, PG_KILL_CORE<1:4>: signal group;
PWR_GOOD, PGOOD<1:4>, PG_FU_X, HIER, HIERB, HIGH, RESUME, KILLB, GATE, GATEB, HIGHB: signal;
PG_GATE_TOP20, PG_GATE_LEFT203, PG_GATE_RIGHT204, PG_GATE_BOTTOM205: gating circuit
PG_CNTRL<16:0>, PG<15:0>: control word;
VDD1_FB, I<16:0>, IN, I<12:0>, I<16:13>, 1, S, 0: input;
PG_FU_ADD_GN, PG_FU_SUB_GN, PG_FU_CONST_RES_CLK, PG_FU_RESUME_STOP, OPB<15:0>, PGTWO, PGTHREE, PGFOUR, PGFIVE and PGSIX, <*6>VSS0, PG<15:7>, PGSIX, <*5>VSS0, PG<15:5>, SUB<15:0>, FSUB<15:0>, <*2>VSS0:PG<15:3 >:PGTWO, <*3>VSS0:PG<15:4 >:PGTHREE, <*4>VSS0:PG<15:5 >:PGFOUR, <*5>VSS0:PG<15:6 >:PGFIVE, DOP<15:0>, VOP<14:0>:VDD0, DOP<14:0>:VDD0, VOP<13:0>:<*2Gre atT.GreaT.GTVDD0, DOP<13:0>:<*2Gre atT.GreaT.GTVDD0, <*4>VSS0:<*12Gre atT.GreaT.GTGATEB, VOP<15:0>, OOPB<15:0>, VSS0:VOP<15:1>, <*3>VSS0:PGT<15: 0>:VSS0, <*2>VSS0:PGT<15: 0>:<*2>VSS0, DTIME<19:0>, PG2T<19:0> ~ PG8T<19:0>, <*13>VDD0:PGTIMEBLEssT.LTssT. LT6:3>:<*3>VDD0, SHIFTVAL1 ~ SHIFTVAL4: numerical value,
PG_FU_ENT<10:5>, PG_FU_RESUME_GN<1:0>, PG_FU_RES_PER<1:0>: numerical value group;
PG_CNTRLA<16:0>, PG_CNTRLB<16:0>: buffering result;
O<16:0>, OUT, O<12:0>, O<16:13>: output;
I<16> ~ I<0>: control buffering result;
501: group of buffers;
O<16> ~ O<0>: Buffer output control level;
502,504,506,508,602:PMOS transistor group;
501: buffer;
503,505,507,601,909,1015,1003,1101,812,1111,1113,1121,1211,1301,1303,1501,1503: inverter group;
CLK20, C20NS, C40NC, C2.6MS: clock signal;
903,907,915,1007,1009,1011,1107,1413,1601,1603,1605,1607,1609,1611,1613,1615,1617,1701,1703: multiplexer;
917,1119,1602,1604,1606,1608,1610,1612,1614,1616:AND door;
1115,1313,1315,1317,1505,1507,1509,1511,1409,1411: NAND door;
919,1013,1103,1105,1117,1123,1305,1307,1309,1311,1319,1321,1323,1325,1327,1329,1401,1403,1405,1407:NOR door.
Embodiment
It is known that utilize analogue technique to carry out power gating.When carrying out full power gating, known power gating fully removes source voltage, thus loses the data that store of circuit and logic state, the data of the memory of such as circuit or registers storage.In many circuit frameworks, the state of required stick holding circuit or data, can carry out well recovery operation after a while.
In order under full power gating, the state of holding circuit, the data that circuit can be stored or information reproduction are in another storage device or memory, and it when circuit enters power gating, can maintain data.Mentioned herein to " state " refer to any information that circuit stores or data, circuit has static state or dynamic apparatus, as register, trigger, latch, dynamic storage device ... etc..When powering on, before carrying out recovery operation, first the data stored in advance are deposited in telegram in reply road.Above-mentioned storage action in order to store data, as the cache on chip ... etc., but when removing power supply, power supply or its data stored of storage device must be removed.In order to storage information before entering power gating, and recover information under recovery operation, therefore, the much time must be spent, therefore from the angle performed, the cost of storage and the information of recovery is quite high.Under large-sized circuit, as the processor of a micro-processor kernel, a System on Chip/SoC ... etc., the price of known power gating is expensive especially.
The present invention understands known power gating technology and improper.Therefore propose a kind of digital power control technology, it has state recovery function, and the service voltage of a circuit is reduced to a final level, and it is still enough to reserved state and reduces leakage current.New control system and a method, in order under power gating, utilize a digital method, makes the level of distributing service voltage equal a final voltage level.Under power gating, numerical control system merges integrates electric voltage displacement, in order to the variable quantity of the voltage according to lock control supply bus, temporarily increases the voltage of lock control supply bus, retains voltage level with the voltage avoiding lock control to supply bus lower than a state.Under recovery operation, as recovered instruction according to one, service voltage level is also little by little reverted to the normal operation voltage level of itself by numerical control system and method.In addition, numerical control system and method may comprise at least one programmable parameter, in order under power gating and recovery operation, and the carrying out of control operation.In the present embodiment, because information is stored in dynamic device, as register, trigger, latch, dynamic storage device ... etc., therefore, power supply can be stored, and can be returned to the state before entering power gating.Also full power gating can be realized.Full power gating operation may have at least one program parameters.
Fig. 1 is core microprocessor more than one one possibility embodiment of the present invention.Microprocessor 100 comprises four kernel 101-104.Kernel 101-104 couples a corresponding power supply brake system separately, as 105 ~ 108.Although Fig. 1 only presents kernel 101 ~ 104, in other embodiments, the quantity of kernel may be greater than or less than 4.In this enforcement, each kernel may be a micro-processor kernel, but and is not used to limit the present invention.Though herein for micro-processor kernel, apprehensible, other needs any circuit pattern of power gating or function all can use power supply brake system.Microprocessor 100 is incorporated into an integrated circuit (IC), semiconductor chip ... etc., and other circuit (not shown) may be had.
Power supply brake system 105 ~ 108 receives a power gating signal respectively, as PGATE1, PGATE2, PGATE3 and PGATE4, wherein power gating signal PGATE1, PGATE2, PGATE3 and PGATE4 are referred to as power gating signal group PGATE<1:4>.Each power gating signal carries out power gating in kernel 104 ~ 104 independently.In a possibility embodiment, power gating can be carried out to kernel 101 ~ 104 simultaneously.For example, power gating signal PGATE1, PGATE2, PGATE3 and PGATE4 may replace by the single overall control signal or control.Microprocessor 100 receives an external power source supply voltage, and it is between source voltage VDD and VSS, and wherein source voltage VSS is suitable reference voltage level, such as a ground connection.Source voltage VDD and VSS is as corresponding integration supply voltage VDD0 and VSS0.Power supply brake system 105 ~ 108 receiver voltage VDD0 and VSS0.Kernel 101 ~ 104 receiver voltage VSS0.Voltage VDD0 is supplied to a conductive plate or conductor group, and conductor group forms an integration supply bus 109.
As shown in the figure, supply voltage VDD0 is converted to one first lock control service voltage VDD1 by power supply brake system 105.Kernel 101 receives the first lock control service voltage VDD1.Supply voltage VDD0 is converted to one second lock control service voltage VDD2 by power supply brake system 106.Kernel 102 receives the second lock control service voltage VDD2.Supply voltage VDD0 is converted to one the 3rd lock control service voltage VDD3 by power supply brake system 107.Kernel 103 receives the 3rd lock control service voltage VDD3.Supply voltage VDD0 is converted to one the 4th lock control service voltage VDD4 by power supply brake system 108.Kernel 104 receives the 4th lock control service voltage VDD4.
When kernel 101 ~ 104 operates in a full electric source modes, corresponding power gating signal PGATE1 ~ PGATE4 will being disabled, and P type or the P channel element of full number of power sources are preset in corresponding power supply brake system 105 ~ 108 conducting or activation one, are called power supply brake gear herein.Preset full number of power sources be enough to effectively by corresponding lock control service voltage VDD1 ~ VDD4 strangulation at VDD0, in order to minimize the impedance path between voltage VDD0 and corresponding lock control service voltage, contribute to providing voltage to give selected kernel.
In a possibility embodiment, P type power supply brake gear comprises PMOS transistor ... etc..Furthermore, in during the control of digital power lock operates in one, the PMOS transistor selected by closedown, in order to reduce the voltage being supplied to kernel.In another embodiment, nmos pass transistor ... etc. element may as power gating device, and be arranged in power supply brake system 105 ~ 108, and the reference voltage VSS0 being coupled in kernel 101 ~ 104 is with between this corresponding ground voltage, as VSS1 ~ VSS4 (not shown), this ground voltage VSS1 ~ VSS4 is supplied to kernel 101 ~ 104.
Those skilled in the art all know very well, under full electric source modes, each micro-processor kernel will there will be large leakage current.Although there is technology that leakage current can be reduced, power loss will be caused, as account for total power consumption 15% or more.Can know, kernel 101 ~ 104 also non-concurrent starts.Therefore, when at least one in kernel 101 ~ 104 carries out power gating operation, a low-power mode is just operable in, in order to reduce power loss.In fact, all kernels of the multi-processor structure of microprocessor 100 li can't be activated simultaneously.Therefore, under normal operation, power gating operation is carried out at least one in kernel 101 ~ 104, in order to reduce the overall power of microprocessor 100.
If do not need storaging state information, then a digital power brake system and method can be utilized to carry out full power gating operation at least one in kernel 101 ~ 104, in order to close at least one in kernel 101 ~ 104.When at least one in kernel 101 ~ 104 does not need running and do not need storage information, then full power gating can be used to operate.But under power gating operation, even if kernel enters idle mode, still need the state retaining kernel, used for recovery operation a little later.In known power gating structure, all states of a kernel can be stored in the memory of a chip built-in or other has the similar components (not shown) of power supply.Then, by not providing voltage VDD or VSS to give kernel, just can effectively stop providing power supply to kernel.When needs use this kernel, more again provide power supply to kernel, and acquisition is stored in the state of memory, and then restarts running.
The level that the control of known power source lock uses directly affects overall efficiency.Special, due to the more clock cycle quantity of needs, just can complete all conversions, and in one independently memory, store and capture state information, thus cause and significantly postpone.Therefore, lower electricity (power-down) with power on (power-up) time, large delay will be caused.If for the group effect improving kernel 101 ~ 104, then delay must be reduced.
In the microprocessor 100 of Fig. 1, each power supply brake system 105 ~ 108 according to corresponding power gating signal PGATE1 ~ PGATE4 (i.e. power gating signal group PGATE<1:4>), the power gating of combine digital formula.When needing to carry out power gating to a particular core of kernel 101 ~ 104, this kernel will enter an idle mode, and the clock of kernel inside also can be closed.Even if at idle state, still have leakage current, thus cause serious power loss.Full power gating will lose the data or information that kernel stores.But, according to the triggering situation of power gating signal PGATE1 ~ PGATE4, close corresponding PMOS device, in order under a given time, reduce the lock control service voltage being supplied to kernel.Final lock control service voltage is less than full power supply service voltage, but can maintain the state information of kernel, and can reduce power consumption and leakage current.
If make a particular core from power gating operation get back to full power operation, then need to carry out a recovery routine or operation.Special, power supply brake system according to the invalid situation of power gating signal PGATE1 ~ PGATE4, between a given period, conducting PMOS device, in order to voltage of increasing supply, and the service voltage of increase is supplied to kernel, wherein can by the length between programming adjustment given period.When kernel receives full service voltage again, just leave idle mode, and may restart.
No matter be time of power gating of reducing power supply and recovering power supply be all less than known storage and time of nuclear state in recovering.Therefore, the time entering and leave power gating pattern just can be minimized, and improves whole efficiency widely.
In a possibility embodiment, under full electric source modes, service voltage VDD0 is approximately 1V or 1.05V.Apprehensible, under specific electric source modes, service voltage VDD0 may change between 0.95V ~ 1.15V.Under power gating pattern, lock control service voltage (as at least one in voltage VDD1 ~ VDD4) can be reduced to 450mV, in order under the state retaining kernel, reduces or minimizes leakage current.Apprehensible, for different semiconductor technologies, different specific voltage level may be had, and these specific voltage level are just exemplarily routine.The present invention can be applicable in the technology of different voltage level, in order at holding circuit (as micro-processor kernel ... etc.) logic state under, reduce or minimize leakage current.
In a possibility embodiment, microprocessor 100 comprises a power-supply controller of electric 110, in order to provide many control signals, to control power supply status, and controls the power gating function of kernel 101 ~ 104.If during for carrying out power gating at least one in kernel 101 ~ 104, power-supply controller of electric 110 make in kernel 101 ~ 104 at least one enter an idle mode, and close the internal clock signal of corresponding kernel.Then, power-supply controller of electric 100 triggers corresponding power gating signal PGATE1 ~ PGATE4 (as shown in PGATE<1:4>), in order to carry out power gating to corresponding kernel.
If when wish recovers the kernel of power gating, corresponding power gating signal in power-supply controller of electric 110 ineffective treatment power gating signal group PGATE<1:4>, and wait for a period of time, until lock control service voltage returns to normal operation level and completes recovery routine.During corresponding power supply ready signal in any one triggering voltage ready signal group PGOOD<1:4> of power supply brake system 105 ~ 108, power-supply controller of electric 110 is according to the trigger state of power supply ready signal group PGOOD<1:4>, learn that recovery routine completes, and lock control service voltage is stabilized in the level of voltage VDD0.Then, the clock signal of power-supply controller of electric 110 activation kernel inside again, therefore, kernel may operate again.
Power-supply controller of electric 110 may also provide a set of reference voltages PG_VREF<1:N>, in order to control the power gating process performed by power supply brake system 105 ~ 108, set of reference voltages PG_VREF<1:N> may have at least one reference voltage.For specific structure or device, N can be Arbitrary Digit.When N is 1, represents and single reference voltage is only provided.For example, as long as can retain the digital state of kernel, when N is 1, this single reference voltage is the final voltage level of lock control service voltage VDD1 ~ VDD4, in order to reduce leakage current.In another possibility embodiment, when N is 2, represents and provide two reference voltages, as PG_VREF_L and PG_VREF_H.Reference voltage PG_VREF_L represents when power gating, the final voltage level of lock control service voltage VDD1 ~ VDD4.Reference voltage PG_VREF_H represents a small voltage level, the final voltage level representated by a little higher than reference voltage PG_VREF_L.
In other embodiments, definable or provide multiple extra reference voltage, as intermediate control voltage level and multiple final voltage.In addition, at least one programmable voltage level can be utilized to replace the reference voltage of set of reference voltages PG_VREF<1:N>.In certain embodiments, the reference voltage of set of reference voltages PG_VREF<1:N> provided by an external source.
Power-supply controller of electric 110 may also provide signal group V_DOWN<4:0> to give power supply brake system 105 ~ 108, in order to during power gating, adjusts, and next will describe in detail.Under some or following specific operation condition, service voltage VDD0 can be downgraded.Before the level of service voltage VDD0 changes, a signal of power-supply controller of electric 110 triggering signal group V_DOWN<4:0>, the minimizing amplitude of the signal indication service voltage VDD0 be wherein triggered.When power gating, when at least one in lock control service voltage VDD1 ~ VDD4 drops to a state reservation level, the extra minimizing of voltage VDD0 may cause at least one (as the VDD1) in lock control service voltage to decline, and lower than a final voltage level.For example, if when final voltage level can maintain the state information of kernel, when not having other to correct, the minimizing of voltage VDD0 may cause lock control service voltage to be less than final voltage level, thus cannot retain the state information of kernel.Signal in signal group V_DOWN<4:0>, as disposable adjustment, in order to activation power supply brake system 105 ~ 108, and adjusts power gating operation.Therefore, lock control service voltage can be avoided to be less than final voltage level.
Such as when needing to close kernel or do not need the state information storing kernel, the one corresponding signal of power-supply controller of electric 110 enable signal group PG_KILL_CORE<1:4>, in order to carry out the initialization of full power gating to a corresponding kernel, the appointment of lock control service voltage is reduced to zero (or close to zero).
Signal PWR_GOOD integrates in order to represent the normal operation voltage level that service voltage VDD0 has been stabilized in itself.In FIG, signal PWR_GOOD produced by power-supply controller of electric 110, but signal PWR_GOOD also may provide (as a motherboard by outside institute ... etc.), in order to represent that service voltage VDD0 is stable and effective.Power on or reset and beginning activation before, signal PWR_GOOD may in order to initialize power controller 110 and power gating signal.
Other PLC technology signal PG_FU_X many are used to the pattern controlling power gating operation and operation.Value represented by symbol FU is by fuse or scan values ... etc. defined, in order to adjust corresponding operating parameter and the numerical value of microprocessor 100.Scan values may be data or register value, just writes at the test phase of IC, as jtag boundary scanning ... etc..Described structure provides static state and the dynamic level of many programmable operations.Under manufacture or specific device, test operation may be carried out by rule of thumb, and define corresponding required operating parameter.Then fuse may be used, in order to programming operation parameter statically, in order to obtain best result.Scanning t test and fuse may be wired-OR gate (wired-OR), in order to strengthen test and static programming.Power-supply controller of electric 110 may provide signal PG_FU_X or other control signal of activation, in order to control power gating process.
In the present embodiment, mode adjustment square 112 may provide signal PG_FU_X, in order under power gating function, controls or adjust the pattern of operation.Mode adjustment square 112 has fuse array 114 and a memory 116.No matter the integration being fuse array 114 or memory 116 or fuse array 114 and memory 116 may in order at least one of programming signal PG_FU_X.Fuse array 114 comprises many fuses, and these fuses may be programmed, in order at least one of static settings signal PG_FU_X.For example, a specific insurance silk can be coupled an external pin (not shown) by address choice or directly by the programming of fuse, is applying enough high pressure with fuse wire.When fuse is fused, an electrical short can be provided, in order to perform the operation of a first mode or a preset mode.When fuse is by fusing, provide an open circuit characteristic, in order to the operation of one second pattern or a programming mode.Memory can at least one of static or dynamically setting signal PG_FU_X.For example, programming static memory, as read-only memory (ROM) ... etc., in order at least one of setting signal PG_FU_X.Programming dynamic memory, as random access memory (RAM), register ... etc., in order to (as to power on and/or boundary scan when operating ... etc.), at least one of setting signal PG_FU_X.
Fig. 2 is the schematic diagram of kernel 101 of the present invention and power supply brake system 105.Because the relation between each kernel in Fig. 1 and corresponding power supply brake system is all identical, therefore kernel 101 shown by Fig. 2 and the relation between power supply brake system 105 also can relations between other kernel of representative graph 1 li and corresponding power supply brake system.In the present embodiment, power supply brake system 105 comprises a power gating system 201 and many gating circuits, is shown as PG_GATE_TOP202, PG_GATE_LEFT203, PG_GATE_RIGHT204 and PG_GATE_BOTTOM205 respectively.Gating circuit PG_GATE_TOP202, PG_GATE_LEFT203, PG_GATE_RIGHT204 and PG_GATE_BOTTOM205 lay respectively at the top of kernel 101, left, right and below.Each gating circuit comprises many power gating devices.Power gating device is arranged on kernel 101 around.In another embodiment, power gating device as a power gating array, and may be incorporated among kernel 101.For at least one in kernel 101 ~ 104, the lock control device of inside and outside can be set.
Kernel 101 with voltage VSS0 for reference, and comprise one lock control supply bus 206.Lock control supply bus 206 provides lock control service voltage VDD1 to give kernel 101.Those skilled in the art all know very well, kernel 101 has many PMOS transistor, nmos pass transistor and other circuit element (all not showing), in order to perform processing capacity.Under full Power Supplies Condition, the CMOS device of kernel 101 has larger leakage current.In the present embodiment, power gating system 201 provides the control word PG_CNTRL<16:0> of 17.During power gating, the level of control word PG_CNTRL<16:0> control voltage VDD1, the level of voltage VDD1 is relevant with voltage VDD0.Voltage VDD1, by input VDD1_FB, feeds back to power gating system 201.
Power gating system 201 receiver voltage VDD0, therefore, when kernel 101 carries out power gating, power gating system 201 is still power-up state, in order to maintain power gating and operation.Power gating system 201 receives the Front Side Bus numerical value FSB<3:0> of a clock signal EESDCLK and 1.Front Side Bus numerical value FSB<3:0> represents the frequency of a bus clock.Clock signal EESDCLK and Front Side Bus numerical value FSB<3:0> is in order to set and to adjust the cycle of at least one internal clock signal (as PG_CLK).The cycle time of internal clock signal PG_CLK is the time performing power gating.Power gating system 201 Received signal strength PWR_GOOD.Signal PWR_GOOD triggered by power-supply controller of electric 110, in order to represent that service voltage VDD0 gets back to normal operation voltage level.When signal PWR_GOOD is not triggered, reset or initialize power gate control system 201.When powering on or reset, the level of voltage VDD1 follows voltage VDD0 level.
Power gating system 201 Received signal strength PG_KILL_CORE1.Signal PG_KILL_CORE1 is a signal of signal group PG_KILL_CORE<1:4>.Power-supply controller of electric 110 provides signal PG_KILL_CORE1 to give kernel 101.If during for closing kernel 101 or do not need the state information storing kernel 101 under a low-power mode, power-supply controller of electric 110 triggering signal PG_KILL_CORE1, in order to carry out the initialization of full power gating to kernel 101, now, voltage VDD1 drops to (or close) 0V.When powering on, if when signal PWR_GOOD is not yet triggered, then ignore signal PG_KILL_CORE1.
Power gating system 201 receives a power gating signal PGATE1.Power gating signal PGATE1 is a signal of signal group PGATE<1:4>.Whether signal group PGATE<1:4> provided by power-supply controller of electric 110, operate in order to represent for the power gating waking or remove kernel 101 up.When signal PGATE1 is triggered, in order to carry out power gating initialization to kernel 101.When being disabled of signal PGATE1, kernel 101 leaves power gating operation, and comes back to normal mode.
Power gating system 201 receives set of reference voltages PG_VREF<1:N>.By at least one reference voltage and the voltage VDD1 (by input VDD1_FB) of comparison reference voltage group PG_VREF<1:N>, just can the progress of monitoring power supply lock control operation, and/or come back to normal mode.For example, in a possibility embodiment, the level of power gating system 201 comparative voltage VDD1 and at least one reference voltage, in order to whether to arrive certain threshold according to voltage VDD1, to enter and/or to leave power gating operation.The present invention does not limit the quantity of the reference voltage controlling power gating.
Power gating system 201 Received signal strength group V_DOWN<4:0>, in order under given conditions, disposable adjustment is done to control word PG_CNTRL<16:0> (or referred to as PG_CNTRL).One signal specific of power-supply controller of electric 110 possibility triggering signal group V_DOWN<4:0>, in order under a low power supply status, reduces the level of voltage VDD0.In certain embodiments, the decoupling capacitor (decouplingcapacitor) of outside or inside may be present among kernel 101, and receives lock control service voltage VDD1.If not there is decoupling capacitor, then undesired signal group V_DOWN<4:0>, or ignore signal group V_DOWN<4:0>.But, if having decoupling capacitor, or when kernel has very large capacitance, because large capacitance will affect resistance-capacitance (RC) time coefficient, if particularly voltage VDD0 has also been downgraded, in the case, control word PG_CNTRL can be utilized to adjust voltage VDD1.C in RC time coefficient refers to the total capacitance in kernel 101, and R refers to the total impedance of the power gating device be coupled between voltage VDD0 and VDD1.When power gating device is unlocked or closes, will total impedance be affected, and then affect RC time coefficient.
The trigger condition of power gating system 201 detection signal group V_DOWN<4:0>, and according to RC time coefficient adjustment control word and voltage VDD1, in order to compensate RC time coefficient, to guarantee immediately can react, and the level of voltage VDD1 is avoided to be in a unknown levels.The level of voltage VDD1 so can be prevented to preset minimum levels (if final voltage level of store status) lower than one, and can avoid losing the state information being stored in kernel 101.
When voltage VDD1 is normal operation level, power gating system 201 triggers a power supply ready signal PGOOD1, and provides power supply ready signal PGOOD1 to give power-supply controller of electric 110.Power supply ready signal PGOOD1 is the signal in above-mentioned signal group PGOOD<1:4>.In one embodiment, when carrying out power gating operation, the highest significant position (MSB) of control word PG_CNTRL<16:0>, namely control bit PG_CNTRL<16> can be closed or not be triggered, in order to close corresponding multiple PMOS devices.When highest significant position or control bit PG_CNTRL<16> are triggered, then carry out Recovery processing.By control bit PG_CNTRL<16:0>, signal PGOOD1 can be derived, or direct triggering signal PGOOD1.
Power gating system 201 Received signal strength PG_FU_X, in order to adjust corresponding operating parameter and numerical value ... Deng.These parameters can be programmed, and can by fuse, scanning ... etc. mode set these parameters.There is the signal of symbol GN in order to adjust the gain of corresponding operating parameter or numerical value.For example, numerical value PG_FU_ADD_GN adjusts a summed values, in order to increase control word PG_CNTRL (as under power gating pattern, statically-retained voltage level), and numerical value PG_FU_SUB_GN adjusts a values of disparity, in order to reduce control word PG_CNTRL (as under power gating pattern).Under voltage modulated, summed values and values of disparity are dynamic gain.
Under power gating operation, if when voltage VDD1 arrives a given threshold voltage, utilize numerical value PG_FU_HIERB regulation time radix or adjustment cycle.In one embodiment, when voltage VDD1 drops to a critical level, trigger binary signal HIER (will illustrate after a while), critical level is higher than a final voltage level, final voltage level can retain data or the state of kernel, and is represented by low critical level (HIGH).When signal HIER is triggered, increase the cycle of clock signal PG_CLK, regulate the speed in order to reduce, the cycle of clock signal PG_CLK is relevant with the length of above-mentioned regulation time.When do not provide or non-trigger value PG_FU_HIERB, regulation time is a preset value.Furthermore, numerical value PG_FU_HIERB is in order to change the cycle size of clock signal PG_CLK.
Under power gating operation, fuse or scan values adjustment clock signal PG_CLK can be utilized.For example, by each numerical value of fuse setting numerical value group PG_FU_ENT<10:5>, in order to change the cycle of clock signal PG_CLK.In a possibility embodiment, can by the cycle of the different parameters adjustment clock signal PG_CLK of certain architectures.In one embodiment, the capacitance of a particular core may because of external capacitive ... etc. and increase, thus power gating operation under, RC time coefficient will be increased.Extra capacitance may increase RC time coefficient, the reaction speed of adjustment action of thus slowing down.Numerical value group PG_FU_ENT<10:5> has a programmable functions, in order under power gating operation, compensates extra capacitance.
When a signal RESUME is triggered, by many fuses or sweep parameter, just can enter recovery operation, and leave power gating operation.Signal RESUME is triggered according to signal PGATE1 or _ PG_KILL_CORE1.In some or all times of power gating operation, signal RESUME can being disabled.In Recovery processing, an adjustment numerical value can be added in control word PG_CNTRL.Numerical value group PG_FU_RESUME_GN<1:0> is in order to select different summed values, in order to adjustment and recovery gain, numerical value group PG_FU_RESUME_GN<1:0> has two numerical value, by fuse or scan mode, the cycle of adjustment clock signal PG_CLK.For example, numerical value PG_FU_CONST_RES_CLK, in order in Recovery processing, selects one of clock signal PG_CLK to preset the fixed cycle.Numerical value group PG_FU_RES_PER<1:0> is programmable 2 bit value, may in order to the period modulation of clock signal PG_CLK is become a fixed numbers.The length of predetermined period must be enough to, being returned under normal running, can not interrupt the operation of around kernel or other circuit.Numerical value PG_FU_RESUME_STOP is binary value, and it, in order to represent under normal operation, stops adjustment control word and control word is returned to initial level.
The operating principle of gating circuit 202 ~ 205 is identical, and has at least one input and at least one output, and input integrates service voltage VDD0 in order to receive, and output is in order to couple lock control supply bus 206.Lock control supply bus 206 transmits lock control service voltage VDD1.In the present embodiment, power gating system 201 produces control word PG_CNTRL<16:0>, and in order in the operation of above-mentioned power gating, the level of control voltage VDD1, the level of voltage VDD1 is relative to voltage VDD0.The input I<16:0> of gating circuit 202 and 203 receives control word PG_CNTRL<16:0>.After gating circuit 202 buffer control word PG_CNTRL<16:0>, then buffering result PG_CNTRLA<16:0> is exported to the corresponding input I<16:0> of gating circuit 204 by output O<16:0>.Similarly, after gating circuit 203 buffer control word PG_CNTRL<16:0>, then buffering result PG_CNTRLB<16:0> is exported to the corresponding input I<16:0> of gating circuit 205 by output O<16:0>.
Symbol I and O represents input respectively and exports control word CNTRL, after gating circuit 202 and 203 buffer control word CNTRL, produces buffering result CNTRLA and CNTRLB respectively.The operating principle of gating circuit 204 and 205 is identical with gating circuit 202 and 203, even if do not show the buffering result that gating circuit 204 and 205 produces.Herein, control word PG_CNTRL<16:0> also can be described as PG_CNTRL, unless need use 16 of control word PG_CNTRL<16:0>.
Gating circuit (as 202 ~ 205) shown by Fig. 2, in the mode of disperseing, is arranged on a large circuit (as kernel 101) around, but and is not used to limit the present invention.For example, identical or different gating circuit may fully be incorporated in circuit or kernel, or the gating circuit of a part is integrated in circuit, and another part is arranged on around circuit.No matter the structure of gating circuit why, each gating circuit has the distributor circuit of part, in order to each corresponding control end to power gating device of transfer control word PG_CNTRL<16:0>.Distributor circuit generally has many buffers or conveyer ... etc., in order to maintain the signal correctness of each of control word.
Fig. 3 is the rough schematic of gating circuit PG_GATE_TOP202 of the present invention, and the operating principle of gating circuit PG_GATE_TOP202 ~ 205 is identical.Gating circuit PG_GATE_TOP202 has four independent and roughly the same side blocks 301.Side block 301, by control word PG_CNTRL (as between PG_CNTRL<16:0> and PG_CNTRLA<16:0>), is serially connected in daisy chain (daisychained) mode.Each side block 301 receives control word PG_CNTRL or buffering result by corresponding input I<16:0>, and exports buffering result by output O<16:0>.
Each side block 301 also comprises input IN and output OUT.Input IN couples and integrates supply bus 109, in order to receiver voltage VDD0.Output OUT couples lock control supply bus 206, in order to produce voltage VDD1.Generally speaking, each conducting of control word PG_CNTRL<16:0> is coupled in the device between VDD0 and VDD1, and can learn the capacitance between service voltage or resistance value.When many devices (or all devices) are switched on, electric capacity is maximum, and impedance is minimum, therefore, voltage VDD1 effectively by strangulation to voltage VDD0, suppose, voltage VDD1 approximates voltage VDD0.Under the local or All Time of power gating operation, close all devices, therefore, relative to voltage VDD0, the level of voltage VDD1 declines.
Fig. 4 is that one of side of the present invention block 301 may embodiment.Side block 301 has two independent and identical lock squares 401.Lock square 401, by the high-order portion PG_CNTRL<16:13> of control word or the buffering result of high-order portion PG_CNTRL<16:13>, links together in daisy-chain fashion.Each lock square 401 comprises control word input I<16:13> and control word output O<16:13>.Side block 301 also has other lock square 403.Lock square 403 receives the low portion PG_CNTRL<12:0> of control word by input I<12:0>, and exports the buffering result of low portion PG_CNTRL<12:0> by output O<12:0>.Lock square 401 and 403 all has input IN and output OUT.Input IN couples and integrates supply bus 109, in order to receiver voltage VDD0.Output OUT couples lock control supply bus 206, in order to provide voltage VDD1.
Fig. 5 is that one of the lock square 401 of high-order portion in order to processing controls word may embodiment.The highest control bit PG_CNTRL<16> of control word controls buffering result I<16>.By the highest control bit PG_CNTRL<16> of group of buffers 501 (buffers as 8 series connection) process, and provide a Buffer output control level O<16>.Multiple PMOS transistor group 502 is connected in parallel, and the grid of each PMOS transistor group 502 couples the output of a corresponding buffer 501, in order to receive a corresponding buffering result (the buffering result of the highest control bit PG_CNTRL<16>).The source electrode receiver voltage VDD0 of PMOS transistor group 502, its drain electrode provides voltage VDD1.In the present embodiment, when the highest control bit PG_CNTRL<16> is triggered to low level, PMOS transistor group 502 is switched on, and in order between voltage VDD0 and VDD1, provides the current path that is corresponding.When the highest control bit PG_CNTRL<16> is triggered to high level (or inactive level), PMOS transistor group 502 is not switched on.
In one embodiment, each PMOS transistor group 502 has 768 PMOS transistor in parallel.Each lock square 401 has 8 PMOS transistor groups 502, each side block 301 has 2 lock squares 401, and each gating circuit 202 ~ 205 all has 4 side blocks, therefore altogether have 196,608 PMOS transistor (large all 200K transistors) are connected in parallel, and are controlled by the highest control bit PG_CNTRL<16>.Because gating circuit, side block and lock square are dispersed in kernel 101 around, and around each kernel, all there is identical framework, therefore, each kernel of microprocessor 100 by the PMOS device of quite large quantity institute around, these PMOS devices are controlled by the highest control bit PG_CNTRL<16>.In one embodiment, the size of each PMOS transistor is about 2 microns (micron), therefore, transistor material approximately needs 393216 microns (about 400K microns), and controlled by the highest control bit PG_CNTRL<16>.
Next the highest effective control bit PG_CNTRL<15> of the highest control bit PG_CNTRL<16> of control word controls buffering result I<15>, by inverter group 503 cushioning control position PG_CNTRL<15>.The output of inverter group 503 couples PMOS transistor group 504.Together, and its grid couples the output of corresponding inverter group to the coupled in parallel that PMOS transistor group is 504 li, its source electrode receiver voltage VDD0, and its drain electrode produces voltage VDD1.In the present embodiment, when control bit PG_CNTRL<15> is low level, each transistor of conducting PMOS transistor group 504 li, in order to provide current path between VDD1 and VDD0.When control bit PG_CNTRL<15> is high level, close each transistor of PMOS transistor group 504 li.
In a possibility embodiment, each PMOS transistor group 504 has 64 PMOS transistor in parallel.Each lock square 401 has 4 PMOS transistor groups 504, each side block 301 has 2 lock squares 401, and each gating circuit 202 ~ 205 all has 4 side blocks, therefore altogether have 8,192 PMOS transistor are connected in parallel, and are controlled by control bit PG_CNTRL<15>.In one embodiment, the size of each PMOS transistor is about 2 microns (micron), and therefore, transistor material approximately needs 16384 microns, and controlled by control bit PG_CNTRL<15>.Therefore, although the quantity being controlled by the PMOS device of control bit PG_CNTRL<15> is minimum in the quantity of PMOS device being controlled by control bit PG_CNTRL<16>, but the surrounding of each kernel of microprocessor 100 still has many PMOS devices, these PMOS devices are controlled by control bit PG_CNTRL<15>.
Next the highest effective control bit PG_CNTRL<14> of the control bit PG_CNTRL<15> of control word controls buffering result I<14>, by inverter group 505 cushioning control position PG_CNTRL<14>.The output of inverter group 505 couples PMOS transistor group 506.Together, and its grid couples the output of corresponding inverter group to the coupled in parallel that PMOS transistor group is 506 li, its source electrode receiver voltage VDD0, and its drain electrode provides voltage VDD1.In the present embodiment, when control bit PG_CNTRL<14> is low level, each transistor of PMOS transistor group 506 li is switched on, in order to provide current path between VDD1 and VDD0.When control bit PG_CNTRL<14> is high level, each transistor not conducting of PMOS transistor group 506 li.
In a possibility embodiment, PMOS transistor group 506 has 64 PMOS transistor in parallel.Each lock square 401 has 2 PMOS transistor groups 504, each side block 301 has 2 lock squares 401, and each gating circuit 202 ~ 205 all has 4 side blocks, therefore altogether have 4,096 PMOS transistor is connected in parallel, and is controlled by control bit PG_CNTRL<14>.In one embodiment, the size of each PMOS transistor is about 2 microns (micron), and therefore, transistor material approximately needs 8192 microns, and controlled by control bit PG_CNTRL<14>.Therefore, although the quantity being controlled by the PMOS device of control bit PG_CNTRL<14> is the half of the quantity of the PMOS device being controlled by control bit PG_CNTRL<15>, but the surrounding of each kernel of microprocessor 100 still has many PMOS devices, these PMOS devices are controlled by control bit PG_CNTRL<14>.
Next the highest effective control bit PG_CNTRL<13> of the control bit PG_CNTRL<14> of control word controls buffering result I<13>, inverter group 507 cushioning control position PG_CNTRL<13>.The output of inverter group 507 couples PMOS transistor group 508.Difference is that PMOS transistor group 508 only has 64 PMOS transistor.In the present embodiment, altogether have 2,048 PMOS transistor is connected in parallel, and is controlled by control bit PG_CNTRL<13>.In one embodiment, the size of each PMOS transistor of transistor group 508 is about 2 microns (micron), therefore, transistor material approximately needs 4096 microns, and controlled by control bit PG_CNTRL<13>.Therefore, although the quantity being controlled by the PMOS device of control bit PG_CNTRL<13> is the half of the quantity of the PMOS device being controlled by control bit PG_CNTRL<14>, but the surrounding of each kernel of microprocessor 100 still has many PMOS devices, these PMOS devices are controlled by control bit PG_CNTRL<13>.
The highest significant position of control word, namely control bit PG_CNTRL<16> approximately controls 200K PMOS transistor 502 of the gating circuit 202 ~ 205 li be dispersed in around kernel 101, approximately needs the transistor material of 400K micron.Control bit PG_CNTRL<15:13> is binary format, wherein control bit PG_CNTRL<15> controls about 16, the transistor material of 384 microns, control bit PG_CNTRL<14> controls about 8, the transistor material of 192 microns, control bit PG_CNTRL<13> controls about 4, the transistor material of 096 micron.In the present embodiment, when corresponding control bit is triggered to low level, just can the corresponding PMOS transistor of conducting; When control bit is triggered to high level, the PMOS transistor that just not conducting is corresponding.
Fig. 6 is that one of the lock square 403 of the low portion receiving control word may embodiment.Lock square 403 continues the remaining position PG_CNTRL<12:0> (except control bit PG_CNTRL<16>, control bit PG_CNTRL<15:00> is binary format) of process.For control bit PG_CNTRL<12:0>, the half of the PMOS transistor quantity that the PMOS transistor quantity that each controls and/or transistor material control for a upper position and/or transistor material.In addition, the grid of each PMOS transistor controlled by corresponding control bit, its source electrode receiver voltage VDD0, and its drain electrode provides voltage VDD1.
Other PG_CNTRL<12:0> of control word structural similarity in lock square 403 is in control bit PG_CNTRL<13>, and comprise inverter group 601 and PMOS transistor group 602, except the quantity of PMOS transistor and/or size can be adjusted, in order to continue binary format.The size of inverter group 601 depends on the quantity of the transistor material in each design.
The control bit PG_CNTRL<12> of control word controls buffering result I<12>, and it connects inverter group 601 and PMOS transistor group 602.PMOS transistor group 602 has 64 PMOS transistor.The structural similarity of control bit PG_CNTRL<12> is in the structure of control bit PG_CNTRL<13>.In each side block 301, there is 2 lock squares 401 and 1 lock square 403, therefore, the half of the number of transistors that the number of transistors that control bit PG_CNTRL<12> controls controls for control bit PG_CNTRL<13>, in order to continue binary format.Each of ensuing control bit PG_CNTRL<11:6> has identical framework, and the number of transistors just controlled is the half of upper.As shown in the figure, cushioning control position I<11> controls 32 PMOS transistor of PMOS transistor group 602 li; Cushioning control position I<10> controls 16 PMOS transistor of PMOS transistor group 602 li; Cushioning control position I<9> controls 8 PMOS transistor of PMOS transistor group 602 li; Cushioning control position I<8> controls 4 PMOS transistor of PMOS transistor group 602 li; Cushioning control position I<7> controls 2 PMOS transistor of PMOS transistor group 602 li; Cushioning control position I<6> controls 1 PMOS transistor of PMOS transistor group 602 li.
Next control bit I<5> only controls the half of the PMOS transistor of half, as PMOS transistor 604.In a possibility embodiment, the width of PMOS transistor 604 only has a half width of PMOS transistor 602, therefore compared to PMOS transistor 602, PMOS transistor 604 only needs the transistor material of half.Next control bit I<4> only controls 1/4 PMOS transistor, as PMOS transistor 606.In a possibility embodiment, PMOS transistor 606 only has a half width of PMOS transistor 604, therefore only has the transistor material of half.Next control bit I<3> only controls 1/8 PMOS transistor, as PMOS transistor 608.In a possibility embodiment, PMOS transistor 608 only has a half width of PMOS transistor 606, therefore only has the transistor material of half.Remaining control bit I<2:0> only controls 1/16,1/32 and 1/64 PMOS transistor, as PMOS transistor 610,612,614.Although the width of each transistor row only has half, many one times of length.Therefore, the width of PMOS transistor 610,612 and 614 is similar in appearance to the width of PMOS transistor 608, length except PMOS transistor 610 is two times of the length of PMOS transistor 608, the length of PMOS transistor 612 is four times of the length of PMOS transistor 608, and the length of PMOS transistor 614 is octuple of the length of PMOS transistor 608.
In the present embodiment, control bit PG_CNTRL<12> controls the transistor material of 2048 microns, control bit PG_CNTRL<11> controls the transistor material of 1024 microns, control bit PG_CNTRL<10> controls the transistor material of 512 microns, control bit PG_CNTRL<9> controls the transistor material of 256 microns, control bit PG_CNTRL<8> controls the transistor material of 128 microns, control bit PG_CNTRL<7> controls the transistor material of 64 microns, control bit PG_CNTRL<6> controls the transistor material of 32 microns, control bit PG_CNTRL<5> controls the transistor material of 16 microns, control bit PG_CNTRL<4> controls the transistor material of 8 microns, control bit PG_CNTRL<3> controls the transistor material of 4 microns, control bit PG_CNTRL<2> controls the transistor material of 2 microns, control bit PG_CNTRL<1> controls the transistor material of 1 micron, control bit PG_CNTRL<0> controls the transistor material of 1/2 micron.
In the present embodiment, the size of the PMOS transistor of each branch reduces gradually, during to control bit PG_CNTRL<6>, and only remaining one-transistor.Therefore, the Breadth-Length ratio (W/L) of adjustable PMOS transistor, in order to reduce transistor material, to minimize binary pattern.For next control bit PG_CNTRL<5>, its width is reduced half, and the width of control bit PG_CNTRL<4> and PG_CNTRL<3> is reduced half again.Therefore, for remaining 2, length parameter for variable, in order to complete binary pattern.
The ad hoc structure of above-mentioned control bit and PMOS device and binary system disperse pattern to be a possible execution mode, and other change also can be utilized to realize.Generally speaking, many devices dispersible around kernel, and are coupled between voltage VDD0 and VDD1, and when carrying out power gating, by conducting or not conducting device, digitally to switch the size of the current path between service voltage.In a digitalization control method, be change the level of voltage VDD1 relative to VDD0.In a possibility embodiment, when power gating operates, the final level of voltage VDD1 must be enough to retain kernel information, in order to reduce leakage current.
Please refer to Fig. 2, under normal operation, control word PG_CNTRL is set to a default value by power gating system 201, in order to by voltage VDD1 strangulation at voltage VDD0.In one embodiment, position PG_CNTRL<16,11:0> of control word are low level, in order to the PMOS transistor that conducting is corresponding, and all the other PG_CNTRL<15:12> of control word are high level, namely control bit PG_CNTRL<16:0> is an initial value 01111000000000000b, and wherein b is binary representation.As mentioned above, power-supply controller of electric 110 can wait kernel 101 to enter idle mode, or after order kernel 101 enters idle mode, and then turn off the functional clock of kernel 101, and enable signal PGATE1, in order to carry out power gating operation to kernel 101.When signal PGATE1 is triggered, power gating operation is initialised, therefore the highest order PG_CNTRL<16> of control word can be pulled to high level, in order to close main PMOS transistor (according to appointment 200K).Because kernel 101 is idle state, and produce leakage current, therefore, when control bit PG_CNTRL<16> closes the most of transistor material between voltage VDD0 and VDD1, the level of voltage VDD1 can not decline significantly.Now, the transistor material of a PG_CNTRL<11:0> conducting about 4096 microns is only had, in order to ME for maintenance VDD1 fully close to voltage VDD0.It should be noted impedance, the impedance between voltage VDD0 and VDD1 will be increased, and thus may cause the slight variations of voltage between voltage VDD0 and VDD1.
Power gating system 201 then starts the position PG_CNTRL<11:0> of Digital Control control word, in order to the level of lock control service voltage VDD1 is reduced to final voltage level.In each consecutive steps, the impedance between voltage VDD0 and VDD1 can increase, and therefore, voltage VDD1 can reduce, until reach a final voltage level.As mentioned above, when voltage VDD1 equals final voltage level, leakage current can be reduced widely, and the state before kernel 101 enters power gating can be maintained.
Each in power supply brake system 105 ~ 108 shown in Fig. 1 utilize character PG_CNTRL each select control PMOS device, in order to carry out Digital Control, wherein PMOS device is centered around around each kernel of microprocessor 100.In a simple digital control framework, every a Fixed Time Interval, just control word PG_CNTRL is deducted a stationary digital adjustment numerical value, in order to reach final voltage level.Lock control service voltage VDD1 generally changes along with the numerical value of control word PG_CNTRL, therefore when control word PG_CNTRL reduces, lock control voltage VDD1 also can reduce.Under power gating operation, by comparative voltage VDD1_FB and PG_VREF_L, just can learn whether arrive final voltage level, and when reaching final voltage level, maintain the numerical value of control word PG_CNTRL.But in the present embodiment, control word PG_CNTRL may change along with the frequency of operating clock, and react along with any further adjustment of lock control voltage.
But when closing PMOS device, the impedance between voltage VDD0 and VDD1 will increase (but capacitance can maintain identical value), therefore, when adjusting voltage VDD1, RC time coefficient can be increased.In the present embodiment, at every turn new adjustment, the longer time is needed to change and the level of burning voltage VDD1.When the numerical value adjusted is too large, or the time interval of adjustment too in short-term, and voltage VDD1 just likely cannot arrive final voltage level.It must be appreciated, when carrying out power gating operation, when if desired maintaining kernel information, then lock control voltage just can not be less than a final voltage level, if because being less than final voltage level, just cannot retain the state information of kernel 101.Therefore, adjustment numerical value must be enough little, and/or the time interval of adjustment must be enough long, cannot equal final voltage level in order to avoid voltage VDD1.
In another embodiment, adjust numerical value and control to have one between numerical value in proportionate relationship.In this instance, when controlling numerical value and reducing, adjustment numerical value also can decline in ratio according to a fixed adjustment gain.In the present embodiment, can significantly adjust control numerical value rapidly at the beginning, and then reduce control numerical value gradually.Lock control service voltage VDD1 changes according to the change controlling numerical value.In above-mentioned digitlization embodiment, can by the control word that moves to right, in order to carry out a proportion expression adjustment, control word just can decline on ground in ratio, and can be adjusted numerical value.In one embodiment, control word is moved to right 6 times, and in order to provide an adjustment numerical value, it is 1/64 of control word, then deducts the result moved to right from control word, reduces control word in order to proportion expression.
In another embodiment, in order to adjust voltage VDD1 adjustment period between length may be adjusted continuously or periodically.In one embodiment, when the cycle of the power gating clock determining regulation time increases, adjustment cycle also can along with increase, and therefore, when voltage VDD1 reaches final voltage level, the frequency of adjustment is minimum.In a possibility embodiment, first produce a clock, it has the known cycle, and recycle the multiple clock signal of this clock generating, each clock signal has the different cycles.When adjusting, by selecting different clock signals, change adjustment cycle.In another embodiment, oscillator can be utilized ... etc., the frequency of adjustment clock signal.In other embodiments, between the adjustment period of by changing cycle of clock, just can changing (as increased) along with the time.
In other embodiments, also when starting or leave power gating operation, along with the time, adjustment numerical value and adjustment cycle can be changed simultaneously.
At the beginning or when leaving power gating operation of power gating operation, preset adjustment numerical value and/or adjustment cycle, in order to provide a fixing regulator curve.In other embodiments, dynamically numerical value and/or adjustment cycle is adjusted according at least one monitoring input.In one embodiment, monitoring lock control service voltage VDD1, and by monitored results compared with at least one critical voltage level (reference voltage as above-mentioned set of reference voltages PG_VREF<1:N>), then according to comparative result adjustment adjustment numerical value and/or adjustment cycle.In another embodiment, according to control word itself, just can be adjusted numerical value and/or adjustment cycle, such as control word equals the control word of a particular preset.For example, when control word is an initial value, utilize the PMOS transistor that position PG_CNTRL<11:0> conducting is corresponding, and the high-order portion PG_CNTRL<15:12> of control word closes corresponding PMOS transistor, in order to adjustment adjustment numerical value and/or adjustment cycle.
In another possibility embodiment, the critical numerical value of monitoring critical voltage level and control word, also can be adjusted numerical value and/or adjustment cycle.The present invention provides many situations of change for carrying out the operation of digitized power gating.
Fig. 7 A and Fig. 7 B is that one of power gating system 201 of the present invention may embodiment.Power gating system 201 has a digital adjuster.Numeral adjuster digitally adjusts control word PG_CNTRL, in order to control the voltage level of lock control supply bus 206.Lock control supply bus 206 provides lock control service voltage VDD1.Under some or all times of power gating operation, or under power up operation (the increment control algorithm word adjuster 801 as Fig. 8), add or deduct a numeral adjustment numerical value gradually, in order to carry out digitlization adjustment, or utilize larger electric voltage displacement (change according to integrating service voltage VDD0), add a larger numeral adjustment numerical value, to carry out digitlization adjustment.Numeral adjusts integer-valued size may depend on lock control state (lock control operation or recovery operation), voltage VDD1 and control word itself.In the continuous setup cycle, regulation may be the cycle depending on signal PG_CLK, and the cycle of signal PG_CLK may also be depend on lock control state (lock control operation or recovery operation), voltage VDD1 and control word itself.Fig. 7 A and the power gating system 201 shown by Fig. 7 B just in order to show relevant feature operation simply, and are not used to limit the present invention.For example, in some specific framework, many control signals may have many versions, comprise and available clock signal synchronization ... etc..The version of these specific control signals does not illustrate at this, and because of for completing for the present invention, these control signals are also inessential.
Power gating system 201 comprises recovers logic 701.Recover logic 701 Received signal strength PG_KILL_CORE1 and PGATE1, and signal RESUME is provided.In power gating operation in local, power-supply controller of electric 110 triggering signal PGATE1, in order to make power gating circuit 105 that the level of voltage VDD1 is reduced to a final voltage level, as a state retains level.The final voltage level preset can be any stable voltage level, to achieve the above object.At least one reference voltage that power-supply controller of electric 110 is programmed in set of reference voltages PG_VREF<1:N> with controlling the method choice of final voltage level, in order to control power gating process.Above-mentioned voltage level is that a state retains level (namely HIGH is triggered), and it can reduce leakage current, in order under a low power supply status, reduces power loss.State retains voltage level and is enough to retain data, in order to maintain the state of the kernel 101 of microprocessor 100.When signal PGATE1 being then disabled time, recover logic 701 triggering signal RESUME, in order to leave power gating operation, and initialization recovery operation, in order to the level of voltage VDD1 to be increased to the level of voltage VDD0.
When kernel 101 enters the operation of full power gating, power-supply controller of electric 110 triggering signal PG_KILL_CORE1, the level of voltage VDD1 is reduced to the level (as ground connection) approximating voltage VSS0 by power supply lock circuit 105.Under full power gating operation, the loss of power is minimum, but can lose the state of kernel 101 and all information recovering kernel 101.In a possibility embodiment, all positions of signal PG_KILL_CORE1 ineffective treatment (or not triggering) control word PG_CNTRL<16:0>, in order to close all PMOS devices, in order to kernel 101 is isolated with service voltage VDD0.In a possibility embodiment, although the priority of signal PG_KILL_CORE1 is greater than power gating operation, the triggering of signal PG_KILL_CORE1 also can triggering signal PGATE1.When signal PG_KILL_CORE1 being then disabled time, signal PGATE1 also can being disabled, and signal RESUME is triggered, in order to leave the operation of full power gating, and initialization recovery operation.
Recover logic 701 also receive a signal PG16 and power supply ready signal PGOOD1 is provided.Signal PG16 is exactly in fact the highest significant position PG_CNTRL<16> of control word.When signal PG16 is triggered to low level, represents and complete Recovery processing, and recover logic 701 and signal PGOOD1 is toggled to high level, in order to notify that power-supply controller of electric 110 completes Recovery processing.
Power gating system 201 comprises an OR logic 703.OR logic 703 Received signal strength group V_DOWN<4:0>, and a signal V_DWN is provided.When at least one signal in signal group V_DOWN<4:0> is triggered, represent that the level of voltage VDD0 starts to decline, as entered a low electric source modes.Now, signal V_DWN is triggered.
Power gating system 201 has a voltage compare group 705, in order to by the level of voltage VDD1_FB compared with each reference voltage of set of reference voltages PG_VREF<1:N>, and provide corresponding comparison signal CMP1 ~ CMPN.Comparison signal being usually disabled to high level.When the level of voltage VDD1_FB is eligible, comparison signal just can be triggered to low level.Each voltage comparator (not shown) can be any applicable mode and realized, as detecting amplifier ... etc..As mentioned above, voltage VDD1_FB is the feedback result of voltage VDD1.When voltage VDD1 is less than corresponding reference voltage, comparison signal CMP1 ~ CMPN can be triggered to low level.Therefore, when voltage VDD1 is less than reference voltage PG_VREF<1>, comparison signal CMP1 can be triggered to low level; When voltage VDD1 is less than reference voltage PG_VREF<2>, comparison signal CMP2 can be triggered to low level; The rest may be inferred for all the other; When voltage VDD1 is less than reference voltage PG_VREF<N>, comparison signal CMPN can be triggered to low level.In a possibility embodiment, reference voltage PG_VREF<1> is identical with signal PG_VREF_H, is all to represent that one retains the voltage level of voltage level higher than state.When voltage VDD1 is less than signal PG_VREF_H, signal HIER can be triggered to low level.Similarly, reference voltage PG_VREF<2> is identical with signal PG_VREF_L, is all to represent that state retains voltage level.When voltage VDD1 is less than signal PG_VREF_L, minimum detectable signal HIGH can be triggered to low level.Scrutable, during the control of voltage lock, can utilize the reference voltage of any amount or critical voltage level compared with voltage VDD1.
Power gating system 201 also comprises a clock controller 706.During the control of digital power lock, clock controller 706 controls the cycle of clock signal PG_CLK.In a possibility embodiment, clock controller 706 comprises clock generator 707, frequency divider 709, clock selecting party block 711 and a temporal decoder 712.In the present embodiment, clock generator 707 receive clock signal EESDCLK and numerical value FSB<3:0>, and clock signal CLK20.Clock signal EESDCLK may be received by an external source, or produced by microprocessor 100 inside.Numerical value FSB<3:0> represents the frequency of a bus clock of microprocessor system.In the present embodiment, clock signal EESDCLK can be any known frequency, and clock generator 707 utilizes clock signal EESDCLK and numerical value FSB<3:0>, clocking CLK20, clock signal clk 20 has the cycle time of about 20ns.Apprehensible, known cycle time 20, how second (ns) can be other arbitrary value, and can utilize replace other suitable known cycle time.
Clock signal clk 20 is provided to frequency divider 709.Frequency divider 709 clocking C20NS, C40NC ..., C2.6MS.Clock signal C 20NS, C40NC ..., C2.6MS has the corresponding clock cycle, for power gating function.Frequency divider 709 is by the cycle of clock signal clk 20 and parameter 2 0, 2 1, 2 2, 2 3..., 2 17be multiplied, in order to make clock signal C 20NS, C40NC ..., C2.6MS have respectively 20ns, 40ns, 80ns, 160ns ..., 2.6ms cycle time, the cycle time of clock signal C 2.6MS is 2.6ms.In the present embodiment, although utilize 20 possible control bits to control 18 timing parameters, and be not used to limit the present invention.In other embodiments, if needed, multiple control bit also can be utilized to control identical clock frequency.In a possibility embodiment, frequency divider 709 has toggle flip-flop (toggleflip-flop) connected in series or T-shaped register ... etc. (not shown).The cycle time of each latch is the twice of a upper latch.Clock signal C 20NS, C40NC ..., C2.6MS is provided to clock selecting square 711.Clock selecting square 711, according to the time numerical value PG_TIME<19:0> of 20, using in received clock signal as signal PG_CLK, and outputs signal PG_CLK.At one time, time numerical value PG_TIME<19:0> only has a position and is triggered, in order to select a corresponding clock signal from the corresponding clock cycle.Clock selecting square 711 may integrate at least one multiplexer or other selects logic (as NAND/NOR).
According to numerical value PG_TIME<19:0>, signal PG_CLK can have a cycle time, this cycle time be cycle time 20ns, 40ns, 80ns, 160ns ..., in 2.6ms one.In a possibility embodiment, at one time, numerical value PG_TIME<19:0> only has one and is triggered, in order to select the cycle time as signal PG_CLK in 18 cycle times.In a possibility embodiment, low selection position (closest to the rightmost significance bit) correspondence of numerical value PG_TIME<19:0> has the signal PG_CLK (having maximum frequency) of time minimum period.When selecting position toward when moving to left, the cycle time of signal PG_CLK becomes large.In other words, the cycle time (frequency is maximum) that the least significant bit of numerical value PG_TIME<19:0> is corresponding minimum, and the cycle time (frequency is minimum) that the highest significant position of numerical value PG_TIME<19:0> is corresponding maximum.More enter one, under power gating and recovery operation, the cycle time of signal PG_CLK determines regulation time.
Clock generator 707 may go back Received signal strength PGATE, V_DWN, PG16 and PG_KILL_CORE1, in order to the operation of control signal PG_CLK.In another possibility embodiment, at least one in these signals may be provided.In addition, frequency divider 709 and/or clock selecting square 711 perform identical function.Under normal operation, signal PGATE1 can not be triggered, therefore signal PG_CLK can not action, and can be maintained at a ready state numerical value, if a ready low logic OR is logical zero.When signal PGATE1 is triggered, when operating in order to the control of initialize power lock, being disabled of signal PG16 (as being pulled to high level), in order to close relevant PMOS device, and signal PG_CLK has a selection frequency.When being disabled of signal PGATE1, recovering logic 701 triggering signal RESUME, return to its normal operation voltage level in order to make voltage VDD1.After completing Recovery processing, signal PG16 can be triggered to low level, in order to stop the start of clock signal PG_CLK.
When carrying out power gating, when signal V_DWN is triggered, signal PG_CLK can be positioned at its ready state numerical value momently, until after Voltage Cortrol, and when being disabled of signal V_DWN, signal PG_CLK is activated again.Because the weight of signal PG_KILL_CORE1 operates higher than power gating, therefore the PMOS device that can be coupled between voltage VDD0 and VDD1 by closedown, in order to kernel 101 is isolated with voltage VDD0.When signal PG_KILL_CORE1 is triggered, then the action (therefore, signal PG_CLK can be triggered to its ready state numerical value) of stop signal PG_CLK.When signal PG_KILL_CORE1 being then disabled time, signal PG_CLK can be activated again, and initialization recovery operation, in order to voltage VDD1 to be returned to its normal operation voltage level.
Temporal decoder 712 receives a control word numerical value PG<15:0>, inversion signal HIER or HIERB, signal RESUME and many guarantors are except silk (or scanning) coefficient is (as PU_FU_HIERB, PG_FU_ENT<10:5>, PG_FU_RES_PER<1:0>, PG_FU_CONST_RES_CLK), and by position one of in trigger value PG_TIME<19:0>, in order to select the cycle time as signal PG_CLK between 20ns ~ 2.6ms.Inverter 710 Received signal strength HIER, and output signal HIERB.Power gating operation under and leave power gating operation enter recovery operation under, the cycle time of signal PG_CLK determines the adjustment cycle of control word PG_CNTRL<16:0>.
According to of control word itself, the also cycle of adjustable signal PG_CLK.As mentioned above, under power gating, being disabled of highest order PG_CNTRL<16> (as being toggled to high level) of control word time (as being toggled to low level), closes many PMOS transistor and the position PG_CNTRL<11:0> of control word is initialised.Select an initial period and a values of disparity of signal PG_CLK, in order to when signal PG_CLK action, reduce control word gradually.When control word is reduced to a default value, the cycle of signal PG_CLK may be adjusted to the slowest adjustment cycle, and this default value is programmed among temporal decoder 712 in advance.For example, when the position PG_CNTRL<11> of control word is high level (ineffective treatment), the cycle of signal PG_CLK may double.When the position PG_CNTRL<10> of control word is high level (ineffective treatment), the cycle of signal PG_CLK may be increased one times again.Therefore, control word is own in order to adjust the cycle of signal PG_CLK.Control word may be programmed to any numerical value, in order to select the corresponding clock cycle.
Signal HIER represents voltage VDD1 lower than preset threshold magnitude of voltage, and signal HIER may in order to adjust the cycle of signal PG_CLK.For example, when signal HIER is triggered to low level, represent that voltage VDD1 has reached the highest critical voltage level, therefore, the clock cycle of signal PG_CLK may increase close to final voltage level along with the level of voltage VDD1, final voltage level is as shown in symbol HIGH, and it is in order to retain data and the state of kernel 101.For example, in some embodiments, voltage VDD1 drops to final voltage level 450mV by 1.05V, and now signal HIER is approximately configured to 550mV.Signal HIGH may be configured to represent that final voltage level is 450mV.Therefore, when voltage VDD1 reaches the critical voltage level 550mV represented by signal HIER, reduce the cycle of signal PG_CLK, adjust frequency, to reduce the possibility of voltage VDD1 lower than final voltage level in order to reduce.In a possibility embodiment, when voltage VDD1 reaches the critical voltage level represented by signal HIER, the cycle of signal PG_CLK becomes four times originally.
In other embodiments, the cycle of the critical voltage adjustment signal PG_CLK of other quantity can be utilized.For example, voltage VDD1 often decline 100mV time, the cycle of signal PG_CLK may double.
When signal RESUME is triggered, during in order to leave power gating, signal PG_CLK may also can be adjusted.For example, when signal RESUME is triggered, the cycle time of signal PG_CLK can be reduced, get back to the speed of normal voltage level in order to accelerate voltage VDD1.For example, when signal RESUME is triggered, selected summed values can be added to the position PG<15:0> of control word, in order to upgrade control word PG_CNTRL<16:0>.It is to be noted, however, that owing to may causing inrush current or causing a current impulse to enter kernel 101, therefore adjusting action should be too fast, and the electric charge caused because of electric current is shared at least one operation in impact around kernel 102 ~ 104.Therefore, when the power-up speeds of kernel 101 is too fast, voltage VDD0 can be caused to decline, thus affect other kernel or peripheral circuits.
Power gating system 201 also comprises a power gating device 713, in order to provide control word PG_CNTRL<16:0> and PG<15:0>, word PG<15:0> is the lower 16 of control word PG_CNTRL<16:0>, will be illustrated in after a while in Figure 11.Power gating device 713 Received signal strength PG_FU_X, PGATE1, RESUME, PG_KILL_CORE1, V_DOWN<4:0>, V_DWN, CMP1 ~ CMPN (comprising HIGH and HIER) and PG_CLK.As mentioned above, signal PG_FU_X comprises fuse or scanning numerical value PG_FU_ADD_GN, PG_FU_SUB_GN, PG_FU_HIERB, PG_FU_ENT<10:5>, PG_FU_RESUME_GN<1:0>, PG_FU_RES_PER<1:0>, PG_FU_CONST_RES_CLK and PG_FU_RESUME_STOP, in order to adjust Energy control process.
Fig. 8 is that one of power gating device 713 may embodiment.Power gating device 713 comprises increment control algorithm word adjuster 801, integral traffic control word adjuster 803, Parasites Fauna 805 and a control word logic 807.Parasites Fauna 805 has multiple register, the corresponding position in corresponding lower 16 of the control word of each register.The character PG<15:0> that increment control algorithm word adjuster 801 receives and control word logic 807 produces, and character PG<15:0> is added or deducts an adjustment numerical value, in order to produce and to export control word numerical value OPB<15:0>.Control word logic 807 judges the highest significant position of control word PG_CNTRL<16>, will illustrate after a while.
To be a summed values or a values of disparity be adjustment numerical value depends on in increase or reduce control word PG_CNTRL<16:0>.Should be noted that, in the present embodiment, in order to control the transistor of P channel (as PMOS), therefore the position of control word PG_CNTRL<16:0> is anti-phase, and the increment of control word PG_CNTRL<16:0> or decrement depend on the size of the transistor of P channel.In order to carry out power gating, just needing to carry out decrement to control word, such as, whether being triggered according to signal PGATE1, or being fully disabled, such as whether be triggered according to signal PG_KILL_CORE1, and reduce the voltage of power gating voltage VDD1.By increment control algorithm word, in order to increase the level of voltage VDD1, as returned normal running according to signal RESUME.May in embodiment one, summed values and values of disparity are all proportionate relationship with the current numerical value of control word, as the number of times y moved to right according to control word, utilize 2 ydistribute control word, in order to judge adjustment numerical value.Numerical value PG_FU_SUB_GN in order to change or may adjust the number of times y moved to right, in order under power gating operation, and the gain of adjustment adjustment.Summed values may be defined by similar method, and signal PG_FU_ADD_GN may be utilized to adjust summed values.
The anti-phase minimum detectable signal HIGH of inverter 810, in order to provide an anti-phase minimum detectable signal HIGHB.Inverter 812 inversion signal PG_KILL_CORE1, in order to provide an anti-phase abort signal KILLB.Increment control algorithm word adjuster 801 Received signal strength PG_KILL_CORE1, anti-phase abort signal KILLB and signal RESUME.In the present embodiment, in symbol, there is " B " to represent that it is an inverted version, do not need to add to explain.Signal HIGHB, KILLB and RESUME in order to select a summed values or a values of disparity, in order to increase or reduce control word.For example, under power gating, selection differences numerical value, in order to reduce control word and voltage VDD1.When voltage VDD1 arrives final voltage level, signal HIGH and HIGHB can be transformed into anti-state.If selection summed values, then in order to increase control word and voltage VDD1.When voltage VDD1 is greater than end value, signal HIGH and HIGHB can transition again, and selection differences numerical value again.In the present embodiment, aforesaid operations may repeat, until signal RESUME is triggered.When the state of signal HIGH can retain data, summed values may be greater than values of disparity, in order to reduce the frequency of oscillator.When signal RESUME is then triggered, the summed values be chosen to, by increasing the level of voltage VDD1, makes it return to normal level.Signal KILLB represents for carrying out full power gating operation, now can ignore signal HIGHB.
Integral traffic control word adjuster 803 receives adjustment control word OPB<15:0>.When being triggered for one of signal group V_DOWN<4:0>, as shown in symbol V_DWN, integral traffic control word adjuster 803 adjusts control word once.For example, under power gating, when estimating to downgrade voltage VDD0, the increment that adjustment increases control word need be integrated, cause the state of kernel 101 to lose to avoid voltage VDD1 lower than final voltage level.When being triggered for one of signal group V_DOWN<4:0>, signal V_DWN also can be triggered, and integral traffic control word adjuster 803 is according to the certain bits be triggered of signal group V_DOWN<4:0>, adjustment control word.
In the present embodiment, integral traffic control word adjuster 803 exports three different control word numerical value, comprises an anti-phase removing numerical value CB<15:0>, an a setting numerical value S<15:0> and value data D<15:0>.Anti-phase removing numerical value CB<15:0>, setting numerical value S<15:0> and value data D<15:0> are input to anti-phase removing input CB, the set input S and data input pin D of Parasites Fauna 805 respectively.As signal PG_CLK and not operating time, initialization and the integral traffic control tone of Chinese characters whole time, anti-phase removing numerical value CB<15:0> is with setting numerical value S<15:0> and asynchronously input to Parasites Fauna 805.When signal PG_CLK action, value data D<15:0> is synchronously inputed to Parasites Fauna 805.Integral traffic control word adjuster 803 also utilizes signal PG_KILL_CORE1 and PGATE1, in order to produce signal GATE and anti-phase result thereof, as GATEB.Control word logic 807 Received signal strength GATE.Signal GATE and GATEB is in order to produce an initial control word.
Parasites Fauna 805 Received signal strength PG_CLK " keeping in " result of control word after exporting adjustment, as shown in symbol ROPB<15:0>, control word may intactly be adjusted or no.Control word logic 807 receives control word ROPB<15:0>.Control word ROPB<15:0> is non-synchronously configured to an initial value.In all processes of adjustment, when signal PG_CLK stops, anti-phase removing numerical value CB<15:0> is utilized non-synchronously to upgrade control word ROPB<15:0> with setting numerical value S<15:0>.Under power gating and recovery operation, utilize value data D<15:0>, control word ROPB<15:0> is synchronously updated along with signal PG_CLK.
Control word logic 807 comprises a logical circuit, in order to control word ROPB<15:0> to be converted to the low level of control word, as PG_CNTRL<15:0>.Control word logic 807 comprises a logical circuit, it is according to signal PG_KILL_CORE1, RESUME, PGATE1 and PG_FU_RESUME_STOP, produces the highest order PG_CNTRL<16> (as PG16) of control word PG_CNTRL<16:0>.Control word logic 807 utilizes control word ROPB<15:0> and PG_KILL_CORE1, produce numerical value PG<15:0>, and numerical value PG<15:0> is supplied to increment control algorithm word adjuster 801 and temporal decoder 712.
Fig. 9 is that one of increment control algorithm word adjuster 801 of the present invention may embodiment.Increment control algorithm word adjuster 801 may have a current limliting 901.Current limliting 901 is protected as one, to avoid electric current too high or too low.As described below, numerical value PG<15:0> moved to right one select number of times, in order to produce adjustment numerical value.When numerical value PG<15:0> arrives a specific low numerical value, the knots modification of voltage VDD1 may be allowed to surpass the expectation.For example, when voltage VDD1 is in low level, if trace reduces numerical value PG<15:0>, then voltage VDD1 may be made lower than the minimum levels that can maintain data.In the present embodiment, current limliting 901 limits the minimum value of numerical value PG<15:0> is 1111111111100000b (the anti-phase digital codes as 31).
Current limliting 901 receives numerical value PG<15:0> and provides many restriction numerical value PGTWO, PGTHREE, PGFOUR, PGFIVE and PGSIX.Each limits numerical value in order to replace the least significant bit (LSB) of the numerical value after a displacement, presets minimum levels in order to prevent the numerical value after displacement lower than one.In a possibility embodiment, default minimum levels has 32 digital codes.Specific restriction numerical value is according to the number of times that moves to right of shift value.For example, numerical value PGTWO is limited in order to carry out moving to right of secondary; Limit numerical value PGTHREE in order to carry out three times move to right; Limit numerical value PGFOUR in order to carry out four times move to right; Limit numerical value PGFIVE in order to carry out five times move to right; Limit numerical value PGSIX in order to carry out six times move to right.
Multiplexer (MUX) 903 has input 0, input 1, and selects input S and an output.Input 0 receives numerical value <*6>VSS0, PG<15:7>, PGSIX.Input 1 receives numerical value <*5>VSS0, PG<15:5>.Select input S Received signal strength PG_FU_SUB_GN.The output of multiplexer 903 provides a values of disparity SUB<15:0>.In the present embodiment, although only show single multiplexer 903, the symbol " X16 " of multiplexer 903 inside represents that 16 multiplexers in parallel connect, 1 in each multiplexer process 16.Identical mark mode is also applied in other multiplexer, latch register and gate.Symbol " <*6>VSS0 " represents 6 logical zeros, in order to form the numerical value of leftmost bit, then be the higher 9 of PG<15:0>, i.e. PG<15:7>, then be numerical value PGSIX, numerical value PGSIX is as the least significant bit of final numerical value.<*6>VSS0, PG<15:7> and PGSIX are that numerical value PG<15:0> moves to right the result after 6 times, and 6 logical zeros are inserted in the leftmost side, recycling numerical value PGSIX is as the least significant bit of final numerical value.1/64 (be namely reduced to preset and limit numerical value) of the numerical value of final numeric representation control word PG<15:0>.Numerical value <*5>VSS0, PG<15:5> are formed in the same way, and difference is only to move to right 5, and does not use restriction numerical value.Therefore, numerical value <*5>VSS0:PG<15:5 > represents 1/32 of control word PG<15:0>.
Default value PG_FU_SUB_GN is logical zero, therefore numerical value <*6>VSS0, PG<15:7> and PGSIX are as the default value (the anti-phase output as multiplexer 903) of values of disparity SUB<15:0>, it represents the gain of 1/64 of the numerical value of control word numerical value PG<15:0>, the adjustment numerical value namely reduced.When default value PG_FU_SUB_GN is triggered to logical one, numerical value <*5>VSS0:PG<15:5 > can by as values of disparity SUB<15:0> (anti-phase after), it represents the gain of 1/32 of the numerical value of control word numerical value PG<15:0>, the adjustment numerical value namely reduced.
The input A of the subtracter 905 of 16 receives control word PG<15:0>, its input B and receives values of disparity SUB<15:0>.The numerical value of input A is deducted the numerical value of input B by subtracter 905, and provides values of disparity FSUB<15:0> by output.In the present embodiment, 1/64 or 1/32 of control word PG<15:0> is represented according to difference gain values PG_FU_SUB_GN, values of disparity FSUB<15:0>.
Add overall gain also can define in an identical manner, but under power gating and recovery operation, can produce that a large amount of to add overall gain for you to choose.Multiplexer 907 has input 0 ~ 3, receiving gain numerical value <*2>VSS0:PG<15:3 >:PGTWO respectively, <*3>VSS0:PG<15:4 >:PGTHREE, <*4>VSS0:PG<15:5 >:PGFOUR and <*5>VSS0:PG<15:6 >:PGFIVE, above-mentioned gain values represents 1/4 respectively, 1/8, the value added gain of 1/16 and 1/32, and each has corresponding least significant bit restriction numerical value.Multiplexer 907 exports anti-phase position, and is supplied to inverter 909.The output of the anti-phase multiplexer 907 of inverter 909, and using anti-phase result as a summed values ADD<15:0>.Multiplexer 907 and 903 has identical characteristic, and multiplexer 907 has symbol " X16 ", and it is in order to represent 16 multiplexers in parallel.Similarly, inverter 909 has the symbol of " X16 ", is also to represent 16 inverters in parallel.Add value decoder 911 and select a gain values according to signal RESUME, PG_FU_ADD_GN and PG_FU_RESUME_GN<1:0>.Add in value decoder 911 trigger output signal S0 ~ S3.Multiplexer 907 according to output signal S0 ~ S3 trigger condition, the gain values received by I/O 0 ~ 3.
Add value decoder 911 according to signal RESUME, PG_FU_ADD_GN and PG_FU_RESUME_GN<1:0>, one in trigger output signal S0 ~ S3, in order to select value added gain.Signal PG_FU_RESUME_GN<1:0> is only useful in when signal RESUME is triggered in the recovery operation of logical one.Signal PG_FU_ADD_GN is only useful in when signal RESUME is triggered in the power gating operation of logical zero.
When signal RESUME and PG_FU_ADD_GN is logical zero, signal PG_FU_RESUME_GN<1:0> can be logical zero or 1, namely unknown state (don ' tcare), therefore, the place value adding the input signal of value decoder 911 is 00XX, therefore, add value decoder 911 trigger output signal S3, in order to select value added gain <*5>VSS0:PG<15:6 >:PGFIVE, also be with regard to 1/32 gain, in order to carry out power gating operation.When signal RESUME is logical zero and signal PG_FU_ADD_GN is logical one, the place value adding the input signal of value decoder 911 is 01XX, therefore, add value decoder 911 trigger output signal S2, in order to select value added gain <*4>VSS0:PG<15:5 >:PGFOUR, namely 1/16 gain, to carry out power gating operation.
When signal RESUME is logical one, the place value of signal PG_FU_RESUME_GN<1:0> is in order to determine the gain of the summed values under recovery operation.In the present embodiment, the place value of signal PG_FU_RESUME_GN<1:0> is respectively 00, 01, when 10 and 11, to make to add value decoder 911 trigger output signal S3 ~ S1 respectively, in order to select <*5>VSS0:PG<15:6 >:PGFIVE (or 1/32 gain) respectively, <*4>VSS0:PG<15:5 >:PGFOUR (or 1/16 gain), <*3>VSS0:PG<15:4 >:PGTHREE (or 1/8 gain) and <*2>VSS0:PG<15:3 >:PGTWO (or 1/4 gain).
The input A of the adder 913 of 16 receives control word numerical value PG<15:0>, and its input B receives value added numerical value ADD<15:0>.Numerical value received by input A and B carries out adding up (A+B) by adder 913, in order to provide and to export summed values FADD<15:0>.It should be noted, in order to control PMOS device, the place value of control word is inverse value, therefore by inverter 909, can help add operation.
The input 0 of 2 input-multiplexers 915 receives summed values FADD<15:0>, its input 1 receives difference value FSUB<15:0>, and its reversed-phase output provides numerical value OPB<15:0>.The symbol " X16 " of 2 input-multiplexers 915 represents that multiplexer 915 is made up of 16 multiplexers in parallel.2 input-AND door 917 Received signal strength KILLB and HIGHB, and provide output signal to give a wherein input of 2 input-NOR doors 919.Another input Received signal strength RESUME of 2 input-NOR doors 919, its output couples the selection input S of 2 inputs-multiplexer 915.Therefore, when signal RESUME is logical one, 2 input-multiplexers 915 export after anti-phase for summed values FADD<15:0> again, in order in recovery operation, increase control word PG_CNTRL<16:0>.When signal RESUME is logical zero, as long as signal KILLB and HIGHB is not high level, export again after 2 input-multiplexers 915 are anti-phase by difference value FSUB<15:0>.When signal PG_KILL_CORE1 is triggered to high level, signal KILLB is low level, in order to carry out full power gating operation.When voltage VDD1 drops to the final critical level being enough to retain data, signal HIGH is low level, and therefore, signal HIGHB is high level, and therefore, summed values selected by 2 input-multiplexers 915, reduces to prevent voltage VDD1 again.
Figure 10 A and Figure 10 B is that one of integral traffic control word adjuster 803 of the present invention may embodiment.Adjustment control word numerical value OPB<15:0> is provided to the input D of bank of latches 1001, and bank of latches 1001 has 16 latchs.The output Q output latch result OOPB<15:0> of bank of latches 1001.The inversion clock input CK Received signal strength V_DWN of bank of latches 1001.When signal V_DWN is triggered to low level, bank of latches 1001 is conduction mode, not processing controls number of words value OPB<15:0>, and directly control word numerical value OPB<15:0> is exported as latch result OOPB<15:0>.When signal V_DWN is triggered to high level, bank of latches 1001 switches to isolation mode, no matter how control word numerical value OPB<15:0> changes, and the latch result OOPB<15:0> of output immobilizes.
The position of latch result OOPB<15:0>, after 16 inverters 1003 are anti-phase, becomes another adjustment control word numerical value VOP<15:0>.Numerical value VOP<15:0> is moved to right once, and fill VSS0 (logical zero), just numerical value VSS0:VOP<15:1> can be formed, wherein low 15 as numerical value VSS0:VOP<15:1> of VOP<15:1>.Therefore, numerical value VSS0:VOP<15:1> is 1/2 of numerical value VOP<15:0>.The input A<15:0> of the adder 1005 of 16 receives numerical value VOP<15:0>, its input B<15:0> receives numerical value VSS0:VOP<15:1>, its output provides numerical value DOP<15:0>, and it is 1.5 times of raw value VOP<15:0>.
By numerical value VOP<15:0> and DOP<15:0>, 1.5 times of raw value VOP<15:0>, 2 times, 3 times, 4 times and 6 multiple value just can be provided.As mentioned above, numerical value DOP<15:0> is 1.5 times of numerical value VOP<15:0>.Numerical value VOP<14:0> is that numerical value VOP<15:0> moves to left the result of 1, and fills voltage VDD0 at least significant bit.Therefore, numerical value VOP<14:0>:VDD0 is 2 times of numerical value VOP<15:0>.Similarly, numerical value DOP<14:0>:VDD0 is that numerical value DOP<15:0> moves to left the result of 1, therefore is 3 times of VOP<15:0>.In addition, numerical value VOP<13:0>:<*2Gre atT.GreaT.GTVDD0 represents that VOP<15:0> moves to left the result of 2, and 2 VDD0 are filled in the rightmost side, therefore, it can represent 4 times of numerical value VOP<15:0>.Similarly, numerical value DOP<13:0>:<*2Gre atT.GreaT.GTVDD0 represents 6 times of numerical value VOP<15:0>.
The input 0 ~ 4 of multiplexer 1007,1009 and 1011 receives 1.5 times, 2 times, 3 times, 4 times of numerical value VOP<15:0> and the numerical value of 6 times respectively.The symbol " X16 " of multiplexer 1007,1009 and 1011 represents 16 multiplexers in parallel.The input 5 of multiplexer 1011 receives raw value VOP<15:0>.2 input-NOR door 1013 Received signal strength PG_KILL_CORE1 and PGATE1, and export an inverse gate signal GATEB.Inverter 1015 receives inverse gate signal GATEB and produces signal GATE.The input 5 of multiplexer 1007 receives numerical value <*4>VSS0:<*12Gre atT.GreaT.GTGATEB.The input 5 of multiplexer 1009 receives numerical value <*4>GATE:<*12Gre atT.GreaT.GTVDD0.The output of multiplexer 1007,1009 and 1011 provides anti-phase removing numerical value CB<15:0>, setting numerical value S<15:0> and value data D<15:0> to give Parasites Fauna 805 above respectively.
V_DOWN decoder 1017 Received signal strength group V_DOWN<4:0>, and the input S0 ~ S5 outputing signal that S0 ~ S5 gives multiplexer 1007,1009 and 1011.Signal group V_DOWN<4:0> is preferential decoding, therefore at one time under, if the multidigit of signal group V_DOWN<4:0> is triggered, then a meeting triggering signal group V_DOWN<4:0>'s is the highest one.Therefore, the highest order of V_DOWN decoder 1017 couples of signal group V_DOWN<4:0> is decoded, and triggers corresponding output signal S0 ~ S5, in order to adjust a control word.When signal V_DOWN<0> is triggered, then select signal S0, in order to carry out the adjustment of 1.5 times.When signal V_DOWN<1> is triggered, then select signal S1, in order to carry out the adjustment of 2 times.When signal V_DOWN<2> is triggered, then select signal S2, in order to carry out the adjustment of 3 times.When signal V_DOWN<3> is triggered, then select signal S3, in order to carry out the adjustment of 4 times.When signal V_DOWN<4> is triggered, then select signal S4, in order to carry out the adjustment of 6 times.When signal group V_DOWN<4:0> does not have position to be triggered, triggering signal S5.Multiplexer 1007,1009 and 1011, according to the signal S0 ~ S5 be triggered, carries out anti-phase to the signal received by corresponding input, then exports anti-phase result.
Integral traffic control word adjuster 803 is described in Fig. 8 and Figure 10.Power on give microprocessor 100 and/or kernel 101 time, or reset microprocessor 100 and/or kernel 101 time, signal group V_DOWN<4:0> does not have position and is triggered, therefore, can not triggering signal V_DWN.Latch 1001 is delivery status, and signal PG_CLK maintains low level, and therefore, Parasites Fauna 805 is failure to actuate, and V_DOWN decoder 1017 triggers the signal S5 of multiplexer 1007,1009 and 1011.Because Parasites Fauna 805 is failure to actuate, therefore, data export being disabled of D<15:0>.In addition, the input 5 of multiplexer 1007 and 1009 also can couple anti-phase removing input and the set input of Parasites Fauna 805, in order to signal ROPB<15:0> is initialized to 1111000000000000b.Simultaneously input 5 due to multiplexer 1007 and 1009 is triggered, therefore Parasites Fauna 805 will be made to transmit logical zero from the anti-phase removing position of multiplexer 1007, is total to and Parasites Fauna 805 will be made to transmit logical one from the setting position of multiplexer 1009.
In the present embodiment, the highest significant position of signal PG_CNTRL, i.e. signal PG16, control the PMOS device of a specific quantity, and other PMOS device controlled by signal PG_CNTRL<15:0>.In this example, signal PG_CNTRL<15:0> is binary weighting.In this instance, under normal operation, signal PG16 controls important PMOS device (as maximum quantity), and in order to effectively the strangulation of lock control supply bus 206 is supplied bus 109 in integration, and other PMOS device is lower for the level impact of voltage VDD1.When signal PGATE1 is triggered, when operating in order to the control of initialize power lock, being disabled of signal PG16, in order to remove voltage clamping effect, the PMOS device of right quantity continues switched on, in order to make the rough level equaling voltage VDD0 of the level of voltage VDD1.Although the low level PG_CNTRL<15:0> of control word is used for carrying out power gating operation, in other embodiments, the position of other quantity may be used.
In the present embodiment, under normal operation, control word PG_CNTRL<16:0> is 01111000000000000b, therefore the low level PG_CNTRL<11:0> of control word is low level, and interposition PG_CNTRL<15:12> is high level, therefore, under normal operation, the PMOS device of a specific quantity is switched on.In the present embodiment, powering on, to reset and under normal running, the level in lock control supply bus 206 is become to integrate the level in supply bus 109 by strangulation effectively, and kernel 101 may normally work.When signal PGATE1 is triggered, during in order to the control of initialize power lock, signal PG16 can being disabled, when the control of initialize power lock, and the PMOS device no longer conducting of conducting because of low level PG_CNTRL<11:0> originally.Therefore, decrease the quantity of PMOS device switched on, in order under power gating operation, the level of voltage VDD1 is reduced to final voltage level, and the state information of kernel can be retained.In another embodiment, under power gating function, the initial value of control word PG_CNTRL<16:0> may be adjusted, in order to control more or less PMOS device.
When signal PGATE1 is triggered, during in order to carry out power gating operation, if when signal group V_DOWN<4:0> still maintains non-trigger state, latch 1001 maintains conducting state, and signal PG_CLK maintains identical frequency, in order to when power gating, reduce the size of control word PG_CNTRL<16:0>.Therefore, the level of voltage VDD1 is similar in appearance to voltage VDD0.V_DOWN decoder 1017 triggering signal S5, because signal PG_CLK is effective status, therefore select the numerical value VOP<15:0> of the input 5 of multiplexer 1011 as value data D<15:0>, and be supplied to the data input pin of Parasites Fauna 805.In the present embodiment, under normal power source lock control operation, by the signal PG_CLK of continuous trigger, adjustment is update signal ROPB<15:0>, PG<15:0> and PG_CNTRL<15:0> also, until the level of voltage VDD1 arrives final voltage level.
Under power gating, no matter which position of signal group V_DOWN<4:0> is triggered, signal V_DWN all can be triggered, and makes the output signal of latch 1001 maintenance itself, and supspends signal PG_CLK.One in V_DOWN decoder 1017 trigger output signal S0 ~ S5 and multiplexer 1007 and 1009 are according to the signal be triggered, the signal of one in I/O 0 ~ 4, in order to utilize the control word of different multiples (as: 1.5,2,3,4,6 times), non-synchronously upgrade Parasites Fauna 805, thus upgrade control word PG_CNTRL<16:0>.As mentioned above, when being updated for one of signal group V_DOWN<4:0>, represent downgrading of voltage VDD0 level, therefore, upgrade control word PG_CNTRL<16:0>, and the level increasing voltage VDD1 once, to avoid the level of voltage VDD1 too low.
Figure 11 is that one of control word logic 807 may execution mode.As mentioned above, control word logic 807 receiving register group 805 the control word ROPB<15:0> that keeps in.Inverter 1101 Received signal strength RESUME.The output of inverter 1101 couples a pair 2 input-NOR doors 1103 and 1105.Another input Received signal strength ROPB<14> of 2 input-NOR doors 1103.Another input Received signal strength ROPB<13> of 2 input-NOR doors 1105.The output of 2 input-NOR doors 1103 and 1105 couples the input 1 and 0 of 2 inputs-multiplexer 1107 respectively.The input S Received signal strength PG_FU_RESUME_STOP of 2 input-multiplexers 1107, its output provides a stop signal STP.Setting-reset (set-reset; SR) the replacement input R of latch 1109 receives stop signal STP.The set input S Received signal strength GATE of SR latch 1109.The control bit ROPB<16> that signal GATE exports in order to the output Q triggering SR latch 1109.Signal ROPB<15:0> and ROPB<16> provided by numerical value ROPB<16:>, in order to produce above-mentioned control word PG_CNTRL<16:0>.
When operating, signal GATE, RESUME and ROPB<16> are initially become low level, and signal ROPB<13> and ROPB<14> is initially become high level.Because signal ROPB<16> is configured to low level under normal operation, therefore, signal PG_CNTRL<16> (i.e. highest significant position PG16) can be pulled down to low level, thus the PMOS device that conducting is maximum, in order to the level making the level of voltage VDD1 equal voltage VDD0.When signal RESUME is low level, no matter the level of signal PG_FU_RESUME_STOP why, 2 input-multiplexers 1017 make stop signal STP be low standard.When the control of initialize power lock operates, signal GATE can be configured to high level, therefore, signal ROPB<16> is triggered into high level by SR latch 1109, therefore a considerable amount of PMOS device of not conducting, these PMOS devices are coupled between voltage VDD0 and VDD1.But because kernel 101 enters idle mode, therefore, voltage VDD1 does not have sizable change.When signal PG_KILL_CORE1 or PGATE1 is triggered to low level, when operating in order to stop power gating and get back to normal running, signal GATE changes over low level, and signal RESUME changes over high level.Signal ROPB<13> and ROPB<14> is still high level, and therefore, stop signal STP maintains low level.
Under a preset state, signal PG_FU_RESUME_STOP is low level, and therefore, the output signal of 2 input-NOR doors 1105 selected by 2 input-multiplexers 1107, namely outputs signal the anti-phase result of ROPB<13>.Signal ROPB<15:0> can be increased, until signal ROPB<13> is triggered to low level, therefore, stop signal STP is triggered to high level, in order to reset SR latch 1109, and signal ROPB<16> gets back to low level, thus signal PG_CNTRL<16> is arranged to low level, in order to the many PMOS devices of conducting, and the level strangulation of voltage VDD1 is become the level of voltage VDD0.If a number PG_FU_RESUME_STOP is programmed to high level, the output signal of 2 input-NOR doors 1103 selected by 2 input-multiplexers 1107, and therefore, 2 input-multiplexers 1107 output signal the anti-phase result of ROPB<14>.In the Recovery processing that other is longer, operation is identical, except stop signal STP can not be configured to high level, until signal ROPB<14> is configured to low level.Stop signal depends on by the position PG_CNTRL<16> selected in control word, and it represents a minimum stopping numerical value.In other words, become special value once control word, just effectively can stop Recovery processing, therefore, may normal running be continued.
Be high level once stop signal STP, signal ROPB<16> is pulled down to low level by high level by SR latch 1109, in order to the level of the pressure VDD0 that the level strangulation of voltage VDD1 wired back, and enters normal running.Signal RESUME gets back to low level, and control word is initialized to 01111000000000000b by integral traffic control word adjuster 803 again, signal ROPB<13> and ROPB<14> is made to get back to high level.In a possibility embodiment, when recovery operation is stopped according to the numerical value of control word, a programming numerical value can be utilized, as fuse or scanning ... etc., reset control word.Therefore, under normal operation, the level of voltage VDD1 gets back to the level of its setting originally.
In another possibility embodiment, in order to control signal ROPB<16>, signal PGATE1 can be provided to give clock controller 706, it can provide one synchronously to keep in result (as PGATE1R; Do not show).When signal PGATE1 is changed to high level, synchronously temporary result, as PGATE1R, be also changed to high level, until the tail end of recovery operation, when signal PG16 is high level, signal PGATE1 can not get back to low level.In the present embodiment, signal PGATE1R (replacing signal PGATE1) is provided to the input of 2 input-NOR doors 1013, in order to change signal GATE.The output signal of 2 input-multiplexers 1107 also can be inverted, and an AND door (not shown) can be utilized to replace SR latch 1109, in order to Received signal strength GATE and STP.In this instance, signal STP can be pulled to high level (instead of low level).Due under normal operation, signal GATE is low level, therefore signal ROPB<16> is also low level.When power gating, signal PGATE1 is pulled to high level, therefore signal GATE changes to high level, and because signal STP is also high level, therefore, signal ROPB<16> is pulled to high level.When initialization recovery operation, when being disabled of signal PGATE1 is to low level, signal GATE1 maintains high level (because being controlled by PGATE1R, instead of PGATE1), and signal STP is also high level.When signal STP is pulled down to low level, during in order to stop recovery operation, signal ROPB<16> also can be triggered to low level.When signal ROPB<16> is low level, be low level by pulldown signal PG16, make signal GATE get back to low level, in order to maintain signal ROPB<16> in low level.Getting back to of control word PG_CNTRL<16:0> initial value, signal ROPB<13> and ROPB<14> is made to be high level, therefore, signal STP is pulled up and gets back to high level (in another embodiment, the output of 2 input-multiplexers 1107 can be inverted, the state of the signal STP namely in anti-phase Figure 11).
Inverter 812 inversion signal PG_KILL_CORE1, in order to produce signal KILLB.Inverter 1111 inversion signal KILLB, in order to produce signal KILL.Inverter 1113 inversion signal KILL, in order to produce another anti-phase result, as KILLBB.NAND door group 1115 has 7 NAND doors (representing with symbol " X7 "), a corresponding position of each NAND door Received signal strength ROPB<6:0>, each NAND door Received signal strength KILLBB.NAND door group 1115 produces low level signal PG<6:0>.NOR door group 1117 has 9 NOR doors (representing with symbol " X9 "), a corresponding position of each NOR door Received signal strength ROPB<15:7>, all NOR door Received signal strength KILL.NAND door group 1117 provides high signal PG<15:7>.When signal PG_KILL_CORE1 is low level, control the anti-phase result that numerical value PG<15:0> is signal ROPB<15:0>, namely control word PG_CNTRL<15:0>.When signal PG_KILL_CORE1 is high level, low level signal PG<6:0> can be triggered to high level, and high level signal PG<15:7> can be pulled down to low level, therefore, signal PG<15:0> can be configured to an initial value 0000000001111111b.Furthermore, the initial value of signal PG<15:0> is in order to after full power gating operation, under recovery operation, when signal PG_KILL_CORE1 then by under retract low level time, initialization control word PG_CNTRL<16:0>.As shown in Figure 8, the control word PG<15:0> after integration is supplied to and increases progressively control word adjuster 801 and temporal decoder 712.Gate 1115 and 1117 action according to anti-phase result KILLBB and the KILL of gate 812,1111,1113, and the position of control word is selected according to signal ROPB, in order to form initialization logic, it can under full power gating operation, when the signal RESUME representing recovery operation is triggered, the numerical value of initialization control word.
Signal ROPB<15:0> and ROPB<16> forms numerical value ROPB<16:0>, and it is in order to produce control word PG_CNTRL<16:0>.AND door group 1119 has 16 AND doors, and each AND door receives a corresponding position of numerical value ROPB<16:0>.Inverter group 1121 processes numerical value ROPB<16:0>, and result is supplied to another input of AND door group 1119.Inverter group 1121 has 16 inverters in parallel.Always have 6 inverter group 1121 to be cascaded, in order to the signal that Late phase is corresponding, it is by inverter group transmission.Although each of numerical value ROPB<16:0> postpone by 6 inverters, and be not used to limit the present invention, in other embodiments, the delay can carrying out in various degree to each.OR door group 1123 has 16 OR doors, and the output of AND door group 1119 couples corresponding OR door.All OR door Received signal strength KILL of OR door group 1123.The output of OR door group 1123 provides control word PG_CNTRL<16:0>.
When a certain position of control word PG_CNTRL<16:0> is numerical value 1, it closes corresponding PMOS device, if numerical value 0, is then the corresponding PMOS device of conducting.If when a certain position of numerical value ROPB<16:0> changes over numerical value 1 by numerical value 0, the corresponding position of control word PG_CNTRL<16:0> also can change, therefore corresponding PMOS device can be closed, in order to reduce the level of voltage VDD1.Similarly, if when a certain position of numerical value ROPB<16:0> changes over numerical value 0 by numerical value 1, the corresponding position of control word PG_CNTRL<16:0> also can change, thus the PMOS device that conducting is corresponding, in order to increase the level of voltage VDD1.
At one time, when changing multiple position to reduce control word PG_CNTRL<16:0>, a problem may be solved.Specifically, when many positions of control word PG_CNTRL<16:0> become another numerical value from a numerical value change simultaneously, the numerical value of control word PG_CNTRL may be caused to be replaced by 0.The position be substituted, by not conducting PMOS device, thus makes the level of voltage VDD1 decline momently.The of short duration decline of voltage VDD1, may lower than final voltage level.Under such consideration, if the level of voltage VDD1 is too low, the state information of kernel 101 possibly cannot be retained.
Inverter group 1121 and AND door group 1119 can prevent the problems referred to above.When AND door group 1119 processing signals, if when part position is changed to numerical value 0 by numerical value 1 rapidly, by inverter group 1121, these positions can be changing into numerical value 1 by numerical value 0 again.In the present embodiment, the PMOS transistor that be switched on can first be switched on before being turned off rapidly.Therefore, when control word is updated, the level of voltage VDD1 first can be increased momently.The impact that the level that the impact that the level increasing voltage VDD1 momently causes is less than minimizing voltage VDD1 momently causes.
Figure 12 is that one of temporal decoder 712 of the present invention may embodiment.The input Received signal strength PG<15:0> of single focus decoder 1201, and signal PG<15:0> is decoded into numerical value PGT<15:0>.As mentioned above, the initial value of control word ROPB<15:0> is 1111000000000000b, after gate 1115 and 1117 is anti-phase, therefore, under power gating, the initial value of control word ROPB<15:0> is 0000111111111111b.When decoding process, under the same time, numerical value PGT<15:0> only has a meeting to be triggered to high level, and other position is low level, wherein high level represents the position of most important position in signal PG<15:0>, is namely triggered to the position of high level to the position of logical one.In addition, the bit quantity of numerical value PGT<15:0> is relevant with the bit quantity of signal PG<15:0>.In the present embodiment, when the initial value of signal PG<15:0> is 0000111111111111b, then the initial value of numerical value PGT<15:0> is 0000000000010000b, wherein the 4th PGT<4> of numerical value PGT<15:0> is high level, and other position is low level.By reading numerical values PG, just can learn numerical value PGT, as position PGT<4> represents the position of numerical value PG<15:0> number from the left side, the 5th position is exactly most significant bit.Under full power gating operation, when signal PG_KILL_CORE1 is high level, signal PG<15:0> becomes 0000000001111111b, and therefore, numerical value PGT<15:0> is 0000000001000000b.Numerical value PGT<15:0>, in order to generation time numerical value PG_TIME<19:0>, in order to according to operator scheme and control word, selects the frequency of signal PG_CLK.Single focus decoder 1201 can realize by standard NOR/NAND door, or other similar circuit realized.
The high signal PG<15:6> of clock shifter 1203 Received signal strength group PG<15:0> and numerical value PG_FU_ENT<10:5>, in order to provide corresponding numerical value FIVE, SIX, SEVEN, EIGHT, NINE and TEN, in order to carry out displacement to time numerical value, namely adjust the cycle of clock signal PG_CLK.Numerical value PG_FU_ENT<10:5> may by fuse ... etc. programmed, in order to the many parameters according to a certain architectures, as voltage supply capacitance ... etc. displacement is carried out to the time radix of time signal PG_CLK.For example, when the numerical value of control word reduces, PMOS device corresponding to certain bits is closed, therefore signal PG_FU_ENT<10:5> is by coefficient 2, displacement is carried out to the frequency of signal PG_CLK, in order to compensate corresponding RC time coefficient (as increased the cycle of signal PG_CLK, in order to slow down the reaction of adjustment).As mentioned above, C is total capacitance of kernel 101, and R is the resistance value of the power gating device (as PMOS device, 502,504,506,508 and 601) be coupled between voltage VDD0 and VDD1.When closedown or power-on lock control device, RC time coefficient will be changed.
Preset clock selection circuit 1205 Received signal strength PGT<15:0 and RESUME, and under the power gating and recovery operation of local, export Preset Time numerical value DTIME<19:0>.Under the power gating and recovery operation of local, Preset Time numerical value is in order to carry out predetermined period adjustment to signal PG_CLK.Under power gating, also can adjust the clock cycle, as adjusted the particular level of voltage VDD1 and/or control word PG_CNTRL special value.Numerical value DTIME<19:0>, in order under recovery operation, selects signal PG_CLK, and the recovered clock that also non-usage one is fixing.In addition, under power gating (being disabled of signal RESUME), when signal HIERB is triggered to high level, then do not need to consider numerical value DTIME<19:0>.
Signal group PG_FU_RES_PER<1:0> is 2 bit value able to programme (by fuse or scan mode programmings), it can leave power gating operation, and under recovery operation (when signal RESUME is triggered), the cycle of adjustment signal PG_CLK.One fixing recovered clock selection circuit 1207 Received signal strength group PG_FU_RES_PER<1:0>, in order to produce a numerical value PGTIMEB<6:3>.When by fuse ... etc. mode, when signal PG_FU_CONST_RES_CLK is set to high level, then selects the fixing recovered clock cycle able to programme, and ignore normal recovered clock.
Clock period selection device 1209 receives numerical value FIVE, SIX, SEVEN, EIGHT, NINE and TEN and numerical value PG_FU_HIERB, RESUME, HIERB, PG_FU_CNST_RES_CLK, DTIME<19:0> and PGTIMEB<6:0>, and produce numerical value PG_TIME<19:0>, in order to select the cycle of signal PG_CLK.Inverter 1211 inversion signal RESUME, in order to produce signal RESUMEB, and is supplied to clock period selection device 1209 by signal RESUMEB.
Figure 13 is that one of clock shifter 1203 of the present invention may embodiment.Clock shifter 1203 comprises the inverter group 1301 with 6 inverters, the inverter group 1303 with 2 inverters, NOR door 1305,1307,1309,1311,1319,1321,1323,1325,1327,1329 and NAND door 1313,1315 and 1317.There is each signal of the inverter group 1301 inversion signal group PG_FU_ENT<10:5> of 6 inverters, in order to produce corresponding anti-phase numerical value ENB<10:5>.There is the anti-phase numerical value ENB<7:6> of inverter group 1302 of 2 inverters, in order to produce corresponding anti-phase numerical value ENBB<7:6>.NOR door 1305 received bit PG<15:13>.NOR door 1307 received bit PG<12:10>.NOR door 1309 received bit PG<9:8>.NOR door 1311 received bit PG<7:6>.
The output of NOR door 1305 couples the input of NAND door 1313,1315 and 1317.The output of NOR door 1307 couples the input of NAND door 1313,1315 and 1317.The output of NOR door 1309 couples the input of NAND door 1315 and 1317.The output of NOR door 1311 couples the input of NAND door 1317.NAND door 1313,1315 and 1317 outputs signal TENB, EIGHTB and SIXB respectively.
NOR door 1319 Received signal strength ENBB<6> and SIXB, and output signal SIX.NOR door 1321 Received signal strength ENB<8> and EIGHTB, and output signal EIGHT.NOR door 1323 Received signal strength ENB<10> and TENB, and output signal TEN.NOR door 1325 Received signal strength ENB<9>, TENB and PG<9>, and output signal NINE.NOR door 1327 Received signal strength ENBB<7>, EIGHTB and PG<7>, and output signal SEVEN.NOR door 13295 Received signal strength ENB<5>, SIXB and PG<5>, and output signal FIVE.
In the present embodiment, according to the special value of signal group PG<15:6>, signal group PG_FU_ENT<10:5> can be utilized to adjust the cycle of signal PG_CLK, and wherein signal group PG<15:6> is relevant with the corresponding position of control word PG_CNTRL<15:6>.Clock period selection device 1209 according to numerical value FIVE ~ TEN, the clock displacement (in order to increase the clock cycle) needed for execution.Hyte PG_FU_ENT<7:6> presets in advance, therefore, even if position PG_FU_ENT<7:6> can be removed by the corresponding fuse of fusing or setting scan mode afterwards, but on a preset condition based, numerical value SIX and SEVEN will be triggered, in order to carry out displacement.
Figure 14 is that one of default clock selection circuit 1205 of the present invention may embodiment.Preset clock selection circuit 1205 and comprise decoder 1420 and a multiplexer 1413, wherein symbol " X20 " represents 20 multiplexers in parallel.For decoder 1420, NOR door 1401 receives the high-order portion PGT<15:13> of numerical value PGT.NOR door 1403 receives next high-order portion PGT<12:10> of numerical value PGT.NOR door 1405 receives the low portion PGT<5:3> of numerical value PGT.NOR door 1407 receives next low portion PGT<2:0> of numerical value PGT.The input of NAND door 1409 couples the output of NOR door 1401 and 1403.The input of NAND door 1411 couples the output of NOR door 1405 and 1407.NAND door 1409 provides signal PGTHI.NAND door 1411 provides signal PGTLO.
The input 0 of multiplexer 1413 receives the first numerical value <*4>VSS0:PGT<15: 0>, and its input 1 receives second value <*14>VSS0:PGTLO:PGTLEssT.LTss T.LT6>:PGT<7>:P GT<8>:PGT<9Great T.GreaT.GT:PGHI.The selection input S Received signal strength RESUME of multiplexer 1413, its output provides numerical value DTIME<19:0>.First numerical value has 20 positions, and wherein 16 positions are 16 of PGT<15:0>, and add 4 logical zeros (VSS0) in the leftmost side.Second value also has 20 positions, 14 high positions are logical zero (VSS0), are next PGTLO, PGT<6>, PGT<7>, PGT<8>, PGT<9>, PGHI.When signal RESUME is low level (as under power gating operation), using the first numerical value as numerical value DTIME<19:0>.When signal RESUME is high level, using second value as numerical value DTIME<19:0>.
Figure 15 is that one of fixing recovered clock selection circuit 1207 of the present invention may embodiment.Inverter receives hyte PG_FU_RES_PER<1:0> to 1501, and provides corresponding anti-phase numerical value RPERB<1:0>.Inverter receives anti-phase numerical value RPERB<1:0> to 1503, and exports corresponding noninverting numerical value RPER<1:0>.NAND door 1505 received bit RPERB<0> and RPERB<1>, and carry-out bit PGTIMEB<5>.NAND door 1507 received bit RPERB<0> and RPER<1>, and carry-out bit PGTIMEB<3>.NAND door 1509 received bit RPER<0> and RPERB<1>, and carry-out bit PGTIMEB<4>.NAND door 1511 received bit RPER<0> and RPER<1>, and carry-out bit PGTIMEB<6>.Clock period selection device 1209 provides numerical value PGTIMEB<6:3>.When signal PG_FU_CONST_RES_CLK is triggered, clock period selection device 1209 selects the PG_CLK of fixed cycle according to PG_FU_RES_PER<1:0>.
As shown in figure 15, when position PG_FU_RES_PER<1:0> is 10b, position PGTIMEB<3> is triggered.When position PG_FU_RES_PER<1:0> is 01b, position PGTIMEB<4> is triggered.When position PG_FU_RES_PER<1:0> is 00b, position PGTIMEB<5> is triggered.When position PG_FU_RES_PER<1:0> is 11b, position PGTIMEB<6> is triggered.Therefore, in recovery operation, the fixed cycle of signal PG_CLK is according to a simple decoding function.
Figure 16 A and Figure 16 B is that one of clock period selection device 1209 of the present invention may embodiment.As shown in the figure, clock period selection device 1209 comprises many multiplexers with 2 inputs, as 1601,1603,1605,1607,1609,1611,1613,1615 and 1617.Each multiplexer has symbol " X20 ", and what it represented each multiplexer has 20 inputs, in order to receive the time numerical value PG_TIME<19:0> with 20 positions.Multiplexer 1601, when outputing signal, can't carry out anti-phase process, and other multiplexer 1603 ~ 1617 is before output signal, will carry out anti-phase process to signal to signal.Clock period selection device 1209 also comprises many AND doors with 2 inputs, as 1602,1604,1606,1608,1610,1612,1614 and 1616.The selection input S Received signal strength PG_FU_HIERB of multiplexer 1601.Input Received signal strength HIERB and RESUMEB of AND door 1602, its output couples the selection input S of multiplexer 1603.The input of AND door 1604 receives numerical value TEN and signal RESUMEB, and its output couples the selection input S of multiplexer 1605.The input of AND door 1606 receives numerical value of N INE and signal RESUMEB, and its output couples the selection input S of multiplexer 1607.The input of AND door 1608 receives numerical value EIGHT and signal RESUMEB, and its output couples the selection input S of multiplexer 1609.The input of AND door 1610 receives numerical value SEVEN and signal RESUMEB, and its output couples the selection input S of multiplexer 1611.The input of AND door 1612 receives numerical value SIX and signal RESUMEB, and its output couples the selection input S of multiplexer 1613.The input of AND door 1614 receives numerical value FIVE and signal RESUMEB, and its output couples the selection input S of multiplexer 1615.Input Received signal strength RESUME and PG_FU_CONST_RES_CLK of AND door 1616, its output couples the selection input S of multiplexer 1617.
The input 0 of multiplexer 1601 receives numerical value <*2>VSS0:PGT<15: 0>:<*2>VSS0, its input 1 receives numerical value <*3>VSS0:PGT<15: 0>:VSS0, and its output couples the input 1 of next multiplexer 1603.The input 0 of multiplexer 1603 receives numerical value DTIME<19:0>, and its reversed-phase output provides a numerical value PG2T<19:0>.The input 0 of multiplexer 1605 receives numerical value PG2T<19:0>, its input 1 receives numerical value PG2T<18:0>:VDD0, and its reversed-phase output provides a numerical value PG3T<19:0>.The input 0 of multiplexer 1607 receives numerical value PG3T<19:0>, its input 1 receives numerical value PG3T<18:0>:VSS0, and its reversed-phase output provides a numerical value PG4T<19:0>.The input 0 of multiplexer 1609 receives numerical value PG4T<19:0>, its input 1 receives numerical value PG4T<18:0>:VDD0, and its reversed-phase output provides a numerical value PG5T<19:0>.The input 0 of multiplexer 1611 receives numerical value PG5T<19:0>, its input 1 receives numerical value PG5T<18:0>:VSS0, and its reversed-phase output provides a numerical value PG6T<19:0>.The input 0 of multiplexer 1613 receives numerical value PG6T<19:0>, its input 1 receives numerical value PG6T<18:0>:VDD0, and its reversed-phase output provides a numerical value PG7T<19:0>.The input 0 of multiplexer 1615 receives numerical value PG7T<19:0>, its input 1 receives numerical value PG7T<18:0>:VSS0, and its reversed-phase output provides a numerical value PG8T<19:0>.The input 0 of multiplexer 1617 receives numerical value PG8T<19:0>, its input 1 receives numerical value <*13>VDD0:PGTIMEBLEssT.LTssT. LT6:3>:<*3>VDD0, and its reversed-phase output provides a numerical value PG_TIME<19:0>.
Because the multiplexer of part has reversed-phase output, therefore utilize VSS0 and VDD0, in order to add logical zero or 1 after displacement.For example, in multiplexer stacks, after numerical value PG2T, PG4T and PG6T of dual numbers carry out displacement, add VDD0, i.e. logical one, after displacement is carried out to numerical value PG3T, PG5T and PG7T of odd number, add VSS0, i.e. logical zero.In other embodiments, if when multiplexer does not have reversed-phase output, then the numerical value added after needing to adjust displacement.
Below by the operating principle of the temporal decoder 712 of key diagram 7B.Under normal operation, when not carrying out power gating, signal RESUME is low level.In simple terms, first suppose that position PG_FU_ENT<10:5> is programmed, therefore, signal FIVE ~ TEN is triggered to low level (comprising signal SIX and SEVEN), and the signal received by input 0 selected by multiplexer 1605 ~ 1617.Signal HIERB is triggered to low level, therefore, default value DTIME<19:0> selected by multiplexer 1603, through the process that multiplexer stacks, produces numerical value PG_TIME<19:0>.Numerical value <*4>:VSS0:PGT<15: 0> selected by multiplexer 1413, as initial value or the preset value of PG_TIME<19:0>.As mentioned above, in starting clock cycle, the low level (position except MSB) of control word PG_CNTRL<15:0> is initially become 1111000000000000b, and be inverted into PG<15:0>, its value is 0000111111111111b, therefore the value of PGT is 0000000000010000b.The initial period of the PG_CLK corresponding to the initial value of PGT is about the 80ns (multiplier 2 of clock cycle 0framework be set to any value by first group 3).Apprehensible, in different frameworks, clock value can be arbitrary value, and any different clock cycle can be selected as initial value.
When the control of constant current source lock, when control word PG_CNTRL<16:0> is reduced, cause corresponding PG<15:0> also to reduce thereupon.When the 11st position of PG<15:0> becomes 0,10th position of PG<15:0> is originally set to 1, therefore PG<15:0> becomes 0000000000100000b.Because PGT<15:0> is incorporated among <19:0>, in order to when power gating, adjustment PG_TIME<19:0>, therefore, DTIME<19:0> and PG_TIME<19:0> all can be adjusted.Due to the cycle selecting next larger, when therefore numerical value PGT<15:0> is increased to two doubling time of PG_CLK.Thus cause the cycle of PG_CLK to become twice, therefore each bottom of PG<15:0> become logical zero.When the cycle of PG_CLK increases, regulating the speed of control word slack-off (because having lower frequency).
As mentioned above, in order to adjust the cycle of PG_CLK, the critical voltage (as PG_VREF<1:N>) of definable any amount (0 or more).As shown in the figure, the critical voltage represented by PG_REF<1> is not enough close to the final voltage level represented by critical voltage PG_VREF<2>.When carrying out power gating, if when having reached larger critical voltage, HIER can become low level, and HIERB becomes high level.Therefore, the signal of input 1 selected by multiplexer 1603, i.e. the output signal of multiplexer 1601.If PG_FU_HIERB is low level (preset value), numerical value <*2>VSS0:PGT<15: 0>:<*2>VSS0 can be provided to multiplexer 1603, instead of numerical value DTIME<19:0>.The numerical value of the PGT<15:0> of this new numeric representation PG_TIME<19:0> need carry out twice moving to left, and namely the cycle of PG_CLK is multiplied by coefficient 4.When the control of constant current source lock, except normal single displacement, also need twice displacement that this is extra.
If when PG_FU_HIERB is triggered to high level, when HIERB becomes high level, multiplexer 1601 choosing coefficient <*3>VSS0:PGT<15: 0>:VSS0, in order to represent that one extra singlely to move to left, the cycle of PG_CLK is multiplied by coefficient 2 by it, instead of coefficient 4.Therefore, numerical value PG_FU_HIERB allows the cycle increasing slightly power gating.
Until reach final level, otherwise in the voltage lock control of local, in order to adjust PG_CLK, can only use single critical voltage value, but in other embodiments, the critical voltage PG_VREF<1:N> of other quantity can be used, in order to the critical voltage defined according to corresponding comparison signal CMP3 ~ CMPN, carry out the clock adjustment of any programmable number.When considering extra critical voltage and the adjustment of corresponding clock cycle, the multiplexer structure of Figure 16 A and Figure 16 B can be changed.
Clock shifter 1203 according to the setting numerical value of the numerical value of position PG<15:6> and position PG_FU_ENT<10:5>, the cycle of extra adjustment PG_CLK.The numerical value of position PG_FU_ENT<10:5> is in order at least one in trigger value FIVE ~ TEN, and each numerical value makes PG numerical value carry out corresponding displacement, in order to adjust the cycle of signal PG_CLK.In each embodiment, when the numerical value of position PG<15:0> arrives a corresponding numerical value, displacement can be carried out, in order to the cycle of PG_CLK is multiplied by two coefficients according to the numerical value of time numerical value contraposition PG<15:0>.For example, under power gating, and when signal RESUMEB is also triggered to high level, numerical value TEN is triggered to high level, therefore numerical value PG2T<18:0>:VDD0 selected by multiplexer 1605, instead of numerical value PG2T<19:0>.By numerical value PG2T<19:0> toward moving to left, and fill logical one (VDD0) in the rightmost side of numerical value PG2T<19:0>, in order to form numerical value PG2T<18:0>:VDD0.The operating principle of other numerical value of N INE, EIGHT, SEVEN, SIX and FIVE is also identical, is all after corresponding numerical value is triggered, and will be multiplied by two coefficients the clock cycle.As mentioned above, if the need arises, can the numerical value of activation in advance SIX and SEVEN.In the present embodiment, when power gating, according to the corresponding numerical value of control word PG_CNTRL, at least one in position PG_FU_ENT<15:0> activation numerical value FIVE ~ TEN, in order to adjust the cycle (and thus increasing the cycle) of signal PG_CLK.
As shown in Fig. 9 A and Fig. 9 B, under power gating operation, when signal HIGHB is triggered to high level, represent the voltage level having reached and retained data or state, therefore, action between summed values and values of disparity, makes voltage VDD1 maintain reservation voltage level.For the small variations of corresponding PG numerical value, control word PG_CNTRL also only can small variations.The cycle of signal PG_CLK remains unchanged or maintains between two numerical value.
When being disabled of signal PGATE1, signal RESUME can be triggered, in order to start recovery operation.Under recovery operation, apprehensible, the time length of replying from full power gating can be determined, and under the power gating of local, the poor situation (namely longer turnaround time) retaining level reply from state also can be determined.When recovery operation is initialised, under recovery operation, depend on the special value of programming numerical value and control word actual recovery time.If when PG_FU_CONST_RES_CLK is also triggered to high level, when signal RESUME is triggered, numerical value <*13>VDD0:PGTIMEBLEssT.LTssT. LT6:3>:<*3>VDD0 selected by multiplexer 1617, according to the numerical value programming PGTIMEB<6:3> of PG_FU_RES_PER<1:0>.Insert 13 logical ones from the left side of numerical value PGTIMEB<16:3>, and insert 3 logical ones on right side.As mentioned above, please refer to Figure 15, according to the numerical value of PG_FU_RES_PER<1:0>, position PGTIMEB<16:3> only has 1 position to be triggered to logical zero, equals a corresponding fixed cycle in order to make the cycle of PG_CLK.Apprehensible, multiplexer 1617 this numerical value anti-phase, makes corresponding logical one select the corresponding clock cycle.
If when the initial value of PG_FU_CONST_RES_CLK is logical zero, the output that multiplexer stacks will be selected.Because signal RESUMEB is low level, therefore the signal of the input 0 of each multiplexer 1603 ~ 1615 can be selected, value DTIME<19:0> is made to become PG_TIME<19:0>.As shown in figure 14, because signal RESUME is high level, therefore, under recovery operation, select numerical value <*14>VSS0:PGTLO:PGTLEssT.LTss T.LT6>:PGT<7>:P GT<8>:PGT<9Great T.GreaT.GT, PGTHI is Preset Time numerical value DTIME.In the present embodiment, decoder 1420 converts low level PGT<5:0> to single position PGTLO, and converts high-order PGT<15:10> to single position PGTHI.In another embodiment, numerical value PGTHI and PGTLO is inserted into time numerical value together with remaining bit PGT<9:6>.As long as 1 of position PGT<5:0> when being triggered, numerical value PGTLO is high level, and when only having 1 of PGT<15:10> in place to be triggered, numerical value PGTHI is high level.Therefore, when numerical value PGT<6>, PGT<7>, PGT<8>, PGT<9> and PGTHI are triggered to high level, a cycle just can be selected to PG_CLK.
In recovery operation, because the numerical value of the PGT in time numerical value can be inverted, therefore, the cycle of signal PG_CLK is a quite little numerical value at the beginning, in order to carry out frequency adjustment rapidly.Under recovery operation, a totalling adjustment numerical value selected by 2 input-multiplexers 915, and therefore, control word starts to increase gradually.Now, the cycle of signal PG_CLK increases gradually, in order to the rise time of control voltage VDD1.But a high position of PGT is merged into the numerical value PGTHI of single position, therefore, signal PG_CLK president time dimension is held in the shorter cycle, in order to increase voltage VDD1 rapidly.When voltage VDD1 arrives operating voltage level, the frequency of signal PG_CLK can reduce along with the increase of control word.In another embodiment, in fast multiple operation, when the rise time of voltage VDD1 is in a suitable scope, control word may increase significantly, in order to reduce the cycle of signal PG_CLK.A particular level is reached once control word PG_CNTRL<16:0>, such as position PG_CNTRL<13> or PG_CNTRL<14> depends on the setting of PG_FU_RESUME_STOP, highest significant position PG16 can be triggered, and control word PG_CNTRL<16:0> can get back to initial value, and the action of stop signal PG_CLK.
Scrutable, in another embodiment, the time that the time that voltage VDD1 is increased to normal operation level from data reservation level may be reduced to data reservation level than voltage VDD1 from normal operation level is also fast.But, need the increase of control voltage VDD1, in order to guarantee that voltage VDD0 can not be affected significantly, and then affect the service voltage of other kernel (or circuit) of microprocessor 100.In addition, the voltage of voltage VDD1 increase programmably can be adjusted according to ad hoc structure.
When PG_CKILL_CORE1 is triggered, during in order to start the operation of full power gating, signal KILL is toggled to high level by the inverter 1111 of Figure 11, make OR door group 1123 each of control word PG_CNTRL<16:0> is pulled to high level (therefore, control word PG_CNTRL<16:0> each being disabled or be not triggered).Therefore, PMOS transistor 502,504,506,508 and 601 all not conductings, in order to isolation voltage VDD1 and VDD0, and are pulled down to ground or VSS0 by voltage VDD1.PG<15:0> is initialized to 0000000001111111b (by gate 1115 and 1117), and therefore, the cycle of PG_CLK is an initial selection tune phase.When being disabled of PG_KILL_CORE1, by initialization PG and PGT numerical value, just RESUME can be triggered.When PG is initialised, just can under recovery operation, initialization control word PG_CNTRL<16:0>.If under recovery operation, during the clock cycle not having selection one fixing, when numerical value PGT is initialised, can by the frequency setting of PG_CLK at a high clock frequency, in order to quick recovery operation.In the present embodiment, when recovery operation, the cycle of recovered clock, according to framework, is fully programmed.Although full power gating can be enabled rapidly, the recruitment that lock control service voltage gets back to normal operation level must be controlled, to avoid affecting kernel around and circuit.
The cycle of PG_CLK is programmed according to many coefficients, in order under power gating or recovery operation, and the level change of control voltage VDD1.One coefficient is exactly control word itself.For example, numerical value PGT and PG_TIME<19:0> changes according to the change of position PGT.By fuse or scan mode ... etc., extra time shifting of programming.Another coefficient in order to control cycle is the level of voltage VDD1, as mentioned above, by triggering HIER, in order to represent higher critical voltage (as switched the input signal of multiplexer 1601).Utilize different implementations or framework, extra adjustment is carried out to the critical voltage of voltage VDD1.
Clock controller 706 produces signal PG_CLK.In the present embodiment, clock controller 706 produces multiple clock signal, and temporal decoder 712 generation time numerical value PG_TIME<19:0>, in order to select a clock signal.In another embodiment, clock controller 706 may be realized by a programmable clock generator, and time numerical value can in order to the cycle of Mbus signal.In other embodiments, time device or counter can be utilized ... etc. realize clock controller 706.
Under power gating or recovery operation, by the adjustment of many coefficient programming Control words, in order to the adjusting range of control voltage VDD1.One coefficient is exactly control word itself, can selected amount by one, Bit andits control word, just can control to adjust gain.
Above-described embodiment has presented according to programmable critical voltage, adjustment PG_CLK.Also programmable critical voltage can be utilized to carry out the adjustment of gain.As shown in figure 17, extra Gain tuning is carried out according to a critical voltage (as comparison signal CMP3).As shown in the 17th, the input of multiplexer 903 couples the output of multiplexer 1701 and 1703.As mentioned above, multiplexer 903,1701 and 1703 is the structure of 16, has 16 multiplexers separately.Multiplexer 903 selects the output signal of multiplexer 1701 or 1703 according to programming numerical value PG_FU_SUB_GN.Multiplexer 1701, according to comparison signal CMP3, selects shift value SHIFTVAL1 or SHIFTVAL2.Multiplexer 1703, according to comparison signal CMP3, selects shift value SHIFTVAL3 or SHIFTVAL4.Each shift value all has 16, and under power gating, represent the different displacement structure of control word, it is relative to different yield values.In the present embodiment, additionally can increase multiplexer newly, in order to the critical voltage according to any amount, utilize summed values and/or values of disparity to carry out Gain tuning.
There is the system and method for the digital power lock control of data recovery function for entirely able to programme, in order to the trigger condition according to current device, digitally control a lock control voltage, as a local service voltage, current device can be PMOS, nmos pass transistor ... etc., it is coupled between two voltages, and wherein a voltage is an integration service voltage.One microprocessor has power gating in various degree, therefore can adjust specific final voltage level statically or dynamically.In addition, circuit or kernel can be changed ... etc. ad hoc structure, as integrated ECC memory ... etc..Therefore, determine that the reference voltage of final level may be adjusted or select a different reference voltage.Actual final voltage level may be depend on ad hoc structure and operator scheme.There is the system and method intactly any applicable voltage level of generation able to programme of the digital power lock control of data recovery function.
The binary numeral of control word PG_CNTRL depends on many parameters, as processor, temperature and final voltage level.Actual voltage can be measured, and in a control loop, continuity or periodically add or deduct an adjustment numerical value, in order to adjust voltage.There is the system and method for the digital power lock control of data recovery function similar in appearance to an analog voltage adjuster, difference is that above-mentioned system and method system digitally controls, and be applied in the device of binary system dispersion, control binary device according to final voltage level.
Although the present invention with preferred embodiment openly as above; so itself and be not used to limit the present invention; without departing from the spirit and scope of the present invention, when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on accompanying those as defined in claim for those skilled in the art.

Claims (20)

1. an integrated circuit for digital power lock control, comprising:
Integrate supply bus;
Lock control supply bus;
Functional circuit, have a voltage supply input, this voltage supply input couples this lock control supply bus;
At least one programmable device, stores at least one programming Control parameter; And
Digital power brake system, comprising:
Multiple lock control device, each lock control device have current terminal to and control end, each current terminal to be coupled to this integration supply bus and this lock control supply between bus;
Power gating system, control figure controls numerical value, and wherein this digital control numerical value comprises multiple position, and each is provided at least one control end of described lock control device, in order to control a part for described lock control device; And
Wherein this power gating system is by this digital control numerical value of adjustment, in order under power gating operation, makes the voltage of this lock control supply bus relevant with the voltage that this integration supplies bus, and utilizes this this power gating of programming Control parameter adjustment to operate.
2. the integrated circuit of digital power lock control as claimed in claim 1, wherein this power gating system comprises a power gating device, under power gating, this power gating device is according to this programming Control parameter, one is selected, in order to reduce the voltage of this lock control supply bus from multiple difference gain values.
3. the integrated circuit of digital power lock control as claimed in claim 1, wherein this power gating system comprises power gating device, under power gating, this power gating device is according to this programming Control parameter, one is selected, in order to increase the voltage of this lock control supply bus from multiple totalling gain values.
4. the integrated circuit of digital power lock control as claimed in claim 1, wherein this power gating system comprises power gating device, under recovery operation, this power gating device is according to this programming Control parameter, one is selected, in order to increase the voltage of this lock control supply bus from multiple recovery gain values.
5. the integrated circuit of digital power lock control as claimed in claim 1, wherein this power gating system comprises a power gating device, this power gating device is according to this programming Control parameter, one is selected from multiple stopping numerical value, during in order to reach a selection stopping numerical value at this digital control numerical value, stop recovery operation.
6. the integrated circuit of digital power lock control as claimed in claim 1, wherein this power gating system comprises a clock controller, this clock controller provides a clock signal, a resize ratio of numerical value is controlled in order to control figure, and this clock controller is according to this programming Control parameter, change the cycle of this clock signal, in order to when the voltage of this lock control supply bus reaches at least one voltage level, change this resize ratio.
7. the integrated circuit of digital power lock control as claimed in claim 1, wherein this power gating system comprises a clock controller, this clock controller provides clock signal, the resize ratio of numerical value is controlled in order to control figure, and this clock controller changes the cycle of this clock signal, in order to when this digital control numerical value reaches at least one default value, change this resize ratio, this default value depends on this programming Control parameter.
8. the integrated circuit of digital power lock control as claimed in claim 1, wherein this power gating system comprises a clock controller, this clock controller provides clock signal, under recovery operation, this clock controller is according to this programming Control parameter, control the cycle of this clock signal, in order to increase the voltage of this lock control supply bus.
9. the integrated circuit of digital power lock control as claimed in claim 1, wherein this power gating system comprises:
Numeral adjuster, multiple continuous setup cycle each in, integrate numeral adjustment number and this digital control numerical value, supply the voltage of bus in order to change this lock control; And
Gain selection logic, utilizes this programming Control parameter, from multiple displacement result of this digital control numerical value, selects one as this numeral adjustment numerical value.
10. the integrated circuit of digital power lock control as claimed in claim 9, wherein this gain selection logic comprises:
Difference selects logic, under power gating, according to a difference gain values able to programme, from the described displacement result of this digital control numerical value, selects the first displacement result to adjust numerical value as selection differences; And
Add up and select logic, under power gating, according to totalling gain values able to programme, from the described displacement result of this digital control numerical value, select one second displacement result to select to add up adjustment numerical value as one.
The integrated circuit of 11. digital power lock controls as claimed in claim 9, wherein this gain selection logic comprises a recovery gain selection logic, under recovery operation, this recovery gain selection logic, according to recovery gain values able to programme, selects one to add up adjustment numerical value as selecting from the described displacement result of this digital control numerical value.
The integrated circuit of 12. digital power lock controls as claimed in claim 1, wherein this power gating system comprises:
Numeral adjuster, multiple continuous setup cycle each after, integrate numeral adjustment number and this digital control numerical value, supply the voltage of bus in order to change this lock control;
Clock generator, clocking, in order to control the described continuous setup cycle, wherein the cycle of this clock signal depends on time controling numerical value; And
Temporal decoder, according to this programming Control parameter, provides and adjusts this time controling numerical value.
The integrated circuit of 13. digital power lock controls as claimed in claim 12, wherein this temporal decoder comprises:
Transducer, converts this digital control numerical value to this time controling numerical value, and when this digital control numerical value is adjusted, adjusts this time controling numerical value; And
Clock period selection device, when the voltage of this lock control supply bus reaches at least one voltage level, this clock period selection device, according to this programming Control parameter, selects one from multiple displacement result of this time controling numerical value.
The integrated circuit of 14. digital power lock controls as claimed in claim 12, wherein when this digital control numerical value reaches each of multiple programming numerical value, this temporal decoder adjusts this time controling numerical value, and described programming numerical value depends on this programming Control parameter.
The integrated circuit of 15. digital power lock controls as claimed in claim 12, wherein this temporal decoder comprises:
Transducer, converts this digital control numerical value to this time controling numerical value, and when this digital control numerical value is adjusted, adjusts this time controling numerical value;
Clock shifter, according to this digital control numerical value and this programming Control parameter, provides at least one shift value; And
Clock period selection device, when this digital control numerical value reaches this shift value, this time controling numerical value of displacement.
The integrated circuit of 16. digital power lock controls as claimed in claim 12, wherein this time controling numerical value is maintained a fixed numbers by this temporal decoder, makes this clock signal have the fixed cycle.
The integrated circuit of 17. digital power lock controls as claimed in claim 16, wherein this temporal decoder is according to this programming Control parameter, from multiple fixed cycle numerical value, select one.
The integrated circuit of 18. digital power lock controls as claimed in claim 1, wherein this programmable device has fuse array, and this programming Control parameter is in order to this fuse array of programming.
The integrated circuit of 19. digital power lock controls as claimed in claim 1, wherein this programmable device comprises memory, and this programming Control parameter is in order to this memory of programming.
20. the integrated circuit of digital power lock control as claimed in claim 19, wherein in boundary scan, this memory of programming.
CN201410246672.0A 2013-06-05 2014-06-05 The integrated circuit of digital power lock control Active CN103986241B (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201361831544P 2013-06-05 2013-06-05
US61/831,544 2013-06-05
US201461930356P 2014-01-22 2014-01-22
US61/930,356 2014-01-22
US14/202,313 US9450580B2 (en) 2013-06-05 2014-03-10 Digital power gating with programmable control parameter
US14/202,313 2014-03-10

Publications (2)

Publication Number Publication Date
CN103986241A CN103986241A (en) 2014-08-13
CN103986241B true CN103986241B (en) 2016-03-30

Family

ID=51278107

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410246672.0A Active CN103986241B (en) 2013-06-05 2014-06-05 The integrated circuit of digital power lock control

Country Status (1)

Country Link
CN (1) CN103986241B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110729999B (en) * 2016-03-22 2024-04-09 华为技术有限公司 Mode control circuit and apparatus
US10296070B2 (en) * 2017-02-24 2019-05-21 Winbond Electronics Corporation Power-gating control and method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1214531C (en) * 1999-10-15 2005-08-10 威盛电子股份有限公司 Single-terminal input voltage level converter controlled by grid voltage
US7131092B2 (en) * 2004-12-21 2006-10-31 Via Technologies, Inc. Clock gating circuit
US7659746B2 (en) * 2005-02-14 2010-02-09 Qualcomm, Incorporated Distributed supply current switch circuits for enabling individual power domains
KR101316788B1 (en) * 2007-01-08 2013-10-11 삼성전자주식회사 Semiconductor integrated circuit device
WO2009144661A1 (en) * 2008-05-27 2009-12-03 Nxp B.V. Integrated circuit and integrated circuit control method
US8373493B2 (en) * 2010-09-15 2013-02-12 Duke University Power switch design and method for reducing leakage power in low-power integrated circuits
US8633751B2 (en) * 2011-11-10 2014-01-21 Advanced Micro Devices, Inc. Centralized power gating control for partitioned power gates

Also Published As

Publication number Publication date
CN103986241A (en) 2014-08-13

Similar Documents

Publication Publication Date Title
CN103984274B (en) Digital power gating integrated circuit and method
EP1759460B1 (en) Adaptive control of power supply for integrated circuits
US7181188B2 (en) Method and apparatus for entering a low power mode
US7930577B2 (en) Closed-loop control for performance tuning
US5473526A (en) System and method for power-efficient charging and discharging of a capacitive load from a single source
US20070200593A1 (en) Digital circuit with dynamic power and performance control via per-block selectable operating voltage
US9411714B2 (en) Finite state machine for system management
US10033362B1 (en) PVTM-based wide voltage range clock stretching circuit
US8699291B1 (en) Memory circuitry with dynamic power control
CN104037940B (en) The integrated circuit of digital power lock control and method
US6763471B1 (en) Single chip microcomputer with reduced channel leakage current during a stable low speed operation state
US7569899B2 (en) Semiconductor integrated circuit
CN103986241B (en) The integrated circuit of digital power lock control
JP2000207884A (en) Semiconductor integrated circuit device
CN103986242B (en) The integrated circuit of digital power lock control and method
EP1759250A1 (en) Control scheme for binary control of a performance parameter
EP0381241A2 (en) High speed output circuit suitable for wired-or structure
US10826467B1 (en) High-accuracy dual-mode free running oscillator
US20150022235A1 (en) Semiconductor device
US6853929B2 (en) Pipeline control for power management
TAKAHASHI et al. A 100 MIPS high speed and low power digital signal processor
KR20020080480A (en) Power management for digital processing apparatus
JP2001228220A (en) Test circuit of semiconductor device
TWI523425B (en) Integrated circuit and method with digital power gating
TASHIRO et al. A 100 MIPS High Speed and Low Power Digital Signal

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant