WO2009144661A1

WO2009144661A1 - Integrated circuit and integrated circuit control method

Info

Publication number: WO2009144661A1
Application number: PCT/IB2009/052198
Authority: WO
Inventors: Jose De Jesus Pineda De Gyvez; Rinze Ida Mechtildis Peter Meijer; Cas Groot
Original assignee: Nxp B.V.
Priority date: 2008-05-27
Filing date: 2009-05-26
Publication date: 2009-12-03

Abstract

The present application discloses an integrated circuit comprising a circuit portion (100) coupled between first and second power supply lines (110; 120); a first switch (115, 135) coupled between the first power supply line (110, 120) and the circuit portion (100) for disconnecting the circuit portion from the first power supply line during an inactive mode of the circuit portion; and an arrangement (315, 335, 410) for, during said inactive mode, providing the circuit portion (100) with a fraction of its active mode power supply at least when averaged over said inactive mode to prevent the circuit portion voltage to drop below a threshold value. The present application further discloses a method for controlling such an integrated circuit.

Description

Integrated circuit and integrated circuit control method

FIELD OF THE INVENTION

The present invention relates to an integrated circuit (IC) comprising a circuit portion coupled between first and second power supply lines and a first switch coupled between the first power supply line and the circuit portion for disconnecting the circuit portion from the first power supply line during an inactive mode of the circuit portion.

The present invention further relates to a method for controlling such an IC.

BACKGROUND OF THE INVENTION

Nowadays, many integrated circuits (ICs) are designed to perform a wide variety of computational tasks. To this end, such an IC may comprise a plurality of different circuit portions, e.g. cores, each designed to perform one of said computational tasks. An example of such a multi-tasking IC design is the system-on-chip concept. Usually, such ICs perform only a subset of the computational tasks at the same time, which means that the other circuit portions do not perform any tasks. To avoid unnecessary power consumption by such idle circuit portions, these circuit portions are placed in a low-power consuming mode until their functionality is required again.

There are several IC design principles available to bring the circuit portion in such a lower-power mode. One such principle consists of gating the circuit portion clock signal during the inactive mode, which ensures during the inactive period of the circuit portion, the peak power consumption of the circuit portion on the clock edges, which typically is caused by the activity of the sequential elements such as flip-flops and other data storage elements, is avoided. The clock gating approach only provides modest power savings because a substantial part of the power consumption of a circuit portion is caused by charge leakage through the substrate, which is not prevented by clock gating. An alternative approach is power gating, in which the circuit portion is disconnected from its power supply during its inactive mode. Fig. 1 shows an example of the power gating principle. A circuit portion 100 has internal power lines 130 and 140, i.e. a virtual ground and a virtual supply line. The virtual ground 130 is connected to a supply line 110 via a pMOS power switch 115 for gating the power supply line 110, e.g. Vdd, and the virtual supply line 140 is connected to a ground line 120 via an nMOS power switch 135 for gating the ground line 120, e.g. V_ss. An inverter chain 150 comprises a first inverter 152 for controlling the nMOS power switch 135 and a second inverter 154 for controlling the pMOS power switch 115. Power gating gives the best possible power saving because continuous charge leakage from the circuit portion to the substrate no longer occurs during the inactive period of the circuit portion. However, power gating can cause other problems. For instance, in case the overall capacitance of a circuit portion is substantial, a large amount of charge has to be restored in the circuit portion upon termination of its inactive mode. The demands this puts on the power supply of the IC can cause a drop in the supply voltage, thereby jeopardizing the correct functioning of other parts of the IC that rely on the same power supply. Also, it can take an undesirably long time to bring the circuit portion back to full power upon termination of the inactive mode. In addition, power gating typically causes the data storage elements of the circuit portion to lose their data values, which may be unwanted.

SUMMARY OF THE INVENTION

The present invention seeks to provide an IC according to the opening paragraph wherein at least some of these problems associated with power gating have been overcome. The present invention further seeks to provide a method for controlling such an IC.

According to a first aspect of the present invention, there is provided integrated circuit according to the opening paragraph, further comprising an arrangement for, during said inactive mode, providing the circuit portion with a fraction of its active mode power supply at least when averaged over said inactive mode to prevent the circuit portion voltage to drop below a threshold value. This has the advantage that a residual charge is kept in the circuit portion during its inactive mode, which reduces the amount of charge that needs to be restored to the circuit power upon its power-up. This has the further advantage that it obviates the need for state-retentive flip-flops in the circuit portion, e.g. a core of a SoC, thereby significantly reducing the complexity of the circuit portion.

In an embodiment, the arrangement comprises a controller arranged to control the first switch such that the circuit portion is periodically connected to the first power supply line for a predefined time period during said inactive mode. In such a burst mode, the charge leaking away from the circuit portion when disconnected from its power supply is periodically replenished, thus avoiding the need to charge the full capacitance of the circuit portion when terminating its inactive mode. The replenish period may be predefined.

Alternatively, the controller may be responsive to a comparator arranged to compare the circuit portion voltage with a reference voltage. This has the advantage that local process variations, which may affect the charge leakage rate of the circuit portion can be taken into consideration, whereas a predefined replenish period typically has to be based on a theoretically established worst case scenario.

In an alternative embodiment, the arrangement comprises a first further switch coupled between the first power supply line and the circuit portion, the first switch having a larger width-to length ratio than the first further switch, said first further switch being arranged to connect the circuit portion to the first power supply line at least during said inactive mode. This ensures that a small current still flows to the circuit portion in its inactive mode, said current feeding the leakage current from the circuit portion.

At this point, it is emphasized that the present invention is partially based on the realization that although full power gating provides a superior power saving that the arrangements of the present invention when applied over a prolonged period of time, in real- life scenarios, the circuit portions of an IC are frequently switched off for relatively short periods of time, during which the additional power saving of full power gating compared to the arrangements of the present invention are more modest, for which this benefit may not outweigh the aforementioned risk associated with a voltage drop across the power supply when powering up such a circuit portion.

Moreover, in case the circuit portion comprises a plurality of data storage elements, said threshold value is chosen such, e.g. at least twice the threshold voltage of the transistors forming the data storage elements, that the data storage elements retain their respective data values in said inactive mode. This cannot be guaranteed with full power gating.

In an embodiment, the first further switch is one of a plurality of substantially identical switches coupled in parallel between the first power supply line and the circuit portion, the integrated circuit further comprising a shift register for individually controlling the plurality of substantially identical switches. This has the advantage that process variations between the individual transistors, which can cause deviations from the intended voltage across the circuit portion, may be averaged out. Obviously, the width-to-length ratio of these transistors is chosen such that the selected transistors have a combined width-to-length ratio that is smaller than the first switch. Preferably, the IC further comprises a second switch coupled between the circuit portion and the second power supply line for disconnecting the circuit portion from the second power supply line during said inactive mode to prevent charge leaking from the circuit portion to ground during said inactive mode. The controller of the present invention may further be arranged to periodically enable the second switch during said inactive mode, and/or the IC may further comprise a second further switch coupled between the second power supply line and the circuit portion, wherein the second switch has a larger width-to length ratio than the second further switch arranged to connect the circuit portion to the second power supply line at least during said inactive mode. The IC of the present invention may be integrated into any suitable electronic device.

According to a further aspect of the present invention, there is provided a method of controlling an integrated circuit comprising a circuit portion coupled between first and second power supply lines, and a first switch coupled between the first power supply line and the circuit portion for disconnecting the circuit portion from the first power supply line during an inactive mode of the circuit portion, the method comprising disconnecting the circuit portion from the first power supply line at the start of its inactive mode by disabling the first switch; and during said inactive mode, providing the circuit portion with a fraction of its active mode power supply at least when averaged over said inactive mode to prevent the circuit portion voltage to drop below a threshold value.

The method of the present invention ensures that less charge needs to be replenished upon power-up of the circuit portion, and that any data storage element of the circuit portion retains its data value during the inactive mode.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention are described in more detail and by way of non- limiting examples with reference to the accompanying drawings, wherein Fig. 1 shows a part of a prior art IC;

Fig. 2 shows a typical inactive mode discharge cycle of a circuit portion of the prior art IC;

Fig. 3 shows a typical inactive mode discharge cycle of a circuit portion of an IC according to an embodiment of the present invention;

Fig. 4 shows a typical inactive mode discharge cycle of a circuit portion of an IC according to another embodiment of the present invention; Fig. 5 shows a typical inactive mode discharge cycle of a circuit portion of an IC according to yet another embodiment of the present invention;

Fig. 6 shows a comparison between prior art gating methods and the gating methods of the present invention; Fig. 7 shows another comparison between prior art gating methods and the gating methods of the present invention;

Fig. 8 shows a calculated correlation between the actual voltage of a circuit portion during its inactive mode and its wake-up time; and

Fig. 9 shows another embodiment of an IC of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

It should be understood that the Figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the Figures to indicate the same or similar parts. Fig. 2 shows the voltage transient 200 of the circuit portion 100 during a full power gating mode, in which both switches 115 and 135 are disabled such that the circuit portion 100 is disconnected from Vdd and ground, i.e. first power supply line 110 and second power supply line 120 respectively. The dynamic behavior of the circuit portion 100 is modeled by a capacitor 112 representing the aggregate capacitance of the various components of the circuit portion 100, with a current source 114 and a resistor 116 modeling the leakage current from the circuit portion 100. As can be seen from the transient, the active mode voltage across the circuit portion 100, which is about 1.2 V in this example, is reduced to OV in about 70 μs due to charge leakage from the circuit portion 100. Hence, after 70 μs, the total capacitance of the circuit portion 100 has been fully depleted. The time it takes to fully replenish capacitor 112 depends on the parameters of the circuit portion 100 as well as on the dimensions of the switches 115 and 135.

This prior art power gating method may be classified as static power gating because during the inactive mode, i.e. the sleep mode, of the circuit portion 100, the power gating does not involve any activity. In contrast, the present invention seeks to apply a dynamic power gating approach, in which, in contrast to a static power gating method, wake-up time, leakage reduction, and maximum voltage drop of the circuit portion 100 are treated as variables between which tradeoffs are chosen. For instance, the wake-up time can be a critical factor in deciding when to use dynamic power gating. This can for instance be applied when the required wake-up time for the circuit portion 100 when using full or static power gating is considered excessive. Also, there may be a desire to reduce the maximum voltage drop of the circuit portion 100 in sleep mode in order to avoid excessive currents being drawn when waking up the circuit portion 100. In an embodiment of the present invention, dynamic power gating techniques are combined with static power gating techniques.

In such a combined approach, four distinct power mode stages can be identified: Active mode: The circuit portion 100 is provided with a voltage V = Vdd-Vdr_Op in which Vdd is the supply voltage and Vdrop is the voltage drop over the gating switch 115. The circuit portion may be either processing a task or waiting to switch to the rise/fall mode.

Sleep mode: The supply voltage of the circuit portion 100 is terminated and the capacitance 112 of the circuit portion 100 is discharged or discharging. The circuit portion 100 is waiting to return to rise/ fall mode.

Rise/ fall mode: The circuit portion 100 is changing from sleep mode to active mode or visa versa. During this mode, the capacitance of the circuit portion 100 is charged or discharged respectively.

Dynamic sleep mode: The circuit portion 100 is provided with a dynamically regulated power supply such that the circuit portion 100 is never fully discharged. The circuit portion 100 may be charging or discharging, and is waiting to return to active mode.

The remainder of this description will focus on the dynamic sleep mode introduced by the present invention.

Fig. 3 shows a part of an IC in accordance with an embodiment of the present invention. A first further switch 315 is placed between the first power supply line 110 and the circuit portion 100 in parallel with the first switch 115. Preferably, a second further switch 315 is placed between the second power supply line 120 and the circuit portion 100 in parallel with the first switch 135. The first further switch 315 as well as the second further switch 335, if present, is arranged to connect the circuit portion 100 to the corresponding power supply lines 110, 120 at least during the inactive mode, i.e. sleep mode of the circuit portion 100.

The first further 315 and the optional second further switch 335 may be permanently enabled by connecting their control terminals to ground and Vdd respectively. In this case, the width-length ratios of the first transistor and the first further transistor are chosen such that during active mode, the combined width-length ratio complies with a required width-length ratio W/L of the power gating switch of the circuit portion 100. For instance, the width-length ratio of the first switch 115 may be chosen to be p*W/L and the width-length ratio of the first further switch 315 may be chosen to be (l-p)*W/L, with 0.5 < p <1. The same applies for the second switch 135 and the second further switch 335 when present.

As can be seen in Fig. 3, when the circuit portion 100 is in its inactive mode, during which switches 115 and 135 are disabled such that only switches 315 and 335 are enabled, the transient 300 of the circuit portion voltage reaches a steady state at an intermediate voltage between Vdd and ground. In this steady state, the current supplied by the further switches 315 and 335, which typically have a smaller width-length ratio than the switches 115 and 135, is in equilibrium with the leakage current from the circuit portion 100. The exact value of this intermediate voltage thus depends on the magnitude of the leakage current from the circuit portion 100 and the chosen width-length ratios of the further switches 315 and 335. The intermediate voltage may be set by varying p in the aforementioned width- length ratio equations.

In case the circuit portion 100 comprises data storage elements such as flip flops, the intermediate voltage preferably is set such that these data storage elements retain their data during the sleep mode of the circuit portion 100. Usually, this intermediate voltage should be at least two times the threshold voltage V_th of the transistors of these data storage elements.

It will be appreciated that the wake-up time of the circuit portion of Fig. 3 is reduced compared to a fully power gated circuit portion due to the fact that the capacitance 112 is not fully discharged. Fig. 4 shows a part of an IC in accordance with another embodiment of the present invention. A controller 410 is coupled to the control terminals of the first switch 115 and the second switch 135 (if present). The controller is typically arranged to provide the first switch 115 and the second switch 135 with an enable signal during the active mode of the circuit portion 100. In the sleep or inactive mode, the controller 410 provides the first switch 115 and the second switch 135 with a periodical enable signal such that the voltage across the circuit portion 100 is not allowed to drop below a certain threshold such as the threshold at which data storage elements may lose their data. Because it is common general knowledge to the skilled person how to generate a periodic signal, the controller 410 will not be described in more detail for reasons of brevity only. A controller 410 operated in accordance with an embodiment of the method of the present invention thus ensures that the switches 115 and 135 switch on periodically for a predefined amount of time. This small enable cycle charges the capacitance 112 of the circuit portion 100 to the supply voltage Vdd thereby preventing the circuit portion voltage to drop below its predefined threshold. It will be understood that the predefined threshold can be set by varying the enabling frequency, i.e. the number of enable cycles in the sleep period. This again reduces the wake-up time of the circuit portion 100 compared to a full power gating approach.

Transient 400 gives the voltage profile of the circuit portion 100 during such a burst-controlled sleep mode. In order to limit noise on the power supply lines, the rise time of these burst cycles can be kept relatively long since no timing performance is required during the sleep period. It is emphasized that the timing of the final burst cycle prior to waking up the circuit portion 100 is important since it determines the wake-up time required for the circuit portion 100. Preferably, this final burst cycle should be executed as shortly as possible before waking up the circuit portion 100.

Fig. 5 shows an embodiment of an IC of the present invention in which the embodiments shown in Fig. 3 and Fig. 4 have been combined. In this combined embodiment, the width-length ratios of further switches 315 and 335 may be smaller than in case of the embodiment shown in Fig. 3, because the periodic enabling of the switches 115 and 135 helps to prevent the core voltage to decrease below the intermediate threshold voltage level. Similarly, the switch frequency produced by the controller 410 may be reduced because the further switches 315 and 335 contribute to reducing the rate of the circuit portion voltage reduction. This may result in a voltage transient of the circuit portion 100 during sleep mode such as the transient 500. Fig. 6 shows the estimated energy consumption of the circuit portion 100 in sleep mode when applying the prior art clock gating method ('Energy Clock gating') and the prior art power gating method ('Energy Full discharge') with the dynamic gating embodiments of Fig. 3 ('Energy Intermediate'), Fig. 4 ('Energy Burst') and Fig. 5 ('Energy Combinatorial') as a function of the duration of the sleep mode in μs. The graph further shows the resulting voltages of the circuit portion 100 for three of these gating principles.

Fig. 7 shows the normalized estimated energy reduction for the prior art power gating method ('Full discharge method'), the method used in Fig. 3 ('Intermediate method'), the method used in Fig. 4 ('Burst method') and the method used in Fig. 5 ('Combinatorial method') relative to the energy consumed in the inactive mode of the circuit portion 100 when using clock gating only. From Figs. 6 and 7, it is immediately apparent that the full, i.e. static, gating approach in which the circuit portion 100 is fully discharged yields the most energy efficient solution. However, this approach can lead to excessive wake-up times and fails to retain data in the data storage elements of the circuit portion 100. When using the dynamic gating methods of the present invention, it can be seen that the method of Fig. 3, in which the small switches 315 and 335 are introduced, is most power-efficient, with power savings of up to 35% compared to clock gating whilst maintaining the state of the circuit portion 100.

When the periodic switching method of Fig. 4 and the combined approach of Fig. 5 are optimized in order to minimize energy consumption of the circuit portion 100 in sleep mode, these methods compare to the embodiment in which the small switches 315 and 335 are solely used. Such a minimization may be achieved by reducing the frequency of the enable cycles, combined with the increase of the rise time of each enable cycle to maintain the intermediate threshold voltage level of the circuit portion 100. The effect of maintaining a residual voltage across the circuit portion 100 during its sleep mode is demonstrated in Fig. 8, which shows the wake-up time (in seconds) of a circuit portion 100 with a known capacitance as a function of the maintained voltage across the circuit portion in its inactive mode. It is demonstrated that a significant reduction in wake-up time can be achieved when an intermediate circuit portion voltage is maintained during its sleep mode.

Now, upon returning to Fig. 3, it is pointed out that in this embodiment of the IC of the present invention, the intermediate voltage level of the core supply is very sensitive to process and temperature variations, which can significantly affect the small further switches 315 and 335 (if present). For instance, simulations in which these switches were simulated in different process corners of the wafer, the maximum difference in the intermediate voltage across the circuit portion 100 was found to be 17.5%, which is a substantial difference from the desired value.

This may be accounted for by assuming the worst case scenario, i.e. switches 315 and 335 being located in the process corners leading to the lowest intermediate voltage, and setting the width-length ratios of the small switches 315 and 335 accordingly. This of course has the drawback that if these switches are located in other process corners, the actual intermediate voltage will be higher than intended, thus reducing the amount of power saved in the sleep mode of the circuit portion 110. Similarly, when considering the effect of temperature variations on the conductive properties of the small switches 315 and 335, e.g. in a temperature range of O⁰C to 125⁰C, the intermediate voltage value of the circuit portion during its inactive mode can change by as much as 6% in 65nm CMOS technology. This again may be compensated for by dimensioning the small switches 315 and 335 accordingly, thereby obtained sub-optimal power reductions in case the IC operates at operating temperatures near the lower end of said temperature range.

Fig. 9 shows an alternative embodiment of Fig. 3, in which such problems have been overcome. The single small switches 315 and 335 with width-length ratio (1- p)*W/L each have been replaced by N substantially identical switches 915 and 935 with a width-length ratio (l-p)/N*W/L. The gates of these parallel switches are individually connected to a control block such as a shift register 920 and shift register 940 respectively. The switches are called substantially identical because they all have the same.

This allows for selecting subsets of the switches 915 and 935 in the inactive mode of the circuit portion by shifting appropriate control words into the shift registers 920 and 940. Using this proposed method provides the ability to program a user-defined threshold voltage when the circuit portion 100 is to enter its sleep mode. In the middle of the programmable intermediate voltage range, where typically about N/2 of the small switches 915 and/or 935 are enabled, the plurality of enabled switches may be chosen such that the different enabled switches are likely to be located in different process corners, which means that fluctuations in the respective threshold voltages of the individual switches 915 and/or 935 tend to average out. Consequently, the selected range of switches 915 and/or 935 provides enough swing during the different corners of process variation the meet the required threshold voltage. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. An integrated circuit comprising: a circuit portion (100) coupled between first and second power supply lines (HO; 120); a first switch (115, 135) coupled between the first power supply line (110, 120) and the circuit portion (100) for disconnecting the circuit portion from the first power supply line during an inactive mode of the circuit portion; and an arrangement (315, 335, 410) for, during said inactive mode, providing the circuit portion (100) with a fraction of its active mode power supply at least when averaged over said inactive mode to prevent the circuit portion voltage to drop below a threshold value.

2. An integrated circuit according to claim 1, wherein said arrangement comprises a controller (410) arranged to control the first switch (115, 135) such that the circuit portion (100) is periodically connected to the first power supply line (110, 120) for a predefined time period during said inactive mode.

3. An integrated circuit according to claim 2, wherein the controller (410) is responsive to a comparator arranged to compare the circuit portion voltage with a reference voltage.

4. An integrated circuit according to any of claims 1-3, wherein the arrangement comprises a first further switch (315, 335) coupled between the first power supply line (110, 120) and the circuit portion (100), the first switch (115, 135) having a larger width-to length ratio than the first further switch (315, 335), said first further switch (315, 335) being arranged to connect the circuit portion (100) to the first power supply line (110, 120) at least during said inactive mode.

5. An integrated circuit according to claim 4, wherein the first further switch is one of a plurality of substantially identical switches (915, 935) coupled in parallel between the first power supply line (110, 120) and the circuit portion (100), the integrated circuit further comprising a shift register (920, 940) for individually controlling the plurality of substantially identical switches (915, 935).

6. An integrated circuit according to any of the preceding claims, wherein the circuit portion (100) comprises a plurality of data storage elements, and wherein said threshold value is chosen such that the data storage elements retain their respective data values in said inactive mode.

7. An integrated circuit according to claim 6, wherein the threshold value is at least twice the threshold voltage of the transistors forming said data storage elements.

8. An integrated circuit according to any of the preceding claims, further comprising a second switch (135) coupled between the circuit portion (100) and the second power supply line (120) for disconnecting the circuit portion (100) from the second power supply line (120) during said inactive mode.

9. An integrated circuit according to claim 8, wherein the controller (410) is further arranged to periodically enable the second switch (135) during said inactive mode.

10. An integrated circuit according to claim 8 or 9, further comprising a second further switch (335) coupled between the second power supply line (120) and the circuit portion (100), the second switch (135) having a larger width-to length ratio than the second further switch (335), said second further switch (335) being arranged to connect the circuit portion (100) to the second power supply line (120) at least during said inactive mode.

11. An electronic device comprising an integrated circuit according to any of claims 1-10.

12. A method of controlling an integrated circuit comprising a circuit portion (100) coupled between first and second power supply lines (110; 120) and a first switch (115, 135) coupled between the first power supply line (110, 120) and the circuit portion (100) for disconnecting the circuit portion (100) from the first power supply line (110, 120) during an inactive mode of the circuit portion, the method comprising: disconnecting the circuit portion (100) from the first power supply line (110, 120) at the start of its inactive mode by disabling the first switch (115, 135); and during said inactive mode, providing the circuit portion (100) with a fraction of its active mode power supply at least when averaged over said inactive mode to prevent the circuit portion voltage to drop below a threshold value.

13. A method according to claim 12, wherein said providing step comprises periodically connecting to the first power supply line (110, 120) for a predefined time period during said inactive mode by periodically enabling the first switch (115, 135).

14. A method according to claim 12, wherein said providing step comprises providing a first further switch (315, 335) coupled between the first power supply line (110, 120) and the circuit portion (100), the first switch (115, 135) having a larger width-to length ratio than the first further switch (315, 335), and enabling first further switch (315, 335) at least during said inactive mode.

15. A method according to any of claims 12-14, wherein the circuit portion (100) comprises a plurality of data storage elements, and wherein the step of providing the circuit portion (100) with a fraction of its active mode power supply comprises ensuring that the circuit portion voltage does not drop to a value at which the data storage elements lose their stored data values.