JP2009105699A - Semiconductor integrated circuit, and method of starting the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent useless power consumption by keeping a power supply switch transistor in an off-state just after starting the transistor. <P>SOLUTION: The semiconductor integrated circuit has a circuit part (circuit block B(BLK_B), etc.), power supply switch transistors SW1 and SW2, and a control part (off start switch control part 2). The off-start switch control part 2 starts an activation operation in a conduction inhibition state (clear signal (CL): "0") of the power supply switch transistors SW1 and SW2 when a set signal (OSM_SET) of an off-start mode input from the outside is active ("1"). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit in which a path of a power supply current that flows when a power supply voltage is supplied to a circuit can be controlled by a power supply switch transistor having a threshold voltage higher than that of the transistor in the circuit, and a starting method thereof .

A technique of using a power switch transistor to cut off a power source current path of a circuit including a transistor having a threshold voltage lower than that of the power switch transistor is known as a so-called MTCMOS (Multi-threshold Complementary Metal Oxide Semiconductor).
It is necessary to lower the threshold voltage of a transistor such as a logic circuit so that signal delay does not occur accompanying power supply voltage reduction or element miniaturization. In MTCMOS technology, leakage current increases when the threshold voltage of a transistor is lowered. Therefore, for a circuit in a stopped state, the leakage current path is blocked by a power switch transistor having a larger threshold voltage to prevent waste of power consumption. It is.

In the application of the MTCMOS technology to a circuit, an internal voltage line provided in the circuit, which is called a so-called virtual VDD line or virtual GND line, is provided. The internal voltage line has a power switch transistor for shutting off and releasing the power supply for the global real power line (real VDD line) and real reference voltage line (real VSS line) that connect the blocks outside the circuit. Connected through.
There are three places where the power switch transistor is provided, between the functional circuit that is repeatedly activated and stopped and the actual VDD line, and between the functional circuit and the actual VSS line. A PMOS transistor is used on the side, and an NMOS transistor is used on the VSS line side.

For example, Patent Document 1 discloses a configuration in which an NMOS transistor is provided on the VSS line side and power is shut off.
Patent Document 1 relates to control of a flip-flop circuit for holding data in a logic circuit to which MTCMOS technology is applied. In Patent Document 1, when a power-on reset circuit that monitors a power supply voltage value at initial power-up, that is, at startup, detects that the power supply voltage has reached an appropriate value, the power supply voltage A configuration for resetting the flip-flop circuit for holding the data in response to the optimization of the above is disclosed.
JP 2005-218099 A

In the configuration disclosed in Patent Document 1, the first control signal SC for controlling the power switch transistor is initialized to a high level in response to the power-on reset circuit detecting the appropriate power supply voltage at the time of startup. Since the control is taken, when the power supply voltage optimization is detected, the power switch transistor is turned on.
On the other hand, Patent Document 1 does not describe the state of the power switch transistor after the startup until the detection of the optimization of the power supply voltage. Since the power supply switch transistor is turned on in response to the appropriateness of the power supply voltage, it is assumed that it has been turned off until then.

  However, in reality, the power supply switch transistor is not necessarily turned off in the process of gradually increasing the power supply voltage value from the start of the start, and if no measures are taken, the power supply switch transistor is turned on when the power supply voltage increases to some extent. May turn on. In this case, useless power is consumed at the time of start-up, and this makes the power consumption reduction that is an effect of applying the MTCMOS technology insufficient.

  As described above, in the field of semiconductor integrated circuits to which the MTCMOS technology is applied, no proposal has been made to realize a function of keeping the power switch transistor in the OFF state immediately after startup.

A semiconductor integrated circuit according to one embodiment of the present invention is provided in a circuit portion that operates by receiving supply of a power supply voltage and a path of a power supply current that flows when the power supply voltage is supplied to the circuit portion. A power switch transistor having a threshold voltage higher than that of the transistor and a control unit are provided on the same semiconductor substrate.
When the setting signal of the off-start mode input from the outside is active at the start-up, the control unit starts the start-up operation with the power switch transistor being in a conduction-inhibited state, and when the setting signal is inactive at the start-up Starts the start-up operation without inhibiting conduction of the power switch transistor.

  Preferably, in the above aspect of the present invention, the control unit includes a switch control circuit that generates a control signal for controlling conduction and non-conduction of the power switch transistor, and a predetermined activation process is completed after the activation operation is started. In response, a reset circuit that deactivates the reset signal in the off-start mode, and is provided between the switch control circuit and the control node of the power switch transistor, and when the setting signal is active at startup Is activated in the continuity prohibition state, and after the activation, the control signal from the activated switch control circuit can be passed by releasing the continuity prohibition state in response to the inactivation of the reset signal. And a regulation circuit for

In the configuration including the reset circuit and the regulation circuit, it is more preferable to further include a power supply stabilization detection unit that detects stabilization of the power supply voltage as the predetermined activation process, and the reset circuit includes the power supply stabilization. In response to the stabilization of the power supply voltage detected by the detection unit, a signal that becomes active when a delay time that can be set and changed by the user has elapsed from the stabilization, and activated by stabilization of the power supply voltage And a circuit that activates the output reset signal when both of the input signals become active.
Alternatively, preferably, an internal power supply voltage generating section that generates a substrate bias internal power supply voltage applied to the transistor in the circuit section, a power supply voltage stabilization detecting section that detects stabilization of the power supply voltage, and the internal power supply voltage An internal power supply stabilization detection unit that detects the stabilization of the clock signal, a clock signal generation unit that generates a clock signal, and a substrate bias control unit that starts initialization upon input of the clock signal, In response to the completion of all of the power supply voltage stabilization detection, the generation and stabilization detection of the internal power supply voltage, the generation of the clock signal, and the initialization of the substrate bias controller The reset circuit activates the reset signal.

  In the configuration including the reset circuit and the regulation circuit described above, more preferably, the regulation circuit includes a flip-flop circuit provided between the switch control circuit and a control node of the power switch transistor, and the setting signal. When the reset signal is input, and both the setting signal and the reset signal are active, the output of the flop flop is fixed to a logic that disables the power switch transistor and the setting signal is inactive. When the reset signal is active, the output of the flip-flop circuit is fixed to the logic opposite to the logic, and in other combinations of input logic, the logic according to the control signal is used as the output of the flip-flop circuit. A clear signal and a preset signal that are allowed to appear are generated, and the generated clear signal and preset signal are generated. Including a logic circuit for outputting a preparative signal to the control input of the flip-flop circuit.

According to the above configuration, the control unit determines whether or not to set the conduction prohibition state of the power switch transistor according to the logic (active or inactive) of the off-start mode setting signal input from the outside, Start in state.
Specifically, when the setting signal is active at the time of activation, the activation operation is started with the conduction of the power switch transistor prohibited. On the other hand, when the setting signal is inactive, the starting operation is started without prohibiting conduction of the power switch transistor.

  In the configuration including the reset circuit and the regulation circuit, the reset circuit activates the reset signal in the off-start mode in response to the completion of the predetermined startup process after the startup operation is started. The “predetermined start-up operation” that triggers activation of the reset signal is arbitrary, but may be, for example, detection of stabilization of the power supply voltage as the first process. The power supply voltage may be input externally or generated internally. In addition to power supply voltage stabilization, for example, generation of internal power supply voltage and detection of stabilization, and generation processing of a clock signal may be included. When the substrate bias control is performed, the substrate bias control unit may be initialized.

When the setting signal is active at the time of activation, the regulation circuit is activated in a state where the power switch transistor is not conductive. Then, after the activation, the regulation circuit cancels the conduction prohibited state in response to the activation of the reset signal. For example, when a switch control circuit that generates a control signal that controls conduction and non-conduction of the power switch transistor is activated after the conduction prohibited state is released, the control signal from the activated switch control circuit can pass through the regulation circuit It becomes. Alternatively, when the switch activation circuit is activated but the regulation circuit is in a conduction-inhibited state, and the control of the power switch transistor through the regulation circuit is impossible, the control signal from the switch control circuit is simultaneously released. It can pass through the restriction circuit (control permission).
The regulation circuit having the above functions is realized by a flip-flop circuit and a logic circuit that changes the combination of the logic state of the clear signal and preset signal given to the flip-flop circuit according to the input logic state of the setting signal and the reset signal. it can.

  In a method for starting a semiconductor integrated circuit according to one embodiment of the present invention, a path of a power supply current that flows when a power supply voltage is supplied to a circuit can be controlled by a power supply switch transistor having a threshold voltage higher than that of the transistor in the circuit. A method for starting a semiconductor integrated circuit, comprising: applying an off-start mode setting signal to the semiconductor integrated circuit; starting the semiconductor integrated circuit in a state where the setting signal is applied; and Validating voltage input or internally generating the power supply voltage, and when the setting signal is active at the start of startup, the power switch transistor is in a conduction prohibited state, and when inactive, the conduction prohibited In response to the completion of the predetermined start-up process started upon receiving the supply of the power supply voltage. A step of deactivating the reset signal in the off-start mode, and a step of releasing the conduction prohibited state in response to the inactivation of the reset signal when the conduction is prohibited after the start of the activation. And including.

  According to the present invention, prohibition of conduction of the power switch transistor at the time of start-up can be controlled by a logic state of an off-start mode setting signal input from the outside. Therefore, it is possible to effectively prevent the control transistor from being turned on in the process where the power supply voltage is optimized or stabilized, thereby obtaining a benefit that unnecessary power consumption can be eliminated.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention.
In the semiconductor integrated circuit illustrated in FIG. 1, reference numeral 1A represents a chip area for arranging a functional circuit and a control circuit. Although not particularly illustrated, a plurality of input / output cells are respectively provided along four sides of the rectangular semiconductor chip on which the semiconductor integrated circuit is formed, in a frame-like portion along the outer periphery of the semiconductor chip located around the chip area 1A. Arranged in rows.

Several circuit blocks are arranged in a chip area 1A for circuit arrangement surrounded by four sides of input / output cells. In FIG. 1, blocks whose edges are indicated by diagonal lines are formed in MTCMOS non-application areas called “current-carrying areas”, and blocks whose edges are not indicated by diagonal lines are formed in MTCMOS application areas. Yes.
A circuit block A (BLK_A) and a circuit block B (BLK_B) are arranged in the MTCMOS application region.

The circuit block A (BLK_A) is a functional circuit block to which a substrate bias technique called VTCMOS (Variable Threshold Complementary Metal Oxide Semiconductor) is applied in addition to MTCMOS.
The circuit block B (BLK_B) is a functional circuit block to which the MTCMOS technology is applied but the VTCMOS technology is not applied.

Easy access from both the circuit block A (BLK_A) and the circuit block B (BLK_B), for example, the substantially central portion of the chip area 1A is a current-carrying region, and MTCMOS is not applied to the current-carrying region. Is always provided with a circuit block C (BLK_C) that operates by receiving supply of power supply voltage.
The circuit block C (BLK_C) includes, for example, a storage circuit such as a register or a memory that needs to be energized constantly after activation. Further, a CPU or a control system circuit such as a DSP that performs overall control may be included in the circuit block C (BLK_C). However, in FIG. 1, it is assumed that the circuit block C (BLK_C) is a non-control system circuit.

Other energization regions include a VTCMOS control unit (VTCMOS.CONT.) 2A, an MTCMOS control unit (MTCMOS.CONT.) 2B, a PLL (Phase-locked Loop) unit 5 as a “clock signal generation unit”, and “internal A VTCMOS voltage regulator (VTCMOS.V-REG.) 6V serving as a “power supply voltage generator” is disposed.
The VTCMOS control unit 2A is a circuit that has a function of executing a predetermined program sequence similar to a so-called CPU, and controls that the VTCMOS voltage regulator 6V generates a VTCMOS substrate bias voltage according to the program sequence.
The MTCMOS control unit 2B has a function of executing a predetermined program sequence similar to a so-called CPU, and is a circuit that is controlled by a CPU (not shown), for example, and performs power supply control of the MTCMOS according to the program sequence. The MTCMOS control unit 2B constitutes a “control unit” that executes start-up control according to an off-start mode to be described later.

The PLL unit 5 is a circuit that is activated by a command from the VTCMOS control unit 2A or the MTCMOS control unit 2B and generates the clock signal CLK so that the oscillation frequency can be changed.
The VTCMOS voltage regulator 6V is a circuit that generates a substrate bias voltage under the control of the VTCMOS control unit 2A and applies the voltage value to a substrate region (well) such as a logic transistor of the circuit block A (BLK_A) in a changeable manner. .

A main voltage regulator (MVV-REG.) 6M, a control voltage regulator (CV-REG.) 6C, and a PLL voltage regulator (PLL.V-REG.) 6P are provided outside the chip area 1A. Yes.
Here, it is assumed that the main voltage regulator 6M, the control voltage regulator 6C, and the PLL voltage regulator 6P are mounted on the same printed circuit board as the semiconductor integrated circuit. However, all or part of the main voltage regulator 6M, the control voltage regulator 6C, and the PLL voltage regulator 6P may be formed in the semiconductor integrated circuit.

The main voltage regulator 6M is a voltage generation circuit that supplies a power supply voltage to the PLL drive voltage circuit blocks A (BLK_A) to C (BLK_C).
The control voltage regulator 6C is a voltage generation circuit that generates a voltage that is a source of the substrate bias voltage generated by the VTCMOS voltage regulator 6V. This voltage is also used as a power supply voltage for the VTCMOS control unit 2A and the MTCMOS control unit 2B.
The VTCMOS voltage regulator 6V that generates the substrate bias voltage is preferably formed in the semiconductor integrated circuit. The reason is that a fine voltage adjustment is quickly performed on the well of the circuit block A (BLK_A).

The MTCMOS control unit 2B includes a switch control unit (hereinafter referred to as off-start / switch control unit) 2 having a function of performing start-up control according to the off-start mode. The off-start switch control unit 2 is a circuit that plays a central role in the “control unit” of the present invention.
In addition, a power-on reset (POR: Power On Reset) circuit 4 (hereinafter referred to as POR) as a “power stabilization detector” is applied to the circuit block A (BLK_A) and the circuit block B (BLK_B) to which the MTCMOS technology is applied. Circuit). The POR circuit 4 is a circuit that detects from the value of the power supply voltage VDDm that the power supply voltage VDDm supplied from the main voltage regulator 6M is stabilized.
The MTCMOS control unit 2B is also provided with a POR circuit 4c as a similar circuit for detecting stabilization of the power supply voltage VDDc input from the control voltage regulator 6C.

Next, an outline of the MTCMOS technology will be described.
FIG. 2 shows connections between a circuit block to which MTCMOS is applied and a control unit (switch control unit) for MTCMOS operation in three modes.
Circuit blocks 10A, 10B, and 10C to which MTCMOS is applied in the three modes shown in FIGS. 2A to 2C are circuits corresponding to circuit block A (BLK_A) or circuit block B (BLK_B) in FIG. A part of the block is shown.
The circuit blocks 10 </ b> A, 10 </ b> B, and 10 </ b> C are usually configured to include a plurality of logic (circuit) cells 11. In each figure, only one logic cell 11 is shown for simplicity.
Transistors (not shown) constituting the logic cell 11 are miniaturized and the operating voltage is reduced. To eliminate the influence of the operation delay due to the miniaturization and voltage reduction, it is necessary to reduce the threshold voltage of the transistors. is there. For this reason, the off-leakage current increases while the fine transistor is off. The MTCMOS technology is a technology applied for suppressing an increase in power consumption due to an off-leakage current and stabilizing the operation. By providing one or more power switch transistors for each of the circuit blocks 10A, 10B, and 10C, the off-leakage current is provided. Shut off.

  The power switch transistor shown in FIG. 2A is provided in the circuit block 10A, and a low-level internal voltage line 22 (L) called a so-called virtual VSS line and a reference voltage supply line constituting the so-called VSS line. 21 is an NMOS switch SW (L) having an NMOS (N channel Metal Oxide Semiconductor) configuration connected between the two. The NMOS switch SW (L) has a threshold voltage sufficiently higher than that of the NMOS logic transistor constituting the logic cell 11, and is turned off when the operation of the circuit block 10A is stopped. Stop power consumption.

In FIG. 2A, the logic cell 11 is connected between the internal voltage line 22 (L) and the main power supply voltage supply line 23M that supplies the power supply voltage VDDm generated by the main voltage regulator 6M of FIG. Yes.
In FIG. 2A, a switch control unit (SW.CONT.) 20A is arranged outside the circuit block 10A, specifically, in the off-start switch control unit 2 of FIG.
The switch control circuit 20A is driven by the power supply voltage VDDc generated by the control voltage regulator 6C in FIG. 1 and supplied from the control power supply voltage supply line 23C with reference to the voltage applied to the reference voltage supply line 21. Unlike the circuit block 10A, the power supply voltage is always supplied while the operation of the entire semiconductor integrated circuit is permitted. The gate of the NMOS switch SW (L) is connected to the switch control circuit 20A. The NMOS switch SW (L) is turned off by the switch control circuit 20A when the operation of the circuit block 10A is stopped and turned on when the operation is restored. The on / off timing of the NMOS switch SW (L) is determined by an operation sequence defined by a program executed by the MTCMOS control unit 2B of FIG. 1, and is repeatedly turned on and off during startup of the semiconductor integrated circuit. It is.

The power switch transistor shown in FIG. 2B is provided in the circuit block 10B and has a high level internal voltage line 22 (H) called a so-called virtual VDD line and a main power supply voltage supply line for supplying the power supply voltage VDDm. This is a PMOS switch SW (H) having a PMOS (P channel Metal Oxide Semiconductor) configuration connected between the terminals 23M and 23M. The threshold voltage of the PMOS switch SW (H) is sufficiently larger than that of the PMOS logic transistor constituting the logic cell 11, and therefore, the PMOS switch SW (H) is turned off when the operation of the circuit block 10B is stopped. Stop power consumption.
Similar to the switch control circuit 20A shown in FIG. 2A, the switch control unit (SW.CONT.) 20B that constantly receives the supply of the power supply voltage VDDc is connected to the outside of the circuit block 10B as shown in FIG. Specifically, it is arranged in the MTCMOS control unit 2B of FIG. The gate of the PMOS switch SW (H) is connected to the switch control unit 20B. The PMOS switch SW (H) is turned off by the switch control unit 20B when the operation of the circuit block 10B is stopped and turned on when the operation is restored. The on / off timing of the PMOS switch SW (H) is determined by an operation sequence defined by a program executed by the MTCMOS control unit 2B in FIG. 1, and the on / off is alternately repeated during startup of the semiconductor integrated circuit. It is.

The power switch transistor shown in FIG. 2C includes both the NMOS switch SW (L) shown in FIG. 2A and the PMOS switch SW (H) shown in FIG. The NMOS switch SW (L) and the PMOS switch SW (H) are both turned off when the circuit block 10C is stopped, thereby preventing power consumption of the logic cell 11.
The switch control unit (SW.CONT.) 20C shown in FIG. 2 (C) has both the functions of the switch control circuit 20A shown in FIG. 2 (A) and the switch control unit 20B shown in FIG. 2 (B). The control power supply voltage supply line 23C and the reference voltage supply line 21 are connected to each other, and the power supply voltage VDD is always supplied during operation of the semiconductor integrated circuit.

In FIG. 2A, if the operation stop time is long, the voltage of the internal voltage line 22 (L) due to the off-leakage current of the logic cell 11 (voltage difference from the voltage of the reference voltage supply line 21 (for example, 0 [V])). Rises. For this reason, when the switch control circuit 20A turns on the NMOS switch SW (L) at the time of the next operation return, the voltage of the internal voltage line 22 (L) decreases.
On the contrary, in FIG. 2B, the internal voltage line 22 (H) close to the power supply voltage VDD immediately before the operation stop is discharged by the off-leakage current of the logic cell 11 during the operation stop period. The voltage of the voltage line 22 (H) falls below the power supply voltage VDD. For this reason, when the switch control unit 20B turns on the PMOS switch SW (H) at the time of the next operation return, the voltage of the detection target voltage VL2 (H) increases.
In FIG. 2C, the internal voltage line 22 (H) on the high level side and the internal voltage line 22 (L) on the low level side approach the potential due to the off-leak current of the logic cell 11 while the operation is stopped. . Therefore, when the switch control unit 20C simultaneously turns on the PMOS switch SW (H) and the NMOS switch SW (L) at the time of the next operation return, the voltage drop of the internal voltage line 22 (L) shown in FIG. The voltage rise of the internal voltage line 22 (H) shown in FIG.

Next, a specific circuit configuration example of the off-start switch control unit 2 will be described by taking the case of FIG. 2A as an example.
FIG. 3A is a circuit diagram showing in more detail including control circuits other than the switch control circuit 20A of FIG.
As shown in FIG. 3A, in the off-start switch control unit 2, in addition to the switch control circuit 20A, a clear signal (CL) and a preset signal as control signals for the flip-flop circuit FF and the flip-flop circuit FF. FF control logic circuit (FF.CONT.) 24 as a “logic circuit” for generating (PR). The flip-flop circuit FF and the FF control logic circuit 24 constitute a “regulator circuit”.
Further, a reset circuit (RST.C.) 25 is disposed in the off-start switch control unit 2.

  The output of the switch control circuit 20A is connected to the data input terminal of the flip-flop circuit FF so that the control signal CS generated in the switch control circuit 20A can be output.

On the other hand, the POR circuits 4 and 4C as the “voltage stabilization detection unit” shown in FIG. 1 can input a low active POR detection signal (POR_X) indicating the result of voltage stabilization detection. It is connected. Hereinafter, “low active” signals including the POR detection signal (POR_X) are indicated by adding “_X” to the end of a symbol representing the signal name.
A system reset signal (SysRST_X) that allows the user to specify and change the reset delay time can be input to the reset circuit 25.

FIG. 4 shows an example of the reset circuit 25.
The illustrated reset circuit 25 includes an AND circuit AND1 having a negative logic input and an AND circuit AND2 having a positive logic input. The system reset signal (SysRST_X) can be input to one input of the AND circuit AND1, and the power-on reset signal (POR_X) from the POR circuit 4 can be input to the other input. The output of the AND circuit AND1 is connected to one input of the AND circuit AND2. The power-on reset signal (PORc_X) from the POR circuit 4c in the MTCMOS control unit 2B can be input to the other input of the AND circuit AND2. A low active reset signal (RST_X) can be output from the output of the AND circuit AND2.
As shown in the figure, the power-on reset signals (POR_X) and (PORc_X) detect that the power supply voltage VDDm or VDDc to be detected has reached a certain level and are low active signals, that is, the POR detection signal (POR_X). Alternatively, it is a circuit that outputs (PORc_X).

Returning to FIG. 3, the reset signal (RST_X) from the reset circuit 25 can be applied to one input of the FF control logic circuit 24. Further, an off-start mode (OSM) setting signal (OSM_SET) inputted from the outside of the semiconductor integrated circuit can be applied to the other input of the FF control logic circuit 24.
The OSM setting signal (OSM_SET) is a signal that is always generated outside the semiconductor integrated circuit, for example, on a mounting board, regardless of whether the semiconductor integrated circuit is started or stopped. When the OSM setting signal (OSM_SET) is “H” or “1” indicating activity, it means setting of the off-start mode, and when “L” or “0” indicating inactivity, it means releasing the off-start mode. . Here, the “off start mode” is a start mode in which the MTCMOS power switch transistor SW is prohibited from conduction when the semiconductor integrated circuit is started. Therefore, “off start mode release” means to release the conduction prohibited state of the power switch transistor SW.

The FF control logic circuit 24 supplies the clear signal (CL) to be supplied to the clear terminal of the flip-flop circuit FF and the preset terminal of the flip-flop circuit FF from the input reset signal (RST_X) and the OSM setting signal (OSM_SET). This circuit generates a preset signal (PR).
Note that the clear terminal and the preset terminal are negative logic inputs. This is because the system reset signal (SysRST_X), the POR detection signal (POR_X), and the reset signal (RST_X) shown in FIG. Corresponding to something. Therefore, if these signals are high active signals, the control input of the flip-flop circuit FF may be positive logic.

The data output terminal of the flip-flop circuit FF is connected to the gates of the power switch transistors SW1 and SW2 in the circuit block B (BLK_B) or the circuit block A (BLK_A). Hereinafter, this gate connection node is referred to as a control node NDc.
The power switch transistors SW1 and SW2 are connected between the internal voltage line 22 (L) and the reference voltage supply line 21 as in FIG. The logic cell 11 is connected between the internal voltage line 22 (L) and the main power supply voltage supply line 23M.
On the other hand, the entire MTCMOS control unit 2B (see FIG. 1) including the off-start switch control unit 2 is connected between the control power supply voltage supply line 23C and the reference voltage supply line 21.

FIG. 3B is a chart showing the input / output relationship of the FF control logic circuit 24.
When the clear signal (CL) is “0”, the flip-flop circuit FF sets the control node NDc to the “L” level where the N-channel power switch transistors SW1 and SW2 are prohibited from conducting. Set FF output to “0”. The input of the FF control logic circuit 24 in this state is when the OSM setting signal (OSM_SET) is “1” (active) and the reset signal (RST_X) is “0” (active).
On the other hand, when the preset signal (PR) is “0”, the flip-flop circuit FF sets the control node NDc to “H” level forcibly turning on the power switch transistors SW1 and SW2. Is set to “1”. The input of the FF control logic circuit 24 in this state is when the OSM setting signal (OSM_SET) is “0” (inactive) and the reset signal (RST_X) is “0” (active).

  Other combinations of input logic, that is, when the OSM setting signal (OSM_SET) is “0” (inactive) and the reset signal (RST_X) is “1” (inactive), and the OSM setting signal (OSM_SET) is When “1” (active) and the reset signal (RST_X) are “1” (inactive), both the clear signal (CL) and the preset signal (PR) are “1”, so that the input control signal CS is The “control signal pass permission state” is given to the control node NDc on the output side as it is.

When the OSM setting signal (OSM_SET) is switched between “0” and “1” as described above, the OSM setting signal (OSM_SET) may be generated from another external CPU or the like.
However, since the purpose of the off-start control is to reduce wasteful power consumption, what is important is the setting of the conduction prohibited state in which the power switch transistors SW1 and SW2 are turned off, that is, the clear signal (CL) is “0”. Therefore, since the OSM setting signal (OSM_SET) is always set to “1” (high level) on the external mounting board, it may be pulled up to the power supply voltage via a resistor or the like. In this case, conduction prohibition and release thereof (control signal passage permission) are controlled by the logic of the reset signal (RST_X).

  Two off-start switch control units 2 are provided corresponding to circuit block A (BLK_A) and circuit block B (BLK_B) in FIG. 1, one of which is provided in circuit block A (BLK_A). The other operates based on the voltage stabilization information from the other POR circuit 4 provided in the circuit block B (BLK_B).

Next, on the premise of the above configuration, the operation of the start control of this embodiment will be described. First, an outline of start control will be described.
FIG. 5 is a flowchart showing an outline of the activation method of the present embodiment. This activation method includes the following steps.

Step ST0: An off start mode setting signal (OSM_SET) is applied to the semiconductor integrated circuit.
Step ST1: Starting the semiconductor integrated circuit with the setting signal (OSM_SET) applied, enables the input of the power supply voltage VDDc or internally generates the power supply voltage VDDc. Here, “validating the input of the power supply voltage VDDc” means that when the VTCMOS voltage regulator 6V is provided outside, the power supply voltage VDDc applied to the power supply terminal of the semiconductor integrated circuit is used as an internal power supply line. It means capturing. Further, “to generate the power supply voltage VDDc internally” corresponds to the case where the control voltage regulator 6C is provided in the semiconductor integrated circuit.

  Step ST2: When the setting signal (OSM_SET) is active (“1”) at the start of startup, the power switch transistors SW1 and SW2 are set in a conduction-inhibited state (clear signal (CL) is “0”) and inactive (“0”) ")", The conduction is not prohibited (clear signal (CL) is set to "1").

  Step ST3: In response to the completion of the predetermined activation process started upon receiving the supply of the power supply voltage VDDc, the off-start mode reset signal (RST_X) is deactivated (“0” → “1”). Here, the “predetermined start-up process” refers to the capture or generation of the power supply voltage VDDm or the subsequent generation of the clock signal CLK and the initialization of the substrate bias voltage VBB control in a specific operation example described later. .

  Step ST4: If the continuity prohibition state has been set after the start of activation, the continuity prohibition state is canceled in response to activation of the reset signal (RST_X) (“0” → “1”) (clear signal (CL) is set). Transition from “0” to “1”). Here, “cancellation of the conduction prohibited state” means that the control signal CS generated thereafter is permitted to pass through the flip-flop circuit FF.

  The correspondence between the above steps and the operation using the next waveform diagram will be described at the end of the description of the operation to clarify the details of the above steps.

FIGS. 6A to 6L are timing charts showing power supply voltages and other voltages and waveforms of various signals.
Here, FIG. 6A shows an input waveform of the power supply voltage VDDc output from the control voltage regulator 6C of FIG. FIG. 6B shows a power input state of the VTCMOS control unit 2A. FIG. 6C shows the voltage VGA of the control node NDc (see FIG. 3A) in the circuit block A (BLK_A), and FIG. 6D shows the voltage VGB of the control node NDc in the circuit block B (BLK_B). Each is shown. FIG. 6E shows input waveforms of the power supply voltage VDDm generated by the main voltage regulator 6M of FIG. 1 and the power supply voltage VDDp generated by the PLL voltage regulator 6P. FIG. 6F shows a waveform of the initial substrate bias voltage VBB. FIG. 6G shows a PLL lock signal (LS_PLL) given from the outside (another CPU or the like on the mounting board) to the PLL unit 5 in FIG. 1, and FIG. 6H shows the clock signal CLK.

FIG. 6I shows a control reset signal (RST_A) that can be externally set and changed by the user to the VTCMOS control unit 2A of FIG. Similarly, FIG. 6K shows a control reset signal (RST_B) that can be externally set and changed by the user to the MTCMOS control unit 2B of FIG. These two control reset signals are initialization signals for operations executed by the VTCMOS control unit 2A and the MTCMOS control unit 2B, and the activation of these control reset signals (time T11) causes the substrate bias voltage VBB of the VTCMOS, respectively. The control sequence and the initialization of the control sequence of the control signal CS (loading of a routine program, etc.) are started.
FIGS. 6J and 6L show input data of the circuit block A (BLK_A) and the circuit block B (BLK_B).

When the semiconductor integrated circuit shown in FIG. 1 is powered on, the semiconductor integrated circuit is activated. Here, turning on the power means applying a power supply voltage from the main voltage regulator 6M, the control voltage regulator 6C, and the PLL voltage regulator 6P, or permitting the input of the power supply voltage already applied to the power supply terminal.
In any case, a voltage appears on the power supply line of the power supply voltage VDDc in the semiconductor integrated circuit as shown in FIG. 6A, and this voltage rises and stabilizes at a value of the predetermined power supply voltage VDDc.

By stabilizing the power supply voltage VDDc, the operation of the VTCMOS control unit 2A is started (FIG. 6B), and at the same time, the operation of the MTCMOS control unit 2B is started. As a result, the voltage VGA applied to the gate of the power switch transistor in the circuit block A (BLK_A) and the voltage VGB applied to the gate of the power switch transistor in the circuit block B (BLK_B) are determined at the “L” level (FIG. 6). (C) and FIG. 6 (D)).
The “L” level determined at this time means prohibition of conduction of the power switch transistor at the start-up, which is a major feature of the present embodiment and is realized by the following operation.

  Since the off-start switch control unit 2 in FIG. 3A is allowed to input the power supply voltage VDDc generated from the control voltage regulator 6C in response to power-on (startup) of the semiconductor integrated circuit, the power supply is supplied. receive. However, since the switch control circuit 20A generates the control signal CS after the control reset (time T11), the power supply voltage VDDc is only supplied to the switch control circuit 20A at this time (time T1).

On the other hand, the power supply voltage VDDc is also supplied to the FF control logic circuit 24, the reset circuit 25, and the flip-flop circuit FF in the off-start switch control unit 2.
The POR circuit 4c for detecting the stabilization of the power supply voltage VDDc is also provided in the MTCMOS control unit 2B. As soon as this detects the stabilization of the power supply voltage VDDc, the operation of setting the clear signal (CL) to “0” 25 and FF control logic circuit 24. Therefore, the MTCMOS control unit 2B (including the off-start switch control unit 2) is activated while the conduction state of the power switch transistors SW1 and SW2 is prohibited.
In FIG. 6C and FIG. 6D, the voltages VGA and VGB are at the “L” level because the off-start control is executed.

At the subsequent time T2, the power supply voltage VDDm and the power supply voltage VDDp are turned on. As a result, the corresponding power supply line voltages rise as shown in FIG. 6E. The power supply voltage VDDp is constant.
At time T3 following time T2, the VTCMOS voltage regulator 6V in FIG. 1 starts outputting the substrate bias voltage VBB. The value of the first substrate bias voltage VBB is given as a specified value at a stage before the routine program for specifying the operation sequence of the substrate bias control is loaded. The initial substrate bias voltage VBB stabilizes at time T5.

Since the circuit block A (BLK_A) is a VTCMOS application block, it is necessary to start the operation in the circuit block first. Therefore, the conduction prohibition of the power switch transistors SW1 and SW2 is released at a time T7 after a predetermined delay time has elapsed since the stabilization of the power supply voltage VDDm (time T4).
Specifically, since the system reset signal (SysRST_X) shown in FIG. 4 changes from “0” to “1” at time T7, the reset signal (RST_X) output from the reset circuit 25 is inactive “ Transition to 1 ″. Therefore, the flip-flop circuit FF in FIG.
At this time T7, the clock signal CLK (high-speed clock signal) shown in FIG. 6 (H) has not yet been generated, but the MTCMOS control unit 2B including the off-start switch control unit 2 shown in FIG. 3 (A). The VTCMOS control unit 2A operates using a low-speed basic clock signal (clock signal before being multiplied by the PLL unit 5) generated internally in the PLL unit 5 or input to the PLL unit 5 from the outside. It is a possible circuit. Therefore, the VTCMOS control unit 2A operates by using the basic clock signal, and can control the deactivation of the reset signal (step ST3) in response to the elapse of the time T7.
Other than the method using the basic clock signal, a clock signal for the control circuit is separately prepared, for example, a method of inputting in advance may be used. However, since a new clock signal is newly generated and the number of terminals is increased, the PLL unit 5 The above method of operating the control circuit with the basic clock signal is more desirable.

  FIG. 6 illustrates a case where the control node NDc is configured to transition to “H” as an initial level when the conduction prohibition is canceled at the time T7 when the control signal is not generated. As a result, power is supplied to the logic cell 11 in FIG. 3A, and the circuit block A (BLK_A) becomes operable. Therefore, thereafter, as shown in FIG. 6J, the input data (IN_A) can be accepted (time T8).

On the other hand, for example, at time T6 delayed from time T5, a PLL lock signal (LS_PLL) for determining the oscillation frequency is given to the PLL unit 5 from an external CPU or the like. Therefore, as shown in FIG. 6 (H), after a standby time of the period TI1 has elapsed from the definite input (rising of the voltage) of the PLL lock signal (LS_PLL), the (high-speed) clock signal CLK is output from the PLL unit 5 from time T10. Is output. When the reset waiting period TI2 passes from time T10, a control reset is applied in accordance with the control reset signal (RST_A) described above, and the VTCMOS control unit 2A starts an initialization operation. This initialization operation includes loading of a routine program that defines an operation sequence.
Thereafter, at time T14 when the initialization waiting period TI3 has elapsed, the startup processing is completed in both the circuit block A (BLK_A) to which VTCMOS is applied and the circuit block B (BLK_B) to which VTCMOS is applied, and normal processing, that is, operation The operation according to the sequence is started.

Since the circuit block B (BLK_B) is not applied with the VTCMOS technology, the start-up process is first advanced in the circuit block A (BLK_A), and the start-up process of the circuit block B (BLK_B) that does not require data input is performed at time T14. Delayed as much as possible so that the end is in time. That is, until time T13, the circuit block B (BLK_B) does not release the prohibition of conduction of the power switch transistors SW1 and SW2, and therefore, waste of power consumption can be greatly reduced.
In addition, the release timing of the conduction prohibition at time T13 is determined by the user setting by the system reset signal (SysRST_X) in FIG.

When there are a plurality of circuit blocks to which VTCMOS is not applied, even if the normal operation starts, the delay time operation for releasing the conduction prohibition of the power switch transistors SW1 and SW2 is increased for a certain circuit block until it becomes necessary. By performing control without energization, power consumption can be further suppressed. Note that the system reset signal (SysRST_X) shown in FIG. 4 for determining the delay time in this case may be read out from the program of the operation sequence.
Further, the conduction prohibition and release control by the clear signal (CL) of the flip-flop circuit FF performed in the above-described off-start control is controlled by MTCMOS control on the assumption that off-start control is performed in addition to the power switch transistor control. The control of other necessary signals can be similarly performed. Such signals include a fence signal that prevents indefinite propagation and a circuit for holding data (a control signal related to the data holding flip-flop circuit FF).

  Further, although the off-start start-up has been described for the combined use with the VTCMOS technology, DVC (Dynamic Voltage Control) for adaptively changing the substrate bias voltage VBB may be performed in the subsequent normal operation.

FIG. 6M shows a correspondence relationship with each step shown in FIG.
At start-up (time T0), the off-start mode (OSM) setting signal (OSM_SET) in step ST0 is applied.
Step ST1 is a process in which the power supply voltage VDDc is stabilized in the internal power supply line by the validation of the input of the power supply voltage (time T0 to time T1).
Step ST2 is a process in which the reset signal (RST_X) is activated (“0”) in response to the stabilization detection by the POR circuit 4c, and thereby the clear signal (CL) of the flip-flop circuit FF is set to “0”. (Slight time from time ST2).
In step ST3, as an example of the “predetermined start-up process”, the reset signal (RST_X) is changed from active (“0”) to inactive (“1”) in response to completion of detection of stabilization of the power supply voltage VDDm or the like. (Slightly before time T4 to time T7). Alternatively, as another example, the reset signal (RST_X) is deactivated (“0” → “1”) in response to the completion of the generation of the clock signal CLK and the initialization of the substrate bias control. A little before time T4 to time T13).
In step ST4, the clear signal (CL) is changed from “0” to “1” in a short time from the time T7 or the time T13, thereby releasing the conduction prohibition of the power switch transistors SW1 and SW2.

  According to the present embodiment, the disadvantages received in the past can be eliminated as follows, and unnecessary power from when the circuit power is turned on (startup) to when the circuit operation is actually started can be deleted.

  Generally, a waiting time of several [ms] is required from power-on (start-up) to stabilization of the power supply voltage, and then several [ms] are required until the PLL unit that generates the clock signal is locked in. . In addition, a process in which a CPU or the like that operates based on the generated clock signal loads a necessary program from a memory may be included in the startup process together with the power supply stabilization and the generation of the clock signal.

In general, the MTCMOS technology is not applied to the control circuits related to these startup processes.
However, many circuit blocks to which the MTCMOS technology is applied are irrelevant to the startup process. Among them, for a circuit block whose operation sequence is determined to operate immediately after startup, even if the power switch transistor is turned on immediately after power stabilization, this does not constitute a significant disadvantage in terms of power consumption.

However, if many circuit blocks having a relatively long standby time after activation are included, there is a great disadvantage in terms of power consumption.
More specifically, the potential of the internal voltage line of the circuit block that does not operate for a relatively long standby time after startup, for example, the potential of the virtual GND line, is slowly charged by the leakage current in the circuit over a long standby time. On the other hand, even if the power switch transistor is turned on to stabilize the power supply voltage after startup and the potential of the virtual GND line is lowered to the GND level, the virtual GND line is still charged in a long standby time. For this reason, useless power consumption is generated only by turning on the power switch transistor and discharging the virtual GND line.

In this embodiment, such wasteful power consumption can be prevented.
Further, in the case where a circuit standby is required for a certain period of time after the power is turned on, such as the time until the output of the PLL unit is stabilized, unnecessary power can be reduced.

1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention. (A) to (C) are diagrams showing three modes of power switch control applicable in this embodiment. FIG. 2A is a circuit block diagram showing FIG. 2A in more detail. (B) is a chart of an input / output state showing functions of the FF control logic circuit. FIG. 3 is a circuit block diagram showing a relationship between a configuration of a reset circuit and a POR circuit, and a function of the POR circuit. It is a flowchart which shows the outline | summary of the starting method of this embodiment. (A)-(L) are timing charts at the time of execution of the starting method concerning this embodiment. (M) is a timing chart which shows the relationship with each step of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1A ... Chip area, 2 ... Off start switch control part, 2A ... VTCMOS control part, 2B ... MTCMOS control part, 4, 4c ... POR circuit, 5 ... PLL part, 6C ... Control voltage regulator, 6M ... Main voltage regulator, 6P ... PLL voltage regulator, 6V ... VTCMOS voltage regulator, 11 ... logic cell, 20A, etc .... switch control unit, 21 ... reference voltage supply line, 22 (L) ... internal voltage line, 23C ... control power supply voltage supply line, 23M ... Main power supply voltage supply line, 24 ... FF control logic circuit, 25 ... Reset circuit, FF ... Flip-flop circuit, (BLK_A), etc. Circuit block, SW1, etc .... Power switch transistor, CS ... Control signal, (RST_X) ... Reset signal , (POR_X), (PORc_X)... POR detection signal, (SysRST_X) System reset signal, (OSM_SET) ... OSM of the setting signal

Claims (6)

A circuit unit that operates upon receiving a supply voltage; and
A power supply switch transistor provided in a path of a power supply current that flows when the power supply voltage is supplied to the circuit unit; and a threshold voltage higher than a transistor in the circuit unit;
When the setting signal of the off-start mode input from the outside is active at the start-up, the start-up operation is started with the power switch transistor being in a conduction-inhibited state, and when the setting signal is inactive at the start-up, the power switch A control unit for starting the start-up operation without prohibiting conduction of the transistor;
A semiconductor integrated circuit having the same semiconductor substrate. The controller is
A switch control circuit for generating a control signal for controlling conduction and non-conduction of the power switch transistor;
A reset circuit for deactivating the reset signal in the off-start mode in response to completion of a predetermined activation process after the start of the activation operation;
Provided between the switch control circuit and the control node of the power switch transistor. When the setting signal is active at the time of activation, it is activated in the conduction prohibited state, and after activation, responds to the inactivation of the reset signal. And a regulation circuit that allows the control signal from the activated switch control circuit to pass by releasing the conduction prohibition state, and
The semiconductor integrated circuit according to claim 1, comprising: A power supply stabilization detector that detects the stabilization of the power supply voltage as the predetermined startup process;
In response to the stabilization of the power supply voltage detected by the power stabilization detection unit, the reset circuit is activated when a delay time that can be set and changed by a user has elapsed from the stabilization. 3. A semiconductor integrated circuit according to claim 2, further comprising: a circuit that inputs a signal that is activated when the power supply voltage is stabilized, and that activates the reset signal when the two input signals are both activated. . An internal power supply voltage generating section for generating an internal power supply voltage of a substrate bias applied to the transistor in the circuit section;
A power supply voltage stabilization detector for detecting the stabilization of the power supply voltage;
An internal power supply stabilization detector for detecting the stabilization of the internal power supply voltage;
A clock signal generator for generating a clock signal;
A substrate bias controller that starts initialization upon input of the clock signal;
As the predetermined start-up process, the stabilization detection of the power supply voltage, the generation and stabilization detection of the internal power supply voltage, the generation of the clock signal, and the initialization process of the substrate bias control unit are all completed. The semiconductor integrated circuit according to claim 2, wherein the reset circuit activates the reset signal in response. The regulation circuit is
A flip-flop circuit provided between the switch control circuit and a control node of the power switch transistor;
The setting signal and the reset signal are input, and when the setting signal and the reset signal are both active, the output of the flop flop is fixed to a logic that sets the power switch transistor in the conduction-inhibited state, and the setting When the signal is inactive and the reset signal is active, the output of the flip-flop circuit is fixed to the logic opposite to the logic, and in other combinations of input logic, the logic according to the control signal is set to the flip-flop. A logic circuit that generates a clear signal and a preset signal that can appear at an output of the circuit, and outputs the generated clear signal and the preset signal to a control input of the flip-flop circuit;
The semiconductor integrated circuit according to claim 2, comprising: A method for starting a semiconductor integrated circuit, wherein a path of a power supply current that flows when supplying a power supply voltage to a circuit can be controlled by a power supply switch transistor having a threshold voltage higher than that of a transistor in the circuit,
Applying an off-start mode setting signal to the semiconductor integrated circuit;
Starting the semiconductor integrated circuit in a state where the setting signal is applied, enabling the input of the power supply voltage, or generating the power supply voltage internally;
When the setting signal is active at the start of the activation, the power switch transistor is in a conduction prohibited state, and when inactive, the step of not in the conduction prohibited state;
Deactivating the reset signal in the off-start mode in response to completion of a predetermined start-up process started by receiving the supply of the power supply voltage;
If the continuity prohibition state is in effect after the start of the activation, releasing the continuity prohibition state in response to the inactivation of the reset signal;
A method for starting a semiconductor integrated circuit comprising:

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