CN103378846A - Device for converting logic signal into low voltage differential signal - Google Patents
Device for converting logic signal into low voltage differential signal Download PDFInfo
- Publication number
- CN103378846A CN103378846A CN2012101176488A CN201210117648A CN103378846A CN 103378846 A CN103378846 A CN 103378846A CN 2012101176488 A CN2012101176488 A CN 2012101176488A CN 201210117648 A CN201210117648 A CN 201210117648A CN 103378846 A CN103378846 A CN 103378846A
- Authority
- CN
- China
- Prior art keywords
- resistance
- output
- signal
- unit
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Dc Digital Transmission (AREA)
- Logic Circuits (AREA)
Abstract
The invention discloses a device for converting a common dual-level logic signal into an LVDS. The device comprises a logic output unit and a trapezoidal resistor network unit. The single-end logic signal is input into the logic output unit and converted into a positive-negative logic signal in the logic output unit, then partial pressure and level conversion of the positive-negative logic signal are achieved through the trapezoidal resistor network unit, and under the condition that the load of an output port is 100 ohms, the voltage signal meeting the low voltage differential signal electrical standard is output. The working conditions of the device are free of limitation of the voltage of the logic signal. The device for converting the common dual-level logic signal into the LVDS is applicable to the transmission occasions of interface conversion between the common dual-level logic signal and the LVDS, and particularly applicable to converting a common positive-negative logic signal in an FPGA into the LVDS.
Description
Technical field
The present invention relates to high-speed communication circuit and integrated circuit (IC) design technical field, especially a kind of logical signal is converted to the device of Low Voltage Differential Signal, this device is not subjected to the restriction of logic signal levels voltage, has general adaptive characteristics.
Background technology
In high speed serial transmission, adopt Low Voltage Differential Signal (low-voltage differential signal, LVDS) to carry out the method for transmitting data in physical layer very general for electrical standard, the LVDS standard is a kind of I/O electrical standard for the high speed base band data transmission that Telecommunications Industry Association (TIA) tissue is announced, and it has speed height, low in energy consumption, characteristics that anti-noise ability is strong.The LVDS electrical standard has clear and definite regulation for common-mode voltage and the differential mode voltage scope of differential output signal, Fig. 1 is LVDS electrical standard key diagram, under the condition with 100 ohm load, LVDS output common mode voltage is about 1.25V, the differential mode voltage scope at 250mV between the 450mV.
At present integrated special-purpose input/output port in the special chip of HSSI High-Speed Serial Interface can be supported the LVDS electrical standard, but, since its particularity, the Limited Number of these special-purpose input/output ports, and large multi-chip input/output port can only be processed common two-level logic signal.Under a lot of applicable cases, owing to be exclusively used in the restriction of LVDS electrical standard input/output port purpose, common output port need to and be supported to carry out transfer of data between the input port of LVDS electrical standard, therefore the two-level logic signal need to be converted into the signal of telecommunication that meets the LVDS electrical standard.
(the patent No.: US 6353334B1) in the United States Patent (USP) that Xilinx company applies for, a kind of external circuits that is made of three resistance has been proposed, can realize the two-level logic signal is converted to the differential output signal that meets the LVDS standard, Fig. 2 is the key diagram of its implementation, wherein R1 (resistance 1) is identical with R5, resistance is 175 ohm, the R3 resistance is 140 ohm, be connected across the LVDS difference output end, R6 is connected across the LVDS differential input end, resistance is 100 ohm, R1, R5, R3 is generally by the outer meeting resistance realization, and the impedance matching R6 of ohm is generally in the inner realization of the LVDS of chip input port, and the one side of choosing of trapezoid resistance network resistance is mated in order to realize transmission line 50 ohm characteristic impedance, on the other hand, can the two-level logic signal be converted to the difference output that meets the LVDS standard by dividing potential drop.Fig. 3 is the circuit structure diagram of transfer process, because R3 is in parallel with R6, be connected to respectively again the high-low level end of the common output logic signal of output by R1 and R5, compare with outer meeting resistance, the internal resistance of common output logic can be ignored, therefore, the LVDS differential output voltage of changing, namely the voltage difference of 2 of LV1 and LV2 is:
(VDD-VSS)*(R3//R6))/(R1+R5+(R3//R6))
＝0.14*(VDD-VSS)，
The LVDS common mode output voltage of changing is the average voltage of 2 of LV1 and LV2, because the symmetric characteristics of trapezoid resistance network, the common mode output level is as can be known:
0.5*(VDD-VSS)，
Wherein, (R3//R6) parallel resistance of expression R3 and R6, (VDD-VSS) level voltage of presentation logic signal is poor, it is 1.25V that the LVDS electrical standard requires the common mode output level, therefore (VDD-VSS) must be 2.5V, then corresponding LVDS differential output voltage is about 357mV, satisfies LVDS electrical standard (differential output voltage scope: 250mV-450mV).Generally speaking, the level voltage of General Logic signal is poor to be exactly its IO (input and output) voltage, therefore, the common mode electrical level of LVDS end difference output depends on IO (input and output) voltage, be half of IO (input and output) voltage, because it is 1.25V that the LVDS electrical code requires the common mode electrical level of output, the General Logic signal high level voltage that therefore can carry out conversion is limited in about 2.5V, thereby has limited the range of application of the method.The voltage standard (1.8V, 2.5V, 3.3V, 5V etc.) of a great variety of at present input and output (I/O) port employing, and the application scenario is also comparatively complicated, Given this, the present invention proposes a kind of novel circuit arrangement, it is not subjected to the restriction of input and output (I/O) voltage standard, the logical signal under the different voltage standards can be converted to the differential signal that meets the LVDS electrical standard.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of novel circuit arrangement, and it is not subjected to the restriction of input and output (I/O) voltage standard, the logical signal under the different voltage standards can be converted to the differential signal that meets the LVDS electrical standard.
The present invention proposes and a kind of logical signal is converted to the device of Low Voltage Differential Signal, it is characterized in that this device comprises logic output unit and trapezoid resistance network unit, wherein,
Described logic output unit comprises a logical node and three inverters, logical node is divided into two-way output, leading up to inverter inv1 and inv2 consists of the forward output out_p of logical signal, and another road consists of the reverse output out_n of logical signal by inverter inv3;
The ladder shaped resistance potential-divider network of described trapezoid resistance network unit for being consisted of by 5 resistance, wherein, the forward output out_p of one termination logical signal of resistance R 1, the other end joins with resistance R 2 and R3, the reverse output out_n of one termination logical signal of resistance R 5, the other end joins with resistance R 4 and R3, the termination additional power source of R2, the other end and R1 and R3 join, the termination additional power source of R4, the other end and R5 and R3 join, termination R1 and the R2 of R3, the other end and R4 and R5 join, and the two ends of R3 are output port LV1 and the LV2 of described trapezoid resistance network unit;
Single-ended logical signal is input to described logic output unit, after in the logic output unit, becoming the positive and negative logic signal, realize dividing potential drop and level conversion by described trapezoid resistance network unit, be that output meets the voltage signal of Low Voltage Differential Signal electrical standard under 100 ohm the condition in the output port load.
The condition of work of circuit arrangement of the present invention is not subjected to the restriction of logical signal voltage, be applicable to common double level logic signal and low-voltage differential to the transmission occasion of signal (LVDS) interface conversion, be specially adapted to common positive and negative logic signal among the FPGA is converted into low-voltage differential to signal (LVDS).
Description of drawings
Fig. 1 is LVDS electrical standard key diagram;
Fig. 2 is the implementation key diagram that the two-level logic signal is converted to the differential output signal that meets the LVDS standard of Xilinx company application;
Fig. 3 is the circuit structure diagram of Fig. 2 transfer process;
Fig. 4 is a kind of circuit implementation key diagram that logical signal under the different voltage standards is converted to the differential signal that meets the LVDS electrical standard that the present invention proposes:
Fig. 5 is the ac equivalent circuit figure of trapezoid resistance network unit 401 interior resistance pressure-dividing networks among Fig. 4;
Fig. 6 is device shown in Figure 4 at logical signal voltage is circuit implementation key diagram under the 3.3V condition;
Fig. 7 is the ac equivalent circuit figure of trapezoid resistance network unit 601 interior resistance pressure-dividing networks among Fig. 6;
Fig. 8 is device shown in Figure 4 at logical signal voltage is circuit implementation key diagram under the 1.8V condition;
Fig. 9 is the ac equivalent circuit figure of trapezoid resistance network unit 801 interior resistance pressure-dividing networks among Fig. 8.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present invention proposes a kind of circuit arrangement that the logical signal under the different voltage standards can be converted to the differential signal that meets the LVDS electrical standard, the present invention is based on the trapezoid resistance network voltage divider principle, by dividing potential drop significant single-ended signal is transformed to by a small margin differential signal, characteristics of the present invention are to adjust by the method for introducing additional power source the common-mode voltage of differential signal, thereby so that the condition of work of this circuit arrangement no longer is subjected to the restriction of logical signal voltage, can under multiple input and output (IO) voltage standard, work, 1.8V for example, 2.5V, 3.3V, 5V etc., in actual application, additional power source is put the level voltage of general multiplexing logic output unit 400 or the zero level earth point in the device, can not require extra power supply.
The structure of described circuit arrangement as shown in Figure 4, this circuit arrangement comprises: logic output unit 400 and trapezoid resistance network unit 401.In order to be described clearly the applied environment of this device, added the differential receiver unit 402 that can receive trapezoid resistance network unit 401 output signals among Fig. 4, need to prove, differential receiver unit 402 is not the necessary component of this device, in actual applications, the user can select different receiving elements to carry out the subsequent treatment of signal as required.Single-ended logical signal is input to logic output unit 400, after in logic output unit 400, becoming the positive and negative logic signal, realize dividing potential drop and level conversion by the resistance pressure-dividing network in the trapezoid resistance network unit 401, be under 100 ohm the condition (this load is generally provided by the integrated resistor in the differential receiver unit 402) in the output port load, output meets the voltage signal of Low Voltage Differential Signal (LVDS) electrical standard, the output signal of trapezoid resistance network unit 401 is transferred to the LVDS input of differential receiver unit 402, be used as the input signal of differential receiver unit 402, particularly:
The ladder shaped resistance potential-divider network of trapezoid resistance network unit 401 for being consisted of by 5 resistance, it is for the key of circuit arrangement of the present invention, trapezoid resistance network unit 401 comes the common-mode voltage of adjusting resistance potential-divider network output differential signal by introducing additional power source, make the common-mode voltage of differential signal meet the LVDS electrical standard.Wherein, resistance R 1 is identical with resistance R 5, and resistance R 2 is identical with resistance R 4, and the resistance of R2 and R4 is greater than R1 and R5.The forward output out_p of the termination logical signal of R1, the other end and R2 and R3 join, the reverse output out_n of the termination logical signal of R5, the other end and R4 and R3 join, the termination additional power source of R2, the other end and R1 and R3 join, the termination additional power source of R4, the other end and R5 and R3 join, termination R1 and the R2 of R3, the other end and R4 and R5 join, and the two ends of R3 are output port LV1 and the LV2 of resistance pressure-dividing network for this reason.
Additional power source in the trapezoid resistance network unit 401 can apply according to physical condition, but need to abide by the principle: when the logical signal high-low level voltage difference of logic output unit 400 output during greater than 2.5V, additional power source voltages in the trapezoid resistance network unit 401 should be lower than 1.25V (recommend connecting to neutral or connect logic low voltage in the logic output unit 400), when the logical signal high-low level voltage difference of logic output unit 400 outputs is lower than 2.5V, additional power source voltage in the trapezoid resistance network unit 401 should be higher than 1.25V (recommendation connects the logic high voltage in the logic output unit 400), be that the output of this resistance pressure-dividing network (LV1 and LV2) produces the signal that meets the LVDS electrical standard under 100 ohm the condition in the output port load.
The circuit of differential receiver unit 402 can be any circuit interface that can receive the LVDS input, in order to reduce reflection, the integrated resistor R6 that generally has 100 ohm is connected across between differential receiver unit 402 differential signal input ports, and in parallel with the resistance R 3 of trapezoid resistance network unit 401, resistance R 6 is simultaneously also as the load resistance of trapezoid resistance network unit 401.When differential receiver unit 402 does not have integrated resistor R6, be recommended in the off chip resistor near 100 ohm of differential receiver unit 402 input pin place cross-over connections.
In order to guarantee good signal transmission, also should be taken into account impedance matching, reach good impedance matching, must guarantee that the resistance to earth of resistance pressure-dividing network output point under the interchange condition of trapezoid resistance network unit 401 is 50 ohm, so when choosing the resistance of resistance R 1, R2, R3, R4 and R5, must consider the qualifications of voltage transitions and two aspects of impedance matching.
Fig. 5 is the ac equivalent circuit figure of the resistance pressure-dividing network of trapezoid resistance network unit 401 among Fig. 4, scheme medium and small triangle representative and exchange ground, exchanging under the equivalent condition, the end points that is connected with all power supplys can be equivalent for exchanging ground, R3_1=R3_2=R3/2 wherein, namely the resistance of R3_1 is half of resistance of the resistance R 3 of trapezoid resistance network unit 401 among Fig. 4, in this ac equivalent circuit figure, R1 one termination exchanges ground, the other end and R2 and R3_1 join, and R5 one termination exchanges ground, and the other end is connected with R4 and R3_2, R2 one termination exchanges ground, the other end and R1 and R3_1 join, and R4 one termination exchanges ground, and the other end and R5 and R3_2 join, R3_1 one termination R1 and R2, and as difference output point LV1, another termination exchanges ground, R3_2 one termination R4 and R5, and as difference output point LV2, another termination exchanges ground.Output LV1 must satisfy 50 ohm characteristic impedance coupling to the equivalent resistance that exchanges ground.
Fig. 6 is work sheet under 3.3V or 5V (situation when logical signal voltage is 5V the is not shown) condition for this circuit arrangement at logical signal voltage, and the figure acceptance of the bid understands the resistance that uses.In order to be described clearly the applied environment of this device, added differential receiver unit 602 among Fig. 6, as mentioned above, differential receiver unit 602 is not the necessary component of these apparatus of the present invention.Operation principle shown in Figure 6 is as follows:
The resistance pressure-dividing network of trapezoid resistance network unit 601 for being consisted of by 5 resistance, it is the key of circuit arrangement for this reason, wherein resistance R 1 is 220 ohm with the resistance of resistance R 5, resistance R 2 is 1000 ohm with the resistance of resistance R 4, the resistance of resistance R 3 is 140 ohm, and these resistances can be tolerated 2% variation.The forward output out_p of the termination logical signal of R1, the other end and R2 and R3 join, the reverse output out_n of the termination logical signal of R5, the other end and R4 and R3 join, the termination 0V additional power source of R2, the other end and R1 and R3 join, the termination 0V additional power source of R4, the other end and R5 and R3 join, termination R1 and the R2 of R3, the other end and R4 and R5 join, and the two ends of R3 are output port LV1 and the LV2 of resistance pressure-dividing network for this reason.
Be that it is 1.253V that the output of this resistance pressure-dividing network (LV1 and LV2) produces the differential signal common-mode voltage under 100 ohm the condition in the output port load, the differential signal voltage amplitude is the signal of 353mV, meets the LVDS electrical standard.
The circuit of differential receiver unit 602 can be any circuit interface that can receive the LVDS input, in order to reduce reflection, the resistance R 6 that generally has 100 ohm is connected across between differential receiver unit 602 differential signal input ports, and in parallel with the resistance R 3 of trapezoid resistance network unit 601, resistance R 6 is simultaneously also as the load resistance of trapezoid resistance network unit 601.When differential receiver unit 602 does not have integrated resistor R6, be recommended in the off chip resistor near 100 ohm of differential receiver unit 602 input pin place cross-over connections.
Fig. 7 is the ac equivalent circuit figure of the resistance pressure-dividing network of trapezoid resistance network unit 601 among Fig. 6, reach good impedance matching, must guarantee that the resistance to earth of resistance pressure-dividing network output point under the interchange condition of trapezoid resistance network unit 601 is 50 ohm, scheme medium and small triangle representative and exchange ground, exchanging under the equivalent condition, the end points that is connected with all power supplys can be equivalent for exchanging ground, R3_1=R3_2=70 ohm wherein, the resistance that is R3_1 and R3_2 is half of resistance of the resistance R 3 of trapezoid resistance network unit 601 among Fig. 6, in this ac equivalent circuit figure, R1 one termination exchanges ground, and the other end and R2 and R3_1 join, R2 one termination exchanges ground, the other end and R1 and R3_1 join, and R4 one termination exchanges ground, and the other end and R5 and R3_2 join, R3_1 one termination R1 and R2, and as difference output point LV1, another termination exchanges ground, R3_2 one termination R4 and R5, and as difference output point LV2, another termination exchanges ground.Difference output point LV1 among Fig. 7 and LV2 are R1//R2//(R3_1)=50.5 ohm to the output impedance that exchanges ground.
Fig. 8 is work sheet under the 1.8V condition for this circuit arrangement at logical signal voltage, the figure acceptance of the bid understands the resistance that uses, in order to be described clearly the applied environment of this device, added differential receiver unit 802 among Fig. 8, as mentioned above, differential receiver unit 802 is not the necessary component of this device.Operation principle shown in Figure 8 is as follows:
Logic output unit 800 comprises a logical node and three inverters, logical node is divided into two-way output, leading up to inverter inv1 and inv2 consists of the forward output out_p of logical signal, and another road consists of the reverse output out_n of logical signal by inverter inv3.The high level of these output logic signals is 1.8V, and low level is 0V.
The resistance pressure-dividing network of trapezoid resistance network unit 801 for being consisted of by 5 resistance, it is the key of circuit arrangement for this reason, wherein resistance R 1 is 130 ohm with the resistance of resistance R 5, resistance R 2 is 200 ohm with the resistance of resistance R 4, the resistance of resistance R 3 is 275 ohm, and these resistances can be tolerated 2% variation.The forward output out_p of the termination logical signal of R1, the other end and R2 and R3 join, the reverse output out_n of the termination logical signal of R5, the other end and R4 and R3 join, the termination 1.8V additional power source of R2, the other end and R1 and R3 join, the termination 1.8V additional power source of R4, the other end and R5 and R3 join, termination R1 and the R2 of R3, the other end and R4 and R5 join, and the two ends of R3 are output port LV1 and the LV2 of resistance pressure-dividing network for this reason.
Be that it is 1.249V that the output of this resistance pressure-dividing network (LV1 and LV2) produces the differential signal common-mode voltage under 100 ohm the condition in the output port load, the differential signal voltage amplitude is the signal of 355mV, meets the LVDS electrical standard.
The circuit of differential receiver unit 802 can be any circuit interface that can receive the LVDS input, in order to reduce reflection, the resistance R 6 that generally has 100 ohm is connected across between differential receiver unit 802 differential signal input ports, in parallel with the resistance R 3 of trapezoid resistance network unit 801, resistance R 6 is simultaneously also as the load resistance of trapezoid resistance network unit 801.When differential receiver unit 802 does not have integrated resistor R6, be recommended in the off-chip capacitive resistance near 100 ohm of differential receiver unit 802 input pin place cross-over connections.
Fig. 9 is the ac equivalent circuit figure of the resistance pressure-dividing network of trapezoid resistance network unit 801 among Fig. 8, reach good impedance matching, must guarantee that the resistance to earth of resistance pressure-dividing network output point under the interchange condition of trapezoid resistance network unit 801 is 50 ohm, scheme medium and small triangle representative and exchange ground, exchanging under the equivalent condition, the end points that is connected with power supply can be equivalent for exchanging ground, R3_1=R3_2=137.5 ohm wherein, the resistance that is R3_1 and R3_2 is half of resistance of the resistance R 3 of trapezoid resistance network unit 601 among Fig. 6, in this ac equivalent circuit figure, R1 one termination exchanges ground, and the other end and R2 and R3_1 join, R2 one termination exchanges ground, the other end and R1 and R3_1 join, and R4 one termination exchanges ground, and the other end and R5 and R3_2 join, R3_1 one termination R1 and R2, and as difference output point LV1, another termination exchanges ground, R3_2 one termination R4 and R5, and as difference output point LV2, another termination exchanges ground.Difference output point LV1 among Fig. 9 and LV2 are R1//R2//(R3_1)=49.7 ohm to the output impedance that exchanges ground.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. one kind is converted to the device of Low Voltage Differential Signal with logical signal, it is characterized in that this device comprises logic output unit and trapezoid resistance network unit, wherein,
Described logic output unit comprises a logical node and three inverters, logical node is divided into two-way output, leading up to inverter inv1 and inv2 consists of the forward output out_p of logical signal, and another road consists of the reverse output out_n of logical signal by inverter inv3;
The ladder shaped resistance potential-divider network of described trapezoid resistance network unit for being consisted of by 5 resistance, wherein, the forward output out_p of one termination logical signal of resistance R 1, the other end joins with resistance R 2 and R3, the reverse output out_n of one termination logical signal of resistance R 5, the other end joins with resistance R 4 and R3, the termination additional power source of R2, the other end and R1 and R3 join, the termination additional power source of R4, the other end and R5 and R3 join, termination R1 and the R2 of R3, the other end and R4 and R5 join, and the two ends of R3 are output port LV1 and the LV2 of described trapezoid resistance network unit;
Single-ended logical signal is input to described logic output unit, after in the logic output unit, becoming the positive and negative logic signal, realize dividing potential drop and level conversion by described trapezoid resistance network unit, be that output meets the voltage signal of Low Voltage Differential Signal electrical standard under 100 ohm the condition in the output port load.
2. device according to claim 1 is characterized in that, the resistance R 1 of described trapezoid resistance network unit is identical with resistance R 5, and resistance R 2 is identical with resistance R 4, and the resistance of R2 and R4 is greater than R1 and R5.
3. device according to claim 1 is characterized in that, described trapezoid resistance network unit comes the common-mode voltage of adjusting resistance potential-divider network output differential signal by introducing additional power source, make the common-mode voltage of differential signal meet the LVDS electrical standard.
4. device according to claim 1, it is characterized in that, the applying of additional power source of described trapezoid resistance network unit abides by the principle: when the logical signal high-low level voltage difference of described logic output unit output during greater than 2.5V, the additional power source voltage of described trapezoid resistance network unit is lower than 1.25V; When the logical signal high-low level voltage difference of described logic output unit output was lower than 2.5V, the additional power source voltage of described trapezoid resistance network unit was higher than 1.25V.
5. device according to claim 1 is characterized in that, the further connection in described trapezoid resistance network unit can receive the differential receiver unit of the voltage signal that meets the Low Voltage Differential Signal electrical standard, so that its output signal is carried out subsequent treatment.
6. device according to claim 5 is characterized in that, described load is provided by the integrated resistor in the described differential receiver unit.
7. device according to claim 5 is characterized in that, described differential receiver unit differential signal input port span is connected to integrated resistor R6 100 ohm, in parallel with the resistance R 3 of described trapezoid resistance network unit, to reduce reflection.
8. device according to claim 7 is characterized in that, when described differential receiver unit does not have integrated resistor R6, at the off chip resistor near 100 ohm of described differential receiver unit input pin place cross-over connections.
9. device according to claim 1 is characterized in that, in order to reach good impedance matching, the resistance to earth of resistance pressure-dividing network output point under the interchange condition of described trapezoid resistance network unit is 50 ohm.
10. device according to claim 1 is characterized in that, the zero level earth point in the level voltage of the multiplexing described logic output unit of described additional power source or the device does not require extra power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210117648.8A CN103378846B (en) | 2012-04-20 | 2012-04-20 | A kind of device that logical signal is converted to Low Voltage Differential Signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210117648.8A CN103378846B (en) | 2012-04-20 | 2012-04-20 | A kind of device that logical signal is converted to Low Voltage Differential Signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103378846A true CN103378846A (en) | 2013-10-30 |
| CN103378846B CN103378846B (en) | 2016-06-29 |
Family
ID=49463468
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210117648.8A Active CN103378846B (en) | 2012-04-20 | 2012-04-20 | A kind of device that logical signal is converted to Low Voltage Differential Signal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103378846B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105973274A (en) * | 2016-04-27 | 2016-09-28 | 深圳市英威腾电气股份有限公司 | Signal detection circuit and apparatus thereof |
| CN106374905A (en) * | 2016-08-29 | 2017-02-01 | 邦彦技术股份有限公司 | signal transmission circuit and communication device |
| CN107196610A (en) * | 2017-05-11 | 2017-09-22 | 中国科学院微电子研究所 | Switch power amplifier |
| CN111900975A (en) * | 2020-08-06 | 2020-11-06 | 中科亿海微电子科技（苏州）有限公司 | Level conversion circuit for converting high-voltage domain signal into low-voltage domain signal |
| WO2023245663A1 (en) * | 2022-06-24 | 2023-12-28 | 京东方科技集团股份有限公司 | Display module and display apparatus |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5126601A (en) * | 1990-11-15 | 1992-06-30 | Ncr Corporation | Driver and receiver for a differential-signal electrical interface |
| US6353334B1 (en) * | 2000-01-27 | 2002-03-05 | Xilinx, Inc. | Circuit for converting a logic signal on an output node to a pair of low-voltage differential signals |
| CN1703011A (en) * | 2004-05-11 | 2005-11-30 | 国际商业机器公司 | Initialization of a bidirectional, self-timed parallel interface with automatic testing of AC differential wire pairs |
| CN201294607Y (en) * | 2008-11-11 | 2009-08-19 | 青岛海信电器股份有限公司 | Debug circuit |
| CN102288215A (en) * | 2011-07-27 | 2011-12-21 | 上海耀华称重系统有限公司 | High-precision strain sensor simulator |
-
2012
- 2012-04-20 CN CN201210117648.8A patent/CN103378846B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5126601A (en) * | 1990-11-15 | 1992-06-30 | Ncr Corporation | Driver and receiver for a differential-signal electrical interface |
| US6353334B1 (en) * | 2000-01-27 | 2002-03-05 | Xilinx, Inc. | Circuit for converting a logic signal on an output node to a pair of low-voltage differential signals |
| CN1703011A (en) * | 2004-05-11 | 2005-11-30 | 国际商业机器公司 | Initialization of a bidirectional, self-timed parallel interface with automatic testing of AC differential wire pairs |
| CN201294607Y (en) * | 2008-11-11 | 2009-08-19 | 青岛海信电器股份有限公司 | Debug circuit |
| CN102288215A (en) * | 2011-07-27 | 2011-12-21 | 上海耀华称重系统有限公司 | High-precision strain sensor simulator |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105973274A (en) * | 2016-04-27 | 2016-09-28 | 深圳市英威腾电气股份有限公司 | Signal detection circuit and apparatus thereof |
| CN106374905A (en) * | 2016-08-29 | 2017-02-01 | 邦彦技术股份有限公司 | signal transmission circuit and communication device |
| CN106374905B (en) * | 2016-08-29 | 2019-05-28 | 邦彦技术股份有限公司 | signal transmission circuit and communication device |
| CN107196610A (en) * | 2017-05-11 | 2017-09-22 | 中国科学院微电子研究所 | Switch power amplifier |
| CN107196610B (en) * | 2017-05-11 | 2020-11-10 | 中国科学院微电子研究所 | Switching power amplifier |
| CN111900975A (en) * | 2020-08-06 | 2020-11-06 | 中科亿海微电子科技（苏州）有限公司 | Level conversion circuit for converting high-voltage domain signal into low-voltage domain signal |
| WO2023245663A1 (en) * | 2022-06-24 | 2023-12-28 | 京东方科技集团股份有限公司 | Display module and display apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103378846B (en) | 2016-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103378846A (en) | Device for converting logic signal into low voltage differential signal | |
| CN105958822B (en) | Voltage conversion circuit | |
| CN102324922B (en) | Low voltage difference signal drive circuit and digital signal conveyer | |
| US20130099822A1 (en) | Cml to cmos conversion circuit | |
| CN108924459A (en) | A kind of output interface circuit and device | |
| CN110289848A (en) | Voltage level converting | |
| CN107872218B (en) | Current mode logic circuit | |
| CN110968014A (en) | Bidirectional MIPI interface circuit based on FPGA universal interface and operation method thereof | |
| CN105550150B (en) | A kind of M-phy driving circuits with dynamic electric resistor mismatch adjustment function | |
| US10003339B1 (en) | General purpose interface circuit compatible with output of MIPI signals | |
| CN107341118A (en) | A kind of common interface circuit of compatible MIPI signal outputs | |
| CN103605627A (en) | One-wire full-duplex bus | |
| KR102335001B1 (en) | Single-wire communication system and control method thereof | |
| CN106598900B (en) | LVDS driver circuit | |
| CN105207661A (en) | Multi-point low voltage differential signal transmitter | |
| CN211403179U (en) | Bidirectional MIPI interface circuit based on FPGA universal interface | |
| CN108829931A (en) | A kind of BMC transceiver | |
| CN111431522B (en) | MIPI drive circuit capable of compatible output | |
| CN109644165A (en) | Drive circuit and its control method and transmitting/receiving system | |
| CN102281078B (en) | Difference receiver circuit for preventing input short circuiting | |
| CN206178797U (en) | MIPI interface circuit based on FPGATrue LVDS interface | |
| US9847777B2 (en) | Signal potential converter | |
| CN101520669B (en) | 300pin 10G optical module self-adaptive power | |
| CN102376288B (en) | Multi-modal transmission output circuit | |
| CN219436969U (en) | Optical module CML level and FPGA LVDS level matching circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |