CN106374905A - signal transmission circuit and communication device - Google Patents
signal transmission circuit and communication device Download PDFInfo
- Publication number
- CN106374905A CN106374905A CN201610753811.8A CN201610753811A CN106374905A CN 106374905 A CN106374905 A CN 106374905A CN 201610753811 A CN201610753811 A CN 201610753811A CN 106374905 A CN106374905 A CN 106374905A
- Authority
- CN
- China
- Prior art keywords
- terminal
- unit
- cpu
- differential
- fpga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dc Digital Transmission (AREA)
Abstract
The invention discloses a signal transmission circuit and communication equipment, wherein the signal transmission circuit comprises a first FPGA unit, a second FPGA unit, a first CPU unit and a second CPU unit; the first FPGA unit comprises a first differential port; the second FPGA unit comprises a second differential port; the first differential port is electrically connected with the second differential port; the first FPGA unit and the second FPGA unit respectively configure the first differential port and the second differential port into single-ended ports; and the first FPGA unit acquires the in-place state information of the first CPU unit, transmits the in-place state information to the second FPGA unit, and then transmits the in-place state information to the second CPU unit to finish in-place state detection. According to the technical scheme, the single-ended signals are transmitted through the differential circuit, and the number of signal transmission channels is increased.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a signal transmission circuit and a communication device.
Background
In a current signal transmission circuit based on an FPGA (Field Programmable Gate Array), a differential circuit and a single-ended circuit are respectively required for transmission, and the differential circuit and the single-ended circuit cannot be mixed with each other. Once the circuit is set, the signal can only be transmitted according to the specified requirements.
Referring to fig. 1, fig. 1 is a schematic diagram of a conventional differential transmission line, so that in an application scenario where port resources are relatively tight and only a simple single-ended signal needs to be transmitted, only a modified circuit can be re-planned, which is very inconvenient.
Disclosure of Invention
The invention mainly aims to provide a signal transmission circuit, which aims to transmit single-ended signals through a differential circuit and expand the number of signal transmission channels.
In order to achieve the above object, the present invention provides a signal transmission circuit, which includes a first FPGA unit, a second FPGA unit, a first CPU unit, and a second CPU unit; the first FPGA unit comprises a first differential port; the second FPGA unit comprises a second differential port; the first differential port is electrically connected with the second differential port;
the first FPGA unit configures a first differential port as a single-ended port; the second FPGA unit configures a second differential port as a single-ended port;
the first FPGA unit acquires in-place state information of the first CPU unit, transmits the in-place state information to the second FPGA unit and then transmits the in-place state information to the second CPU unit;
when the second CPU unit detects that the first CPU unit is in place, the second CPU unit is in standby; and when the second CPU unit detects that the first CPU unit is not in position, the second CPU unit works.
Preferably, the first differential port comprises a first terminal and a second terminal; the second differential port comprises a third terminal and a fourth terminal; the first terminal is electrically connected to the third terminal, and the second terminal is electrically connected to the fourth terminal; wherein,
and the first FPGA unit transmits the in-place state information to the second FPGA unit through the first terminal or the second terminal.
Preferably, the first FPGA unit includes a first CPU configuration module, a state waveform generation module, and a first difference module; the input end of the first CPU configuration module is connected with the output end of the first CPU unit, the output end of the first CPU configuration module is connected with the input end of the state waveform generation module, and the state waveform generation module is connected with the input end of the first difference module; the first output end of the first differential module is connected with the first terminal, and the second output end of the first differential module is connected with the second terminal.
Preferably, the second FPGA unit includes a second CPU configuration module, a state detection module, and a second difference module; the output end of the second CPU configuration module is connected with the input end of the second CPU unit, the input end of the second CPU configuration module is connected with the output end of the state detection module, and the input end of the state detection module is connected with the output end of the second differential module; the first input end of the second differential module is connected with the third terminal, and the second input end of the second differential module is connected with the fourth terminal.
Preferably, a first capacitor is connected between the first terminal and the third terminal, and a second capacitor is connected between the second terminal and the fourth terminal.
Preferably, the first FPGA unit further includes a first resistor and a power supply; when the first FPGA unit transmits in-place state information through a first terminal, the first FPGA unit configures a first resistor, wherein a first end of the first resistor is connected with the first terminal, and a second end of the first resistor is connected with the power supply;
when the first FPGA unit transmits the in-place state information through the second terminal, the first FPGA unit configures a first resistor, the first end of the first resistor is connected with the second terminal, and the second end of the first resistor is connected with the power supply.
Preferably, the first FPGA unit acquires in-place state information of the first CPU unit, converts the in-place state information into a pulse signal with a preset frequency and a preset duty ratio, transmits the pulse signal to the second FPGA unit, and then transmits the pulse signal to the second CPU unit.
Preferably, the frequency of the pulse signal is 1 KHZ.
Preferably, the duty cycle of the pulse signal is 1: 7.
The invention also provides communication equipment which comprises the signal transmission circuit, wherein the signal transmission circuit comprises a first FPGA unit, a second FPGA unit, a first CPU unit and a second CPU unit; the first FPGA unit comprises a first differential port; the second FPGA unit comprises a second differential port; the first differential port is electrically connected with the second differential port; the first FPGA unit configures a first differential port as a single-ended port; the second FPGA unit configures a second differential port as a single-ended port; the first FPGA unit acquires in-place state information of the first CPU unit, converts the in-place state information into a pulse signal, transmits the pulse signal to the second FPGA unit, and then transmits the pulse signal to the second CPU unit; when the second CPU unit detects that the first CPU unit is in place, the second CPU unit is in standby; and when the second CPU unit detects that the first CPU unit is not in position, the second CPU unit works.
According to the technical scheme, the signal transmission circuit is formed by arranging the first FPGA unit, the second FPGA unit, the first CPU unit and the second CPU unit. The first differential port is configured to be a single-ended port through the first FPGA unit, and the second differential port is configured to be a single-ended port through the second FPGA unit, so that one path of differential circuit is expanded to two paths of single-ended circuits, the sampling differential circuit is used for transmitting single-ended signals, the number of signal channels is increased, and the universality of the signal transmission circuit is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a conventional differential signal transmission circuit;
FIG. 2 is a functional block diagram of a signal transmission circuit according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a signal transmission circuit according to an embodiment of the present invention, in which a first terminal is used to transmit signals;
fig. 4 is a schematic structural diagram of a signal transmission circuit according to an embodiment of the invention, which uses a second terminal to transmit signals.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 100 | First FPGA unit | 230 | Second difference module |
| 110 | First CPU configuration module | 300 | A first CPU unit |
| 120 | State waveform generation module | 400 | Second CPU unit |
| 130 | First difference module | R1 | A first resistor |
| 200 | Second FPGA unit | C1 | First capacitor |
| 210 | Second CPU configuration module | C2 | Second capacitor |
| 220 | State detection module | VCC | Power supply |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides a signal transmission circuit.
Referring to fig. 2, in the embodiment of the present invention, the signal transmission circuit includes a first FPGA unit 100, a second FPGA unit 200, a first CPU unit 300, and a second CPU unit 400; the first FPGA cell 100 includes a first differential port; the second FPGA cell 200 includes a second differential port; the first differential port is electrically connected with the second differential port.
The first FPGA cell 100 configures a first differential port as a single-ended port; the second FPGA cell 200 configures the second differential port as a single-ended port; the first FPGA unit 100 acquires the in-place state information of the first CPU unit 300, transmits the in-place state information to the second FPGA unit 200, and then transmits the in-place state information to the second CPU unit 400; when the second CPU unit 400 detects that the first CPU unit 300 is in place, the second CPU unit 400 stands by; when the second CPU unit 400 detects that the first CPU unit 300 is not in place, the second CPU unit 400 operates.
It should be noted that, the present invention is a switch board based on MTCA (Multiple Terminal communication adapter) platform, and the switch board includes a main switch board and a standby switch board to improve the stability of the switch board. The main exchange board is connected with the standby exchange board through a differential circuit. Under normal conditions, the main exchange board works normally, the standby exchange board is in a standby state, and when the main exchange board is damaged, the standby exchange board is switched to work normally from the standby state, so that the MTCA platform can work continuously. When the main switch board works normally, the standby switch board needs to detect whether the main switch board is in place and the main/standby state, so as to judge whether the main switch board works normally.
In this embodiment, the first FPGA unit 100 and the first CPU unit 300 are disposed on the main board; the second FPGA unit 200 and the second CPU unit 400 are provided on the standby switch board. The first FPGA unit 100 obtains on-bit state information of the first CPU unit 300, converts the on-bit state information into a pulse signal, transmits the pulse signal to the second FPGA unit 200 through one channel in the differential circuit, and then transmits the pulse signal to the second CPU unit 400, thereby completing on-bit detection and active/standby state detection. It is easy to understand that programs are programmed in both the first FPGA unit 100 and the second FPGA unit 200, and the related ports are set by the programs, so as to transmit single-ended signals through the differential ports.
According to the technical scheme of the invention, a signal transmission circuit is formed by arranging a first FPGA unit 100, a second FPGA unit 200, a first CPU unit 300 and a second CPU unit 400. The first differential port is configured as a single-ended port by the first FPGA unit 100, and the second differential port is configured as a single-ended port by the second FPGA unit 200, so that one path of differential circuit is expanded into two paths of single-ended circuits, the sampling differential circuit is used for transmitting single-ended signals, the number of signal channels is increased, and the universality of the signal transmission circuit is improved.
Specifically, the first differential port (not labeled) includes a first terminal Vout1 and a second terminal Vout 2; the second differential port (not labeled) comprises a third terminal Vin1 and a fourth terminal Vin 2; the first terminal Vout1 is electrically connected with the third terminal Vin1, the second terminal Vout2 is electrically connected with the fourth terminal Vin 2; wherein,
the first FPGA cell 100 transmits on-bit status information to the second FPGA cell 200 through either the first terminal Vout1 or the second terminal Vout 2.
It should be noted that the first FPGA cell 100 and the second FPGA cell 200 configure the differential circuit into a single-ended circuit, and the pulse signal output by the first FPGA cell 100 is transmitted through the first terminal Vout1 or the second terminal Vout 2.
Specifically, the first FPGA unit 100 includes a first CPU configuration module 110, a state waveform generation module 120, and a first difference module 130; the input end of the first CPU configuration module 110 is connected to the output end of the first CPU unit 100, the output end of the first CPU configuration module 110 is connected to the input end of the state waveform generation module 120, and the state waveform generation module 120 is connected to the input end of the first difference module 130; the first output terminal of the first differential block 130 is connected to the first terminal Vout1, and the second output terminal of the first differential block 130 is connected to the second terminal Vout 2.
In this embodiment, the first FPGA unit 100 is implemented by using an FPGA chip and a corresponding peripheral circuit. The first CPU configuration module 110 is configured to configure an attribute of the first differential port, that is, configure the first differential port as a single-ended port, acquire in-place state information of the first CPU unit 100, and send a state instruction to the state waveform generation module 120 according to the in-place state information; the state waveform generating module 120 generates a pulse signal with a preset frequency and a preset duty ratio by multiplying the state command, and transmits the pulse signal to the second FPGA unit 200 through the port of the first difference module 130.
Specifically, the second FPGA unit 200 includes a second CPU configuration module 210, a state detection module 220, and a second difference module 230; the output end of the second CPU configuration module 210 is connected to the output end of the second CPU unit, the input end of the second CPU configuration module 210 is connected to the output end of the state detection module 220, and the input end of the state detection module 220 is connected to the output end of the second difference module 230; the first input terminal of the second differential block 230 is connected to the third terminal Vin1, and the second input terminal of the second differential block 230 is connected to the fourth terminal Vin 2.
Similarly, the second FPGA unit 200 is implemented by using an FPGA chip and a corresponding peripheral circuit. The second difference module 230 receives the input pulse signal, and the state detection module 220 analyzes the pulse signal to obtain the in-place state information of the first CPU unit and output the information to the second CPU configuration module; the second CPU configuration module 210 is configured to configure the attribute of the second differential port, that is, configure the second differential port as a single-ended port, and report the in-place state information of the first CPU unit 100 to the second CPU unit 200.
Further, a first capacitor C1 is connected between the first terminal Vout1 and the third terminal Vin1, and a second capacitor C2 is connected between the second terminal Vout2 and the fourth terminal Vin 2.
In addition, in order to electrically isolate the main switching board from the standby switching board, the first capacitor C1 and the second capacitor C2 are correspondingly arranged, so that the differential port is effectively prevented from being damaged when the main switching board and the standby switching board are plugged in a live manner.
Referring to fig. 3 and 4, further, the first FPGA unit 100 further includes a first resistor R1 and a power source VCC; when the first FPGA cell 100 transmits bit status information through the first terminal Vout1, the first FPGA cell 100 configures a first resistor R1, a first terminal of the first resistor R1 is connected to the first terminal Vout1, and a second terminal of the first resistor R1 is connected to the power VCC;
when the first FPGA cell 100 transmits bit status information through the second terminal Vout2, the first FPGA cell 100 configures a first resistor R1, a first end of the first resistor R1 is connected to the second terminal Vout2, and a second end of the first resistor R1 is connected to the power VCC.
In this embodiment, the first resistor is pre-configured by a program burned in the FPGA chip, the first CPU configuration module controls generation and transmission of a state waveform, and the second CPU configuration module obtains a state of the opposite terminal through the state waveform. The first differential block 130 includes a first resistor R1, a power source VCC, and a tri-state gate, and the second differential block 230 includes an input buffer.
It should be noted that, in practical application, the circuit inside the FPGA chip is already configured in the single-ended mode, the circuit outside the FPGA chip is not changed, but the circuit configuration inside the chip is changed. When the first terminal is adopted to transmit signals, the first resistor is configured as a pull-up resistor of a single-ended circuit where the first terminal and the third terminal are located inside the chip. If the second terminal is adopted to transmit signals, the first resistor is configured as a pull-up resistor of a single-ended line where the second terminal and the fourth terminal are located inside the chip.
Further, the first FPGA unit 100 acquires the in-place state information of the first CPU unit 300, converts the in-place state information into a pulse signal with a preset frequency and a preset duty ratio, transmits the pulse signal to the second FPGA unit 200, and then transmits the pulse signal to the second CPU unit 400.
In this embodiment, the duty ratio of the pulse signal is 1:7, and the frequency of the pulse signal is 1 KHZ.
It should be noted that, in order to utilize the isolation characteristic of the differential circuit, the differential capacitors (i.e., the first capacitor C1 and the second capacitor C2) are still retained, but the direct transmission of the dc signal by using such a differential circuit would result in signal failure, and the direct transmission of the clock signal with a single-ended 50% duty cycle would cause distortion of the signal at the receiving end under the charging and discharging effects of the capacitors, and at the same time, would cause the signal voltage to shift down, so that the negative voltage occurs and the receiving end port is damaged.
The method can realize the distortion-free transmission of clock signals by adjusting the frequency and the duty ratio of transmitted waveforms and matching with an isolation capacitor with a specific capacitance value, and can not cause the downward shift of signal voltage, the capacitor used in the embodiment is 10nf (nano method), the frequency of the waveforms generated by the FPGA chip is 1KHZ, the duty ratio of the signals is 1:7, and the distortion-free transmission of the signals is realized.
The invention uses the existing differential line to transmit single-ended signals; the transmission of a single-ended clock signal on a differential circuit is realized by using a method for changing clock frequency and duty ratio; the electric isolation of single-ended signals between the board cards is realized by using differential capacitors of the differential circuit; the FPGA is utilized to conveniently realize the switching from the existing differential mode to the single-ended mode without changing the circuit.
The present invention further provides a communication device, which includes a signal transmission circuit, and the specific structure of the signal transmission circuit refers to the foregoing embodiments, and since the communication device adopts all technical solutions of all the foregoing embodiments, the communication device at least has all beneficial effects brought by the technical solutions of the foregoing embodiments, and details are not repeated herein.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A signal transmission circuit is characterized by comprising a first FPGA unit, a second FPGA unit, a first CPU unit and a second CPU unit; the first FPGA unit comprises a first differential port; the second FPGA unit comprises a second differential port; the first differential port is electrically connected with the second differential port;
the first FPGA unit configures a first differential port as a single-ended port; the second FPGA unit configures a second differential port as a single-ended port;
the first FPGA unit acquires in-place state information of the first CPU unit, transmits the in-place state information to the second FPGA unit and then transmits the in-place state information to the second CPU unit;
when the second CPU unit detects that the first CPU unit is in place, the second CPU unit is in standby; and when the second CPU unit detects that the first CPU unit is not in position, the second CPU unit works.
2. The signal transmission circuit of claim 1, wherein the first differential port comprises a first terminal and a second terminal; the second differential port comprises a third terminal and a fourth terminal; the first terminal is electrically connected to the third terminal, and the second terminal is electrically connected to the fourth terminal; wherein,
and the first FPGA unit transmits the in-place state information to the second FPGA unit through the first terminal or the second terminal.
3. The signal transmission circuit of claim 2, wherein the first FPGA unit includes a first CPU configuration module, a state waveform generation module, and a first difference module; the input end of the CPU configuration module is connected with the output end of the first CPU unit, the output end of the first CPU configuration module is connected with the input end of the state waveform generation module, and the state waveform generation module is connected with the input end of the first differential module; the first output end of the first differential module is connected with the first terminal, and the second output end of the first differential module is connected with the second terminal.
4. The signal transmission circuit of claim 2, wherein the second FPGA unit includes a second CPU configuration module, a state detection module, and a second difference module; the output end of the second CPU configuration module is connected with the input end of the second CPU unit, the input end of the second CPU configuration module is connected with the output end of the state detection module, and the input end of the state detection module is connected with the output end of the second differential module; the first input end of the second differential module is connected with the third terminal, and the second input end of the second differential module is connected with the fourth terminal.
5. The signal transmission circuit according to any one of claims 2 to 4, wherein a first capacitor is connected between the first terminal and the third terminal, and a second capacitor is connected between the second terminal and the fourth terminal.
6. The signal transmission circuit of claim 5, wherein the first FPGA unit further comprises a first resistor and a power supply; when the first FPGA unit transmits in-place state information through a first terminal, the first FPGA unit configures a first resistor, wherein a first end of the first resistor is connected with the first terminal, and a second end of the first resistor is connected with the power supply;
when the first FPGA unit transmits the in-place state information through the second terminal, the first FPGA unit configures a first resistor, the first end of the first resistor is connected with the second terminal, and the second end of the first resistor is connected with the power supply.
7. The signal transmission circuit according to claim 6, wherein the first FPGA unit obtains on-site state information of the first CPU unit, converts the on-site state information into a pulse signal with a preset frequency and a preset duty ratio, transmits the pulse signal to the second FPGA unit, and then transmits the pulse signal to the second CPU unit.
8. The signal transmission circuit according to claim 7, wherein the frequency of the pulse signal is 1 KHZ.
9. The signal transmission circuit according to claim 7, wherein a duty ratio of the pulse signal is 1: 7.
10. A communication device, characterized in that it comprises a signal transmission circuit according to any one of claims 1-9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610753811.8A CN106374905B (en) | 2016-08-29 | 2016-08-29 | signal transmission circuit and communication device |
| PCT/CN2016/097770 WO2018040049A1 (en) | 2016-08-29 | 2016-09-01 | Signal transmission circuitand communication device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610753811.8A CN106374905B (en) | 2016-08-29 | 2016-08-29 | signal transmission circuit and communication device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106374905A true CN106374905A (en) | 2017-02-01 |
| CN106374905B CN106374905B (en) | 2019-05-28 |
Family
ID=57904021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610753811.8A Active CN106374905B (en) | 2016-08-29 | 2016-08-29 | signal transmission circuit and communication device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106374905B (en) |
| WO (1) | WO2018040049A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117155372A (en) * | 2023-09-06 | 2023-12-01 | 苏州异格技术有限公司 | Input/output driver structure, input/output control method and communication system |
| TWI842324B (en) * | 2022-06-01 | 2024-05-11 | 大陸商長鑫存儲技術有限公司 | Receiving circuit and memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201075866Y (en) * | 2007-09-28 | 2008-06-18 | 华为技术有限公司 | Signal multiplexing transmission system |
| US20080303554A1 (en) * | 2007-06-07 | 2008-12-11 | International Business Machines Corporation | Structure for a configurable low power high fan-in multiplexer |
| CN103378846A (en) * | 2012-04-20 | 2013-10-30 | 中国科学院电子学研究所 | Device for converting logic signal into low voltage differential signal |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2681799A (en) * | 1998-04-17 | 1999-11-08 | Conexant Systems, Inc. | Low cost line-based video compression of digital video stream data |
| CN203786723U (en) * | 2014-04-18 | 2014-08-20 | 北京盛博协同科技有限责任公司 | Dual redundant system based on X86 PC/104 embedded CPU modules |
-
2016
- 2016-08-29 CN CN201610753811.8A patent/CN106374905B/en active Active
- 2016-09-01 WO PCT/CN2016/097770 patent/WO2018040049A1/en not_active Ceased
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080303554A1 (en) * | 2007-06-07 | 2008-12-11 | International Business Machines Corporation | Structure for a configurable low power high fan-in multiplexer |
| CN201075866Y (en) * | 2007-09-28 | 2008-06-18 | 华为技术有限公司 | Signal multiplexing transmission system |
| CN103378846A (en) * | 2012-04-20 | 2013-10-30 | 中国科学院电子学研究所 | Device for converting logic signal into low voltage differential signal |
Non-Patent Citations (1)
| Title |
|---|
| 谭宇等: "基于FPGA主备倒换的电路设计与实现", 《电视技术》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI842324B (en) * | 2022-06-01 | 2024-05-11 | 大陸商長鑫存儲技術有限公司 | Receiving circuit and memory |
| CN117155372A (en) * | 2023-09-06 | 2023-12-01 | 苏州异格技术有限公司 | Input/output driver structure, input/output control method and communication system |
| CN117155372B (en) * | 2023-09-06 | 2024-02-06 | 苏州异格技术有限公司 | Input/output driver structure, input/output control method and communication system |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2018040049A1 (en) | 2018-03-08 |
| CN106374905B (en) | 2019-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111711442A (en) | Interface circuit and method for operating an interface circuit | |
| WO2017173889A1 (en) | Communication interface hardware self-adaptive multiplexing device and method | |
| CN107395243A (en) | A kind of single-wire communication circuit | |
| CN106374905B (en) | signal transmission circuit and communication device | |
| CN213210263U (en) | Oscilloscope probe switching device | |
| US20160149492A1 (en) | Voltage adjusting apparatus | |
| CN101800821A (en) | Medical communication calling equipment | |
| CN211577382U (en) | Short circuit detection device and charging equipment | |
| CN103904743B (en) | A kind of parasitic method of supplying power to and structure thereof | |
| CN208820756U (en) | A kind of RS485 communication isolation circuit | |
| CN203911885U (en) | Biasing resistor controllable type 485 communication circuit | |
| CN105760331A (en) | Transmitter applied to USB-PD communication | |
| CN216599614U (en) | Bidirectional rapid transmission isolation circuit | |
| CN103424598B (en) | Inversion system output voltage detecting circuit and inversion system | |
| CN103118143A (en) | Multiplex circuit of serial interface and Ethernet interface | |
| CN210518267U (en) | Low-rate level conversion circuit | |
| CN105553504A (en) | Isolated transceiver module and manufacturing method thereof | |
| CN101008696B (en) | Circuit arrangement for galvanically isolated signal lines | |
| CN106340915A (en) | Terminal equipment | |
| CN206251103U (en) | A kind of signal protection circuit and device | |
| CN202586965U (en) | Charge pump and transmitting device employing charge pump | |
| CN207367195U (en) | A kind of IIC interface expansion boards | |
| CN207427093U (en) | A kind of notch diplexer | |
| CN205486082U (en) | Be applied to ware that sends in USB -PD communication | |
| CN112887179B (en) | Single-wire communication circuit with protection function |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP02 | Change in the address of a patent holder | ||
| CP02 | Change in the address of a patent holder |
Address after: 518000 2101, No. 100, Zhihe Road, Dakang community, Yuanshan street, Longgang District, Shenzhen, Guangdong Patentee after: BANGYAN TECHNOLOGY Co.,Ltd. Address before: 518000 room 901, block B, building 5, Shenzhen software industry base, Nanshan District, Shenzhen City, Guangdong Province Patentee before: BANGYAN TECHNOLOGY Co.,Ltd. |