CN206178797U - MIPI interface circuit based on FPGATrue LVDS interface - Google Patents
MIPI interface circuit based on FPGATrue LVDS interface Download PDFInfo
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- CN206178797U CN206178797U CN201620925028.0U CN201620925028U CN206178797U CN 206178797 U CN206178797 U CN 206178797U CN 201620925028 U CN201620925028 U CN 201620925028U CN 206178797 U CN206178797 U CN 206178797U
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Abstract
The utility model relates to a MIPI interface circuit based on FPGATrue LVDS interface, including FPGA chip, MIPI interface receiving equipment, connect the HS_O_P high -speed signal of true LVDS interface and the LP_O_P low -speed signal of LVCMOS12 interface, 50 omega of resistance R1 resistance scope~150 omega through resistance R1, connect the HS_O_N high -speed signal of true LVDS interface and the LP_O_N low -speed signal of LVCMOS12 interface, 50 omega of resistance R2 resistance scope~150 omega through resistance R2. The utility model discloses a FPGA and the MIPI interface receiving equipment high -efficient data transmission of transmission path has within a definite time been realized to the optimal design of trueLVDS interface, LVCMOS12 interface and peripheral resistance, has characteristics such as signal integrality is good, transmission rate is high, the consumption is little, resistance is small in quantity.
Description
Technical field
This utility model is related to a kind of MIPI interface circuits, more particularly to a kind of based on FPGA True LVDS interfaces
MIPI interface circuits, belong to the technical field of the interface of MIPI agreements and the combination of FPGA.
Background technology
MIPI interfaces are the open standards formulated for Mobile solution processor and specification that MIPI alliances initiate, and are current masters
The high speed image transmission means of stream, in virtual implementing helmet, unmanned plane, smart mobile phone, panel computer, video camera, wearable
The fields such as equipment, man machine interface (HMI) are widely applied.
Early stage realize that MIPI interface bridging functionalitys rely primarily on asic chip, with FPGA technology continuous development and enter
Step, the bridging chip of MIPI interfaces is progressively replaced by FPGA.
Table 1 puts flow standard for the output of MIPI interfaces：
Table 1
| Parameter | Description | It is minimum | Typical case | It is maximum | Unit |
| VCMTX | HS sends common-mode voltage | 150 | 200 | 250 | mV |
| VOD | HS sends differential voltage | 140 | 200 | 270 | mV |
| |△VOD| | HS two paths of differential signals deviations | - | - | 14 | mV |
| ZOS | Single-ended output impedance | 40 | 50 | 62.5 | Ω |
| |△ZOS| | Single-ended output impedance deviation | - | - | 10 | % |
Fig. 1 is MIPI interface level technical specification schematic diagrams, it will be noted from fig. 1 that common-mode voltage typical case during HS patterns
, in 200mV, differential swings representative value is in 200mV for value；Signal level amplitude 1.2V during LP patterns.
The output of MIPI interfaces has two kinds of mode of operations, in high speed mode (HS), and output is gone out in the form of small size difference
It is existing.Under low-power consumption mode (LP), output becomes LVCMOS1.2V standards, occurs in the form of two Single-end outputs.It is such
IO design comparisons are complicated.
FPGA (Field-Programmable Gate Array), i.e. field programmable gate array, it be PAL,
The product further developed on the basis of the programming devices such as GAL, CPLD.It is as in special IC (ASIC) field
A kind of semi-custom circuit and occur, both solved the deficiency of custom circuit, original programming device gate circuit is overcome again
The limited shortcoming of number.
The characteristics of someone utilizes the programmable I/O of FPGA, the difference output and two LVCMOS1.2V outputs with FPGA, profit
With the outer resistor voltage divider network of piece, the output solution of MIPI is realized.As shown in Figure 2.Fig. 2 is MIPI interfaces in prior art
The circuit diagram of circuit.In Fig. 2, using LVDS25E interfaces, by connecting voltage-splitter resistance net between LVDS25E interfaces and LVCMOS12
Network is realized being matched with the port identity of MIPI interfaces.The program due to sealing in 330 Ω resistances at HS ends, work(when causing high-speed transfer
Consumption is increased, and transfer rate is limited, and clock rate is only capable of reaching 400MHz or so；Another has the disadvantage every road differential signal needs
Two more than this utility model, five road MIPI differential signals will have more ten resistance to resistance quantity, place empty to consumer devices
Between also result in no small pressure.
LVDS, i.e. LowVoltageDifferentialSignaling, are a kind of technology of Low Voltage Differential Signaling interfaces.It
It is U.S. NS companies (National Semiconductor) to overcome power consumption when transmitting broadband high code rate data in Transistor-Transistor Logic level mode
Greatly, the shortcomings of EMI electromagnetic interference is big and a kind of digital signal transmission mode for developing.
LVDS output interface is using low-down voltage swing (about 350mV) in two PCB traces or a pair of balanced cables
On the transmission of data, i.e. low-voltage differential signal transmission are carried out by difference.Using LVDS output interface, signal can be caused poor
With the speed rates of hundreds of Mbit/s on point PCB lines or balanced cable, due to using low pressure and low current type of drive, therefore,
Realize low noise and low-power consumption.At present, LVDS output interface has obtained widely should in 17in and above liquid crystal display
With.
How based on a kind of signal integrity of True LVDS interface standard implementations is good, transfer rate is high, small power consumption circuit
Become technical problem urgently to be resolved hurrily.
The content of the invention
For existing FPGA and the deficiency of the transtation mission circuit of MIPI interface equipment rooms, this utility model provides one kind
MIPI interface circuits based on FPGA True LVDS interfaces；
MIPI physical layers support HS (High Speed) and two kinds of mode of operations of LP (Low Power).Under HS patterns, adopt
Low Voltage Differential Signal, 140~270mV of differential amplitude, static common-mode voltage 150mV~250mV, data rate be 80Mbps~
1Gbps.Under LP patterns, using single-ended signal, signal amplitude 1.2V, data rate is less than 10Mbps.
The static common-mode voltage about 1.2V of True LVDS interfaces output, differential amplitude is in 400mV or so.In order to realize FPGA
With the Interface Matching of MIPI equipment room transmission paths, this utility model combine True LVDS and LVCMOS12 interface features, pass through
Resistance is sealed between True LVDS interfaces and LVCMOS12 interfaces and realizes matching for MIPI interfaces amplitude and common-mode voltage.By excellent
Change the MIPI data transfers that resistance is capable of achieving under various high speeds.
The technical solution of the utility model is：
A kind of MIPI interface circuits based on FPGA True LVDS interfaces, including fpga chip, MIPI interfaces set
It is standby, it is divided into HS_O_P during the I/O that MIPI_O_P difference positive signal reception signal is sent in the fpga chip and believes at a high speed
Number and LP_O_P low speed signals；When MIPI_O_N difference positive signal reception signal is sent to the I/O in the fpga chip
It is divided into HS_O_N high speed signals and LP_O_N low speed signals；
Connect the HS_O_P high speed signals of True LVDS interfaces and the LP_O_P low speed of LVCMOS12 interfaces by resistance R1
Signal, Ω~150 Ω of resistance R1 Standard resistance ranges 50；Resistance can be matched according to the impedance of actual PCB lines.
Connect the HS_O_N high speed signals of True LVDS interfaces and the LP_O_N low speed of LVCMOS12 interfaces by resistance R2
Signal, Ω~150 Ω of resistance R2 Standard resistance ranges 50.Resistance can be matched according to the impedance of actual PCB lines.
When HS patterns are enabled, True LVDS drive signal lines, now LVCMOS12 interfaces be output as 0；LP patterns are enabled
When, LVCMOS12 drive signal lines, now True LVDS are high-impedance state.
Resistance R1, resistance R2 play terminal resistance effect simultaneously, keep signal integrity, resistance R1, resistance R2 positions to use up
May be near the input pin of MIPI interface equipment；
It is further preferred that Ω~110 Ω of resistance R1 Standard resistance ranges 90, Ω~110 Ω of resistance R2 Standard resistance ranges 90.With reality
The high speed of existing MIPI interface circuits, stable transmission.Differential signal line needs isometric process.
It is particularly preferred, clock rate 500MHz is transmitted, resistance R1 resistances are 100 Ω, and resistance R2 resistances are 100 Ω.
The operation method of the above-mentioned MIPI interface circuits based on FPGA True LVDS interfaces, concrete steps include：
LP_O_P low speed signals with HS_O_P high speed signals and are MIPI_O_P signals after resistance R1, are connected to MIPI
Interface equipment, LP_O_N low speed signals with HS_O_N high speed signals and are MIPI_O_N signals after resistance R2, are connected
To MIPI interface equipment.
The beneficial effects of the utility model are：
This utility model adopts FPGA solutions, gives full play to its abundant I/O level resource and I/O interface capabilities,
By True LVDS interfaces, LVCMOS12 interfaces and the optimization design of peripheral resistance, realize FPGA and MIPI interfaces and set
The efficient data transfer of transmission path between standby, with signal integrity is good, the spy such as transfer rate is high, small power consumption, resistance quantity are few
Point, transmission clock rate can reach 900MHz, improve more than 1 times than existing scheme；Due to no resistance on HS paths, so comparing
Existing scheme power consumption is substantially reduced；Resistor network adopts two resistance, compares four resistance of existing scheme, reduces half.
There is versatility and portability simultaneously.
Description of the drawings
Fig. 1 is MIPI interface level technical specification schematic diagrams.
Fig. 2 is the circuit diagram of MIPI interface circuits in prior art.
Fig. 3 is circuit diagram of this utility model based on the MIPI interface circuits of FPGA True LVDS interfaces.
Specific embodiment
This utility model is further qualified with reference to Figure of description and embodiment, but not limited to this.
Embodiment 1
A kind of MIPI interface circuits based on FPGA True LVDS interfaces, as shown in figure 3, including fpga chip, MIPI
Interface equipment, during the I/O that MIPI_O_P difference positive signal reception signal is sent in the fpga chip HS_ is divided into
O_P high speed signals and LP_O_P low speed signals；MIPI_O_N difference positive signal receives signal and is sent to the fpga chip
In I/O when be divided into HS_O_N high speed signals and LP_O_N low speed signals；
Connect the HS_O_P high speed signals of True LVDS interfaces and the LP_O_P low speed of LVCMOS12 interfaces by resistance R1
Signal, Ω~150 Ω of resistance R1 Standard resistance ranges 50；Resistance can be matched according to the impedance of actual PCB lines.
Connect the HS_O_N high speed signals of True LVDS interfaces and the LP_O_N low speed of LVCMOS12 interfaces by resistance R2
Signal, Ω~150 Ω of resistance R2 Standard resistance ranges 50.Resistance can be matched according to the impedance of actual PCB lines.
Resistance R1, resistance R2 play terminal resistance effect simultaneously, keep signal integrity, resistance R1, resistance R2 positions to use up
May be near the input pin of MIPI interface equipment；
Embodiment 2
A kind of MIPI interface circuits based on FPGA True LVDS interfaces according to embodiment 1, its difference is,
Ω~110 Ω of resistance R1 Standard resistance ranges 90, Ω~110 Ω of resistance R2 Standard resistance ranges 90.With realize MIPI interface circuits high speed,
Stable transmission.Differential signal line needs isometric process.
Embodiment 3
A kind of MIPI interface circuits based on FPGA True LVDS interfaces according to embodiment 1, its difference is,
Transmission clock rate 500MHz, resistance R1 resistances are 100 Ω, and resistance R2 resistances are 100 Ω.
Claims (3)
1. a kind of MIPI interface circuits based on FPGA True LVDS interfaces, it is characterised in that connect including fpga chip, MIPI
Mouth receiving device, during the I/O that MIPI_O_P difference positive signal reception signal is sent in the fpga chip HS_O_ is divided into
P high speed signals and LP_O_P low speed signals；MIPI_O_N difference positive signal receives signal and is sent in the fpga chip
I/O when be divided into HS_O_N high speed signals and LP_O_N low speed signals；
Connect the HS_O_P high speed signals of True LVDS interfaces and the LP_O_P low speed letter of LVCMOS12 interfaces by resistance R1
Number, Ω~150 Ω of resistance R1 Standard resistance ranges 50；
Connect the HS_O_N high speed signals of True LVDS interfaces and the LP_O_N low speed letter of LVCMOS12 interfaces by resistance R2
Number, Ω~150 Ω of resistance R2 Standard resistance ranges 50.
2. a kind of MIPI interface circuits based on FPGA True LVDS interfaces according to claim 1, it is characterised in that
Ω~110 Ω of resistance R1 Standard resistance ranges 90, Ω~110 Ω of resistance R2 Standard resistance ranges 90.
3. a kind of MIPI interface circuits based on FPGA True LVDS interfaces according to claim 1, it is characterised in that
Transmission clock rate 500MHz, resistance R1 resistances are 100 Ω, and resistance R2 resistances are 100 Ω.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620925028.0U CN206178797U (en) | 2016-08-23 | 2016-08-23 | MIPI interface circuit based on FPGATrue LVDS interface |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620925028.0U CN206178797U (en) | 2016-08-23 | 2016-08-23 | MIPI interface circuit based on FPGATrue LVDS interface |
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| CN206178797U true CN206178797U (en) | 2017-05-17 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106250342A (en) * | 2016-08-23 | 2016-12-21 | 广东高云半导体科技股份有限公司 | A kind of MIPI interface circuit based on FPGA True LVDS interface and operation method thereof |
-
2016
- 2016-08-23 CN CN201620925028.0U patent/CN206178797U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106250342A (en) * | 2016-08-23 | 2016-12-21 | 广东高云半导体科技股份有限公司 | A kind of MIPI interface circuit based on FPGA True LVDS interface and operation method thereof |
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Address after: 510000 room 1001, science Avenue, Whampoa District, Guangzhou, Guangdong, 1001 Patentee after: Guangdong high cloud semiconductor technologies limited company Address before: 528303 13 building, Dongying business building, 16 Rong Qi Avenue, Shunde, Foshan, Guangdong. Patentee before: Guangdong high cloud semiconductor technologies limited company |
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