CN103605627A - One-wire full-duplex bus - Google Patents
One-wire full-duplex bus Download PDFInfo
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- CN103605627A CN103605627A CN201310640143.4A CN201310640143A CN103605627A CN 103605627 A CN103605627 A CN 103605627A CN 201310640143 A CN201310640143 A CN 201310640143A CN 103605627 A CN103605627 A CN 103605627A
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Abstract
The invention relates to a full-duplex bus, in particular to a one-wire full-duplex bus. The one-wire full-duplex bus is composed of an interface circuit A and an interface circuit B. A port P1 of the interface circuit A is connected with a port P2 of the interface circuit B. The interface circuit A is composed of an output circuit buffer A, an output driving circuit A, an input circuit A, an input circuit buffer A and a clock generating circuit A. The interface circuit B is composed of an output circuit buffer B, an output driving circuit B, an input circuit B, an input circuit buffer B and a clock generating circuit B. The one-wire full-duplex bus has the advantages that the one-wire full-duplex bus is a solution with minimum full-duplex bus connection between semiconductor chips and has a positive meaning in saving of pins of the chips.
Description
Technical field
The present invention relates to a kind of full duplex bus, particularly relate to a kind of bus of single line full duplex.
Background technology
Between semi-conductor chip, conventional bus comprises I2C bus, spi bus, UART bus etc. at present.These buses all have ，Mou aspect, application scenario separately to have significant advantage.I2C bus is comprised of SDA and two lines of SCL, and its advantage is that circuit is simple, and a main control end can connect maximum 127 equipment, is applicable to very much the situation that a plurality of equipment shares one group of bus.SPI is become by CS/CLK/DIN/DOUT quad, and advantage is that speed is high, can realize two-way data transmission.UART bus is comprised of TX/RX two lines, can realize full-duplex communication.
No matter be duplex or half-duplex transmission, a common trait of current all buses is at least 2 lines, to consist of.
The present invention proposes a kind of bus, is realized the communication of full duplex by a line.Only it is advantageous that and connect and just can realize full-duplex communication with single line.
Summary of the invention
The bus that the object of this invention is to provide a kind of single line full duplex, for the full-duplex communication between semi-conductor chip provides a kind of line solution still less.
The present invention adopts following scheme to realize:
A bus for single line full duplex, it is comprised of interface circuit A and interface circuit B, and wherein the port P1 of interface circuit A and the port P2 of interface circuit B are connected to each other.
Described interface circuit A is comprised of following part: output circuit impact damper A, output driving circuit A, input circuit A, input circuit impact damper A and clock generating circuit A, wherein, output circuit impact damper A is connected with output driving circuit A, input circuit A is connected with input circuit impact damper A, clock generating circuit A is connected with output circuit impact damper A, output driving circuit A, input circuit A simultaneously, and output driving circuit A and input circuit A are all connected to port P1.
Described output circuit impact damper A, the data that will export send to output driving circuit A input end by turn.
Described output driving circuit A, by power supply VCC, two resistance R 1, R2 and one group of push-pull circuit that formed by P type metal-oxide-semiconductor and N-type metal-oxide-semiconductor, formed, wherein, P type metal-oxide-semiconductor is connected with power supply VCC by resistance R 1, N-type metal-oxide-semiconductor is connected with GND by resistance R 2, the output terminal of this push-pull circuit is connected with the port P1 of interface A, and the resistance value of R2 equals 2 times of R1 resistance value.
The ADC(analog-digital converter that described input circuit A is 2-bit by resolution) form, this ADC is powered by power supply VCC.
Described clock generating circuit A, produces clock and exports input circuit impact damper A, output circuit impact damper A and input circuit A to.
Described interface circuit B is comprised of following part: output circuit impact damper B, output driving circuit B, input circuit B, input circuit impact damper B and clock generating circuit B, wherein, output circuit impact damper B is connected with output driving circuit B, and input circuit B is connected with input circuit impact damper B, clock generating circuit B is connected with output circuit impact damper B, output driving circuit B, input circuit B simultaneously, and output driving circuit B and input circuit B are all connected to port P2.
Described output circuit impact damper B, the data that will export send to output driving circuit B input end by turn.
Described output driving circuit B, by power supply VCC, two resistance R 3, R4 and one group of push-pull circuit that are comprised of P type metal-oxide-semiconductor and N-type metal-oxide-semiconductor form, wherein, P type metal-oxide-semiconductor is connected with power supply VCC by resistance R 3, N-type metal-oxide-semiconductor is connected with GND by resistance R 4, and the output terminal of this push-pull circuit is connected with the port P2 of interface B, and the resistance value of R3 equals 2 times of R4 resistance value.
Described input circuit B, the ADC that is 2-bit by resolution forms, and this ADC is powered by power supply VCC.
Described clock generating circuit B, produces clock and exports input circuit impact damper B, output circuit impact damper B and input circuit B to.
In described interface circuit B and interface circuit A, the resistance value that the resistance value of R3 equals R1 equals 2 times of R4 resistance value.
Positive progressive effect of the present invention is: the invention provides a kind of full duplex bus of single line, is that between semi-conductor chip, full duplex bus connects minimum solution, to saving the pin of chip, has positive meaning.
Accompanying drawing explanation
Fig. 1 is circuit structure schematic diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, further technical scheme of the present invention is illustrated.
In Fig. 1, interface circuit A is by output circuit impact damper A (100), output driving circuit A (102), and input circuit A (103), input circuit impact damper A (101), clock generating circuit A (104) form.
Wherein, output driving circuit A is comprised of power supply VCC, resistance R 1, R2, P-MOS pipe S1, N-MOS pipe S2.Here, the resistance of R1 is 100ohm, and the resistance of R2 is 200ohm.
Interface circuit B consists of output circuit impact damper B (200), output driving circuit B (202), input circuit B (203), input circuit impact damper B (201), clock generating circuit B (204).
Wherein, output driving circuit B is comprised of power supply VCC, resistance R 3, R4, P-MOS pipe S3, N-MOS pipe S4.Here, the resistance of R3 is 100ohm, and the resistance of R4 is 50ohm.
The clock generating circuit of interface circuit A and interface circuit B produces the clock of same frequency.The transfer rate of interface circuit A and interface circuit B is set as consistent.
Principle of work of the present invention is as follows:
When interface circuit A output logic level " 1 ", during interface circuit B output logic level " 1 ", now interface circuit A enables S1, and interface circuit B enables S3, and now the level in bus is VCC.The ADC output of the input circuit at two ends is logic " 11 ".
When interface circuit A output logic level " 0 ", during interface circuit B output logic level " 1 ", now interface circuit A enables S2, interface circuit B enables S3, and now the level in bus is: VCC*R2/ (R2+R3)=2/3 VCC. now output valve of the input circuit ADC of interface is logic " 10 ".
When interface circuit A output logic level " 1 ", during interface circuit B output logic level " 0 ", now interface circuit A enables S1, interface circuit B enables S4, and now the level in bus is: VCC*R4/ (R1+R4)=1/3 VCC. now output valve of the input circuit ADC of interface is logic " 01 ".
When interface circuit A output logic level " 0 ", during interface circuit B output logic level " 0 ", now interface circuit A enables S2, and interface circuit B enables S4, now the level in bus be 0V. now the output valve of the input circuit ADC of interface be logic " 00 ".
By foregoing description, can be known, the output driver module of interface circuit A and interface circuit B can drive bus simultaneously.After the input circuit of interface circuit A and interface circuit B quantizes bus level by ADC, can obtain the output valve of the other side's driving circuit.Corresponding relation is as follows: (" 0 " and " 1 " is digital circuit logic output herein)
Although more than described the specific embodiment of the present invention; but it will be understood by those of skill in the art that these only illustrate, do not deviating under the prerequisite of the present invention's essence and principle; embodiment is made to various changes or modifications, should think and belong to protection scope of the present invention.
Claims (10)
1. a bus for single line full duplex, is characterized in that it is comprised of interface circuit A and interface circuit B, and the port P1 of interface circuit A and the port P2 of interface circuit B are connected to each other; Described interface circuit A is comprised of following part: output circuit impact damper A, output driving circuit A, input circuit A, input circuit impact damper A and clock generating circuit A, wherein, output circuit impact damper A is connected with output driving circuit A, input circuit A is connected with input circuit impact damper A, clock generating circuit A is connected with output circuit impact damper A, output driving circuit A, input circuit A simultaneously, and output driving circuit A and input circuit A are all connected to port P1; Described interface circuit B is comprised of following part: output circuit impact damper B, output driving circuit B, input circuit B, input circuit impact damper B and clock generating circuit B, wherein output circuit impact damper B is connected with output driving circuit B, input circuit B is connected with input circuit impact damper B, and clock generating circuit B is connected with output circuit impact damper B, output driving circuit B, input circuit B simultaneously, and output driving circuit B and input circuit B are all connected to port P2.
2. the bus of a kind of single line full duplex according to claim 1, is characterized in that described output circuit impact damper A, and the data that will export send to output driving circuit A input end by turn.
3. the bus of a kind of single line full duplex according to claim 1, it is characterized in that described output driving circuit A, by power supply VCC, two resistance R 1, R2 and one group of push-pull circuit that formed by P type metal-oxide-semiconductor and N-type metal-oxide-semiconductor, formed, wherein P type metal-oxide-semiconductor is connected with power supply VCC by resistance R 1, N-type metal-oxide-semiconductor is connected with GND by resistance R 2, the output terminal of this push-pull circuit is connected with the port P1 of interface A, and the resistance value of R2 equals 2 times of R1 resistance value.
4. the bus of a kind of single line full duplex according to claim 1, is characterized in that described input circuit A, and the ADC that is 2-bit by resolution forms, and this ADC is powered by power supply VCC.
5. the bus of a kind of single line full duplex according to claim 1, is characterized in that described clock generating circuit A, produces clock and exports input circuit impact damper A, output circuit impact damper A and input circuit A to.
6. the bus of a kind of single line full duplex according to claim 1, is characterized in that described output circuit impact damper B, and the data that will export send to output driving circuit B input end by turn.
7. the bus of a kind of single line full duplex according to claim 1, it is characterized in that described output driving circuit B, by power supply VCC, two resistance R 3, R4 and one group of push-pull circuit that are comprised of P type metal-oxide-semiconductor and N-type metal-oxide-semiconductor form, wherein P type metal-oxide-semiconductor is connected with power supply VCC by resistance R 3, N-type metal-oxide-semiconductor is connected with GND by resistance R 4, and the output terminal of this push-pull circuit is connected with the port P2 of interface circuit B, and the resistance value of R3 equals 2 times of R4 resistance value.
8. the bus of a kind of single line full duplex according to claim 1, is characterized in that described input circuit B, and the ADC that is 2-bit by resolution forms, and this ADC is powered by power supply VCC.
9. the bus of a kind of single line full duplex according to claim 1, is characterized in that described clock generating circuit B, produces clock and exports input circuit impact damper B, output circuit impact damper B and input circuit B to.
10. the bus of a kind of single line full duplex according to claim 1, is characterized in that in described interface circuit B and interface circuit A, and the resistance value that the resistance value of R3 equals R1 equals 2 times of R4 resistance value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310640143.4A CN103605627A (en) | 2013-12-04 | 2013-12-04 | One-wire full-duplex bus |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310640143.4A CN103605627A (en) | 2013-12-04 | 2013-12-04 | One-wire full-duplex bus |
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| CN103605627A true CN103605627A (en) | 2014-02-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310640143.4A Pending CN103605627A (en) | 2013-12-04 | 2013-12-04 | One-wire full-duplex bus |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104953989A (en) * | 2015-04-27 | 2015-09-30 | 成都腾悦科技有限公司 | Communication system |
| CN106055503A (en) * | 2015-04-13 | 2016-10-26 | 英飞凌科技股份有限公司 | Signal line interface |
| CN110415504A (en) * | 2019-07-24 | 2019-11-05 | 珠海格力电器股份有限公司 | A kind of single line UART means of communication, computer readable storage medium and household electrical appliance |
| WO2022021869A1 (en) * | 2020-07-27 | 2022-02-03 | 苏州浪潮智能科技有限公司 | Single-level single-line full-duplex bus communication method and system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1506806A (en) * | 2002-12-12 | 2004-06-23 | 华邦电子股份有限公司 | Single-wire tandem transmission protocol method and circuit |
| WO2006051458A1 (en) * | 2004-11-10 | 2006-05-18 | Koninklijke Philips Electronics N.V. | Method of an device for performing bi-directional transmission using a single-wire |
| CN201724980U (en) * | 2009-04-03 | 2011-01-26 | 深圳市锐能微科技有限公司 | Electric energy metering chip with single-wire two-way serial communication interface |
| CN102693205A (en) * | 2012-05-11 | 2012-09-26 | 杭州硅星科技有限公司 | Data transmission and power supply device and data transmission and power supply method thereof |
| CN203573316U (en) * | 2013-12-04 | 2014-04-30 | 福建师范大学 | Single-line full-duplex bus |
-
2013
- 2013-12-04 CN CN201310640143.4A patent/CN103605627A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1506806A (en) * | 2002-12-12 | 2004-06-23 | 华邦电子股份有限公司 | Single-wire tandem transmission protocol method and circuit |
| WO2006051458A1 (en) * | 2004-11-10 | 2006-05-18 | Koninklijke Philips Electronics N.V. | Method of an device for performing bi-directional transmission using a single-wire |
| CN201724980U (en) * | 2009-04-03 | 2011-01-26 | 深圳市锐能微科技有限公司 | Electric energy metering chip with single-wire two-way serial communication interface |
| CN102693205A (en) * | 2012-05-11 | 2012-09-26 | 杭州硅星科技有限公司 | Data transmission and power supply device and data transmission and power supply method thereof |
| CN203573316U (en) * | 2013-12-04 | 2014-04-30 | 福建师范大学 | Single-line full-duplex bus |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106055503A (en) * | 2015-04-13 | 2016-10-26 | 英飞凌科技股份有限公司 | Signal line interface |
| CN106055503B (en) * | 2015-04-13 | 2019-10-18 | 英飞凌科技股份有限公司 | Signal wire interface |
| CN104953989A (en) * | 2015-04-27 | 2015-09-30 | 成都腾悦科技有限公司 | Communication system |
| CN110415504A (en) * | 2019-07-24 | 2019-11-05 | 珠海格力电器股份有限公司 | A kind of single line UART means of communication, computer readable storage medium and household electrical appliance |
| WO2022021869A1 (en) * | 2020-07-27 | 2022-02-03 | 苏州浪潮智能科技有限公司 | Single-level single-line full-duplex bus communication method and system |
| US11741037B2 (en) | 2020-07-27 | 2023-08-29 | Inspur Suzhou Intelligent Technology Co., Ltd. | Single-level single-line full-duplex bus communication method and system |
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Application publication date: 20140226 |