CN109818608B

CN109818608B - High-speed high common mode noise immunity level shift circuit

Info

Publication number: CN109818608B
Application number: CN201910079804.8A
Authority: CN
Inventors: 明鑫; 张春奇; 胡黎; 潘朔; 冯旭东; 张宣; 王卓; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2019-01-28
Filing date: 2019-01-28
Publication date: 2020-06-16
Anticipated expiration: 2039-01-28
Also published as: CN109818608A

Abstract

A high-speed high common mode noise immunity level shift circuit belongs to the technical field of integrated circuits. The high-speed current mirror module is used for transmitting the input signal to two output nodes of the high-speed current mirror module, so that the overturning speed of the two output nodes is improved, and the speed of a level shift circuit is greatly improved; the latch module latches the states of two output nodes of the middle node and the high-speed current mirror module through two-stage latching, and then latches the states of the output nodes of the level shift circuit, so that the power loss is reduced, and the stability of the circuit is improved; auxiliary modules are also provided to reduce the effect of the circuit on the intermediate and output node voltages when the power supply rail is floating at high speeds. The invention has the characteristics of high response speed, low power consumption and high common-mode noise immunity, and can be suitable for a driving circuit of a GAN power device.

Description

High-speed high common mode noise immunity level shift circuit

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a high-speed high-common-mode noise immunity level shift circuit which can be applied to a driving circuit of a GAN power device.

Background

With the increasing development of integrated circuits, the integration level of chips is higher and higher, on one hand, functional modules with different supply voltages need to be integrated, and on the other hand, signal transmission among the different supply voltage modules needs to be realized. Therefore, the level shift circuit capable of realizing the switching of signals among different power supply modules is widely applied to the aspects of switching power supplies, motor driving, PDP display and the like.

With the continuous development of the GAN application of the new generation of power devices, the switching frequency of the power devices is improved very much, and the energy loss of the power devices is also reduced significantly. The level shift circuit is used as a key circuit for connecting the control circuit and the output driving stage, and the development trend is bound to be as follows: fast response, low power consumption and high common mode noise immunity.

As shown in fig. 1, GAN drive in half bridge applications requires a high speed floating level shift circuit to transfer the signal of the low power rail (ground signal VSS — power signal VDD) to the high power rail (floating ground signal SW — high power signal VDDH), which is the signal at the switch node, due to the need to drive GAN devices at high speed and high power density. Meanwhile, since the SW node needs to float at a fast speed with the high-speed switching action of GAN, the level shift circuit needs to have a high common mode noise immunity. The level shift circuit reported at present cannot make a good compromise in the aspects of power consumption, common mode noise immunity, speed, circuit cost and the like, so how to design a level shift circuit which meets the requirements of high speed, low power consumption and high common mode noise immunity plays a crucial role in optimizing GAN driving.

Disclosure of Invention

Aiming at the requirements of the level shift circuit on response speed, power consumption, common-mode noise immunity and the like, the invention provides the level shift circuit which has the characteristics of quick response capability, low power consumption and high common-mode noise immunity and can be applied to a driving circuit of a GAN power device.

The technical scheme adopted by the invention for solving the technical problems is as follows:

a high-speed high common mode noise immunity level shift circuit is used for converting an input signal of a low power supply rail into an output signal of a high power supply rail, wherein the low power supply rail is a ground signal-power supply signal, and the high power supply rail is a floating ground signal-high power supply signal;

the level shift circuit comprises a high-speed current mirror module, a latch module and an auxiliary module,

the high-speed current mirror module comprises a first resistor, a second resistor, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a thirteenth PMOS tube and a fourteenth PMOS tube,

the grid electrode of the third NMOS tube is connected with the input signal, the drain electrode of the third NMOS tube is connected with the drain electrode of the fourteenth PMOS tube, and the source electrode of the third NMOS tube is connected with the source electrodes of the first NMOS tube, the second NMOS tube and the fourth NMOS tube and is connected with the ground signal;

the grid electrode of the fourth NMOS tube is connected with the inverted signal of the input signal, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the thirteenth PMOS tube;

the drain electrode of the third PMOS tube is connected with the source electrode of the thirteenth PMOS tube and serves as the first output end of the high-speed current mirror module, the grid electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the first PMOS tube and the drain electrode of the first NMOS tube, and the source electrode of the third PMOS tube is connected with the source electrodes of the first PMOS tube, the second PMOS tube and the fourth PMOS tube and is connected with a high power supply signal;

the drain electrode of the fourth PMOS tube is connected with the source electrode of the fourteenth PMOS tube and serves as a second output end of the high-speed current mirror module, and the grid electrode of the fourth PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second PMOS tube and the drain electrode of the second NMOS tube;

the grid electrodes of the thirteenth PMOS tube and the fourteenth PMOS tube are connected with a floating ground signal;

the first resistor is connected between the grid and the source of the thirteenth PMOS tube; the second resistor is connected between the drain electrode and the source electrode of the fourth PMOS tube;

the grid electrode of the first NMOS tube is connected with a first pulse signal; the grid electrode of the second NMOS tube is connected with a second pulse signal;

the first pulse signal generates a narrow pulse when the rising edge of the input signal comes, and the second pulse signal generates a narrow pulse when the falling edge of the input signal comes;

the auxiliary module comprises a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube and a twelfth PMOS tube,

the grid electrode and the source electrode of the ninth NMOS tube are connected with a ground signal, and the drain electrode of the ninth NMOS tube is connected with the grid electrode of the eleventh PMOS tube, the grid electrode and the drain electrode of the ninth PMOS tube;

the grid electrode and the source electrode of the tenth NMOS tube are connected with a ground signal, and the drain electrode of the tenth NMOS tube is connected with the grid electrode of the tenth PMOS tube, the grid electrode and the drain electrode of the twelfth PMOS tube;

the drain electrode of the twelfth NMOS tube is connected with the first output end of the high-speed current mirror module, the grid electrode of the twelfth NMOS tube is connected with the drain electrode of the eleventh PMOS tube, the grid electrode of the eleventh NMOS tube and the drain electrode of the eleventh NMOS tube, and the source electrode of the twelfth NMOS tube is connected with the source electrode of the eleventh NMOS tube and is connected with a floating ground signal;

the drain electrode of the thirteenth NMOS tube is connected with the second output end of the high-speed current mirror module, the grid electrode of the thirteenth NMOS tube is connected with the drain electrode of the tenth PMOS tube, the grid electrode of the fourteenth NMOS tube and the drain electrode of the fourteenth NMOS tube, and the source electrode of the thirteenth NMOS tube is connected with the source electrode of the fourteenth NMOS tube and is connected with a floating ground signal;

the source electrodes of the ninth PMOS tube, the tenth PMOS tube, the eleventh PMOS tube and the twelfth PMOS tube are connected with a high power supply signal;

the latch module comprises a first-stage latch unit and a second-stage latch unit, wherein the first-stage latch unit is used for stabilizing a first output end and a second output end of the high-speed current mirror module at a floating ground signal and a high power supply signal respectively;

the second-stage latch unit comprises a fifth PMOS (P-channel metal oxide semiconductor) tube, a sixth PMOS tube and a latch structure, wherein the grid electrode of the fifth PMOS tube is connected with the first output end of the high-speed current mirror module, and the source electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube and is connected with a high power supply signal; the grid electrode of the sixth PMOS tube is connected with the second output end of the high-speed current mirror module, the drain electrode of the sixth PMOS tube outputs an output signal of the level shift circuit, and the latch structure is used for latching the drain end levels of the fifth PMOS tube and the sixth PMOS tube.

Specifically, the first-stage latch unit comprises a seventh NMOS transistor, an eighth NMOS transistor, a seventh PMOS transistor and an eighth PMOS transistor,

the drain electrode of the seventh PMOS tube is connected with the drain electrode of the seventh NMOS tube, the grid electrodes of the eighth NMOS tube and the eighth PMOS tube and is connected with the first output end of the high-speed current mirror module, the source electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube and a high power supply signal, and the grid electrode of the seventh PMOS tube is connected with the grid electrode of the seventh NMOS tube, the drain electrode of the eighth PMOS tube and the second output end of the high-speed current mirror module;

the sources of the seventh NMOS transistor and the eighth NMOS transistor are connected with a floating ground signal.

Specifically, the latch structure in the second-stage latch unit comprises a fifth NMOS transistor and a sixth NMOS transistor, a drain electrode of the fifth NMOS transistor is connected to a gate electrode of the sixth NMOS transistor and a drain electrode of the fifth PMOS transistor, a gate electrode of the fifth NMOS transistor is connected to a drain electrode of the sixth NMOS transistor and a drain electrode of the sixth PMOS transistor, and a source electrode of the fifth NMOS transistor is connected to a source electrode of the sixth NMOS transistor and a floating ground signal.

The invention has the beneficial effects that: the level shift circuit provided by the invention has the characteristics of high response speed, low power consumption and high common-mode noise immunity, and can be suitable for a driving circuit of a GAN power device.

Drawings

Fig. 1 is a schematic diagram of a level shift circuit applied to a GAN half-bridge driving circuit.

Fig. 2 is an implementation form of a high-speed high common mode noise immunity level shift circuit according to an embodiment of the present invention.

FIG. 3 is a waveform diagram of a key control timing of a high speed high common mode noise immunity level shift circuit according to the present invention.

Fig. 4 is a schematic diagram of an operation principle of an auxiliary module with high common mode immunity in a high-speed high common mode noise immunity level shift circuit according to an embodiment of the present invention.

FIG. 5 is a simulation diagram of a high-speed high common mode noise immunity level shift circuit according to the present invention.

FIG. 6 illustrates the effect of a high speed high common mode noise immunity level shift circuit on nodes N1 and N2 when the floating ground signal is floating at high speed.

Fig. 7 is a block diagram of a logic circuit for generating the first Pulse signal Pulse1 and the second Pulse signal Pulse2 according to the input signal In1 and the inverted signal In2 of the input signal.

Detailed Description

The invention is described in detail below with reference to the figures and specific embodiments.

The invention provides a high-speed high-common mode noise immunity level shift circuit which is used for converting an input signal of a low power supply rail into an output signal of a high power supply rail, wherein the low power supply rail is a ground signal VSS-power supply signal VDD, the high power supply rail is a floating ground signal SW-high power supply signal VDDH, and the level shift circuit comprises a high-speed current mirror module, a latch module and an auxiliary module.

As shown In fig. 2, the high-speed current mirror module includes a first resistor R1, a second resistor R2, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a thirteenth PMOS transistor MP13, and a fourteenth PMOS transistor MP14, wherein a gate of the third NMOS transistor MN3 is connected to an input signal In1, a drain of the third NMOS transistor MP14 is connected to a drain of the fourteenth PMOS transistor MP14, and a source of the third NMOS transistor MN1, a source of the second NMOS transistor MN2, and a source of the fourth NMOS transistor MN4 are connected to the ground signal VSS; the gate of the fourth NMOS transistor MN4 is connected to the inverted signal In2 of the input signal, and the drain thereof is connected to the drain of the thirteenth PMOS transistor MP 13; the drain of the third PMOS transistor MP3 is connected to the source of the thirteenth PMOS transistor MP13 and serves as the first output terminal N1 of the high-speed current mirror module, the gate thereof is connected to the drain of the first NMOS transistor MN1, the gate and the drain of the first PMOS transistor MP1, and the source thereof is connected to the sources of the first PMOS transistor MP1, the second PMOS transistor MP2, and the fourth PMOS transistor MP4 and is connected to the high power supply signal VDDH; the drain electrode of the fourth PMOS transistor MP4 is connected to the source electrode of the fourteenth PMOS transistor MP14 and serves as the second output terminal N2 of the high-speed current mirror module, and the gate electrode thereof is connected to the drain electrode of the second NMOS transistor MN2, the gate electrode and the drain electrode of the second PMOS transistor MP 2; the gates of the thirteenth PMOS transistor MP13 and the fourteenth PMOS transistor MP14 are connected to the floating ground signal SW; the first resistor R1 is connected between the gate and the source of the thirteenth PMOS transistor MP 13; the second resistor R2 is connected between the drain and the source of the fourth PMOS transistor MP 4; the gate of the first NMOS transistor MN1 is connected with a first Pulse signal Pulse 1; the gate of the second NMOS transistor MN2 is connected to the second Pulse signal Pulse 2.

The first Pulse signal Pulse1 and the second Pulse signal Pulse2 are generated according to the input signal In1, a rising edge of the input signal In1 generates a narrow Pulse when the first Pulse signal Pulse1 arrives, a falling edge of the input signal In1 generates a narrow Pulse when the second Pulse signal Pulse2 arrives, that is, a rising edge of the inverted signal In2 of the input signal arrives when the second Pulse signal Pulse2 generates a narrow Pulse. A logic circuit for generating the first Pulse signal Pulse1 and the second Pulse signal Pulse2 according to the input signal In1 and the inverted signal In2 of the input signal is shown In fig. 7, and Vin1 and Vin2 are the input signal In1 and the inverted signal In2 of the input signal, respectively.

The defect that the turning speed of a first output end N1 and a second output end N2, namely nodes N1 and N2, of a high-speed current mirror module in the level shift circuit is not high enough is overcome by adding the high-speed current mirror module in the level shift circuit, and the speed of the level shift circuit is greatly improved.

As shown in fig. 2, the auxiliary module includes a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, and a twelfth PMOS transistor MP12, wherein a gate and a source of the ninth NMOS transistor MN9 are connected to a ground signal VSS, and a drain thereof is connected to a gate of the eleventh PMOS transistor MP11, a gate and a drain of the ninth PMOS transistor MP 9; the grid electrode and the source electrode of the tenth NMOS transistor MN10 are connected with a ground signal VSS, and the drain electrode of the tenth NMOS transistor MN10 is connected with the grid electrode and the drain electrode of the twelfth PMOS transistor MP 12; the drain of the twelfth NMOS transistor MN12 is connected to the first output terminal N1 of the high-speed current mirror module, the gate thereof is connected to the drain of the eleventh PMOS transistor MP11, the gate and the drain of the eleventh NMOS transistor MN11, and the source thereof is connected to the source of the eleventh NMOS transistor MN11 and is connected to the floating ground signal SW; the drain of the thirteenth NMOS transistor MN13 is connected to the second output terminal N2 of the high-speed current mirror module, the gate thereof is connected to the drain of the tenth PMOS transistor MP10, the gate and the drain of the fourteenth NMOS transistor MN14, and the source thereof is connected to the source of the fourteenth NMOS transistor MN14 and to the floating ground signal SW; the sources of the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11 and the twelfth PMOS transistor MP12 are connected to the high power supply signal VDDH.

The effect of the level shifting circuit on the intermediate and output node voltages when the power supply rail is floating at high speeds is reduced by adding an auxiliary module of high common mode immunity to the level shifting circuit.

The latch module comprises a first-stage latch unit and a second-stage latch unit, wherein the first-stage latch unit is used for stabilizing a first output end and a second output end of the high-speed current mirror module at a floating ground signal SW and a high power supply signal VDDH respectively.

An implementation form of the first-stage latch unit is shown in fig. 2, and includes a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a seventh PMOS transistor MP7, and an eighth PMOS transistor MP8, where a drain of the seventh PMOS transistor MP7 is connected to a drain of the seventh NMOS transistor MN7, gates of the eighth NMOS transistor MN8, and the eighth PMOS transistor MP8 and is connected to the first output terminal N1 of the high-speed current mirror module, a source of the seventh PMOS transistor MP8 and a high power signal VDDH are connected to a source of the eighth PMOS transistor MP8, and a gate of the seventh NMOS transistor MN7, a drain of the eighth NMOS transistor MN8, a drain of the eighth PMOS transistor MP8, and the second output terminal N2 of the high-speed current mirror module; the sources of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are connected to the floating ground signal SW.

The second-stage latch unit comprises a fifth PMOS tube MP5, a sixth PMOS tube MP6 and a latch structure, wherein the grid electrode of the fifth PMOS tube MP5 is connected with the first output end N1 of the high-speed current mirror module, and the source electrode of the fifth PMOS tube MP5 is connected with the source electrode of the sixth PMOS tube MP6 and is connected with a high power supply signal VDDH; the gate of the sixth PMOS transistor MP6 is connected to the second output terminal N2 of the high-speed current mirror module, and the drain thereof outputs the output signal of the level shift circuit. The latch structure is used for latching the drain levels of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6, and as shown in fig. 2, an implementation form of the latch structure in the second-stage latch unit is provided, which includes a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6, a drain of the fifth NMOS transistor MN5 is connected to a gate of the sixth NMOS transistor MN6 and a drain of the fifth PMOS transistor MP5, a gate thereof is connected to a drain of the sixth NMOS transistor MN6 and a drain of the sixth PMOS transistor MP6, and a source thereof is connected to a source of the sixth NMOS transistor MN6 and the floating ground signal SW.

The latch module in a low-power-consumption level state is added in the level shift circuit, so that the level shift circuit only generates power consumption in a short pulse, and the intermediate node state of the circuit is latched by a latch structure subsequently, so that the power consumption loss is reduced, and the stability of the circuit is improved.

The principle of this embodiment is further explained with reference to the drawings, and the control sequence of the circuit is shown in fig. 3.

First, the operation of the level shift circuit provided by the present invention when the input signal In1, i.e. vin1 In fig. 3, makes a transition is analyzed.

(1) When the input signal vin1 transits from the ground signal VSS to the power signal VDD, vin2 (i.e., the inverted signal In2 of the input signal In 1) transits from the power signal VDD to the ground signal VDD, the first pulse signal pulse1 has a short pulse signal, and the second pulse signal pulse2 still maintains a low level.

vin1 and vin2 are in an inverse relationship, pulse1 and pulse2 are generated according to the changes of vin1 and vin2, pulse1 generates a narrow pulse when the vin1 rising edge is generated, and pulse2 generates a narrow pulse when the vin2 rising edge is generated.

When the pulse comes, the first NMOS transistor MN1 operates in the saturation region, and the operating current in the saturation region is:

wherein u is_nFor electron mobility, C_oxW is the width of the first NMOS transistor MN1, L is the length of the first NMOS transistor MN1, Vgs is the gate-source voltage of the first NMOS transistor MN1, and VTH is the threshold voltage of the first NMOS transistor MN 1.

The current is mirrored from the first PMOS transistor MP1 to the third PMOS transistor MP3 through the high-speed current mirror, and the current Id _ MP3 of the third PMOS transistor MP3 injects a current into the node N1, so that the node N1 is pulled high quickly.

The node N2 is initially at the high power supply signal VDDH of the high level due to the initialization resistance, i.e., the second resistor R2. When Vin1 jumps from 0 to 1, the third NMOS transistor MN3 is turned on, the fourteenth PMOS transistor MP14 is turned on, a low-impedance path is formed, the potential of the node N2 is clamped to the floating-ground signal SW + | VTHP14|, and VTHP14 is the threshold voltage of the fourteenth PMOS transistor MP 14.

However, in order to save power consumption, the high-speed current mirror is turned on only in a very small pulse time, and when the pulse time is over, the parts of the nodes N1 and N2 connected with the current mirror are high-impedance, and the voltages of N1 and N2 are very unstable. A latch module with low power consumption is added in order to improve the stability of the nodes N1 and N2 while reducing power consumption.

In the latch module, the first-stage latch unit forms a positive feedback latch structure by a phase inverter composed of a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a seventh PMOS transistor MP7 and an eighth PMOS transistor MP 8. Since the node N1 is the high level high power supply signal VDDH, the node N2 is SW + | VTHP14 |. Therefore, the seventh PMOS transistor MP7 is turned on, the seventh NMOS transistor MN7 is turned off, the eighth NMOS transistor MN8 is turned on, and the eighth PMOS transistor MP8 is turned off. After the inverter latch structure of this stage, node N1 is pulled up to the high power supply signal VDDH, whereas node N2 is pulled down to the floating ground signal SW. At the moment, the two nodes belong to low-resistance nodes, and the stability is good.

The second-stage latch unit comprises a fifth PMOS tube MP5, a sixth PMOS tube MP6 and a latch structure for latching the drain level of MP5 and MP 6. Since the node N1 is pulled to the high power supply signal VDDH of high level and the node N2 is pulled to the floating ground signal SW of low level, the sixth PMOS transistor MP6 is turned on, the fifth PMOS transistor MP5 is turned off, the fifth NMOS transistor MN5 in the latch structure is turned on, the sixth NMOS transistor MN6 is turned off, and the output signal OUT is pulled to the high power supply signal VDDH. Output signal OUT varies between floating-ground signal SW-high supply signal VDDH.

(2) When the input signal vin1 changes from the power signal VDD to the ground signal VSS, vin2 changes from the ground signal VSS to VDD, the first pulse signal pulse1 keeps at a low level, the second pulse signal pulse2 has a pulse signal, and the circuit operates as shown in fig. 4.

When the pulse comes, the second NMOS transistor MN2 operates in the saturation region, and the operating current in the saturation region is:

the current is mirrored to the fourth PMOS transistor MP4 through the second PMOS transistor MP2 of the high-speed current mirror, and the current Id _ MP4 of the fourth PMOS transistor MP4 injects a current into the node N2, so that the node N2 is pulled high quickly.

The node N1 is initially in the high level floating ground signal SW due to the initialization resistor R1. When Vin1 changes from 1 to 0, the fourth NMOS transistor MN4 is turned on, the thirteenth PMOS transistor MP13 is turned on, a low-impedance path is formed, the potential of the node N1 is clamped to the floating-ground signal SW + | VTHP13|, and VTHP13 is the threshold voltage of the thirteenth PMOS transistor MP 13.

Similarly, the auxiliary circuit for maintaining low power consumption level can improve the stability of the nodes N1 and N2. After passing through the inverter latch structure, node N1 is pulled down to the floating ground signal SW and node N2 is pulled up to the high power supply signal VDDH.

Then the signals of the nodes N1 and N2 pass through the second stage latch unit composed of MN5, MN6, MP5 and MP 6. Since the node N2 is pulled to the high power supply signal VDDH of high level and the node N1 is pulled to the floating ground signal SW of low level, the sixth PMOS transistor MP6 is turned off, the fifth PMOS transistor MP5 is turned on, the fifth NMOS transistor MN5 is turned off, the sixth NMOS transistor MN6 is turned on, and the output signal is pulled up to the floating ground signal SW.

The influence of the dv/dt variation caused by the rapid transition of the floating-ground signal SW node mainly causes the influence of the common-mode noise inside the level shift circuit in the following two ways. The specific principle is analyzed in conjunction with the diagram 5 as follows

1. When the floating-ground signal SW node floats quickly, the floating-power high supply signal VDDH also floats quickly with the floating-ground signal SW node. However, the gate terminal voltages of MP1 and MP2 cannot follow the variation of the high power signal VDDH, so that a voltage difference is generated between the gate-source voltages of MP1 and MP2, and common mode noise currents Im1 and Im2 are generated on MP1 and MP 2.

2. When the floating supply high supply signal VDDH quickly floats with the floating ground signal SW node, dv/dt is crosstalked to the node of N1 and N2 with the parasitic capacitance CPARN1 parasitic between the high supply signal VDDH and the nodes N1, N2, CPARN 2.

When the node N1 is high and the power supply signal VDDH is high, the node N2 is low and the change in dv/dt generated by the rapid transition of the node SW generates a change in the ground signal VSS + Δ V at the node N2, and the node N1 still maintains the high power supply signal VDDH. When the voltage change Δ V of N2 caused by common mode noise is large enough to make the current IMN7 flowing through MN7 > the current IMP7 flowing through MP7, the latch formed by the inverters will be broken, the node N1 will be pulled down to the floating ground signal SW, and the node N2 will be pulled up to the high power supply signal VDDH, resulting in the error of the output logic.

Similarly, when node N2 is high and VDDH, node N1 is low and the change in dv/dt of the floating signal SW at its node transitions rapidly generates a change in the ground signal VSS + Δ V at node N1, and node N2 still maintains the high supply signal VDDH. When the voltage change Δ V of N1 caused by common mode noise is large enough to make the current IMN8 flowing through MN8 > the current IMP8 flowing through MP8, the latch formed by the inverters will be broken, the node N1 will be pulled down to the floating ground signal SW, and the node N2 will be pulled up to the high power supply signal VDDH, resulting in the error of the output logic.

Therefore, on the basis of the circuit, the circuit needs to additionally add an auxiliary module for common mode noise immunity, and the interference of common mode noise on the intermediate nodes N1 and N2 is reduced. The specific principle is analyzed in conjunction with scheme 4 as follows:

the auxiliary module of common mode immunity is composed of MN9, MP9, MP11, MN11, MN12 and MN10, MP10, MP12, MN13, MN 14. When the floating ground signal SW of the high power rail-the high power signal VDDH floats at a high speed, the crosstalk due to dv/dt also generates common mode parasitic currents Im3 and Im4 on the ninth PMOS transistor MP9 and the twelfth PMOS transistor MP12 of the current mirror. The influence of common-mode parasitic currents Im1 and Im2 on nodes N1 and N2 is counteracted by mirroring the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13 and the fourteenth NMOS transistor MN14 to the nodes N1 and N2 through the current mirror.

However, at this time, the dv/dt changes still occur from the parasitic capacitance CPARN1 and CPARN2 between the high power signal VDDH and the nodes N1 and N2 crosstalk to the nodes N1 and N2. Although this voltage variation is not sufficient to cause false flip of the inverter latch structure, this variation in Δ V is likely to cause false flip of the subsequent stage output logic.

Assuming that the node N1 is high and the node N2 is low, the node N1 still holds the high power supply signal VDDH, since the dv/dt variation generated by the rapid transition of the node SW generates a change in the ground signal VSS + Δ V at the node N2. Assuming at this time that the inverter latch is not broken. Then the current IMP6 flowing through MP6 is reduced by Δ V change during the Δ t time affected by dv/dt, but the gate terminal of MN6 is still kept low during the Δ t time, so IMP6 > IMN6, and the output is high level high supply signal VDDH.

Assuming that the node N2 is high and the node N1 is low, the node N2 still holds the high power supply signal VDDH, since the dv/dt variation generated by the rapid transition of the node SW generates a change in the ground signal VSS + Δ V at the node N1. Assuming at this time that the inverter latch is not broken. Then the current IMP5 flowing through MP5 is reduced by Δ V change during the Δ t time affected by dv/dt, but the gate of MN5 transistor remains low during the Δ t time, so IMP5 > IMN5, and the output is a low floating ground signal SW.

After the nodes N1 and N2 are shaped by the two-stage level shift circuit with common mode immunity, the change of the output waveform is smaller than that of the nodes N1 and N2, and the output waveform is not easy to be identified by the subsequent stage circuit.

Fig. 5 is a timing diagram of the circuit. When the input signal vin1 goes from logic low to high, the fast response high speed current mirror circuit pulls node N1 high quickly, node N2 low quickly, and the changes in the input signal are transmitted to the output quickly. During the pulse time, the low-power consumption circuit establishes a high potential at a node N1 and a low potential at a node N2; after the pulse width is finished, the circuit quickly responds to the turn-off of the current mirror circuit, enters a zero power consumption state, only the low power consumption level circuit maintains the electric potentials of the nodes N1 and N2, and the output electric potential is maintained through the secondary latch circuit with common mode immunity.

Meanwhile, when the output power supply rail floats at a high speed, the added common mode noise immunity auxiliary module can reduce the influence of common mode noise on the nodes N1 and N2, and the common mode noise immunity capability of the circuit is improved. FIG. 6 illustrates the effect of high speed floating of the floating ground signal SW node on the internal circuit nodes. The dotted line is the simulation result of the circuit without adding the common mode noise auxiliary circuit, and the solid line is the simulation result of the circuit with adding the common mode noise. From simulation results, it can be verified that the common mode immunity auxiliary circuit can greatly reduce the interference of common mode noise to internal nodes and output. The high-speed low-power high-common-mode immunity level shift circuit applied to GAN driving can be easily realized by the method.

It should be noted that, in addition to the GAN driving circuit applied in this embodiment, the level shift circuit proposed in the present invention can also be applied to other circuits for changing the signal of any low power rail to any high power rail. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims

1. A high-speed high common mode noise immunity level shift circuit is used for converting an input signal of a low power supply rail into an output signal of a high power supply rail, wherein the low power supply rail is a ground signal-power supply signal, and the high power supply rail is a floating ground signal-high power supply signal;

characterized in that the level shift circuit comprises a high-speed current mirror module, a latch module and an auxiliary module,

the second-stage latch unit comprises a fifth PMOS (P-channel metal oxide semiconductor) tube, a sixth PMOS tube and a latch structure, wherein the grid electrode of the fifth PMOS tube is connected with the first output end of the high-speed current mirror module, and the source electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube and is connected with a high power supply signal; the grid electrode of the sixth PMOS tube is connected with the second output end of the high-speed current mirror module, the drain electrode of the sixth PMOS tube outputs an output signal of the level shift circuit, and the latch structure is used for latching the drain electrode levels of the fifth PMOS tube and the sixth PMOS tube.

2. The high-speed high-common mode noise immunity level shift circuit according to claim 1, wherein the first stage latch unit comprises a seventh NMOS transistor, an eighth NMOS transistor, a seventh PMOS transistor and an eighth PMOS transistor,

3. The high-speed high-common mode noise immunity level shift circuit according to claim 1 or 2, wherein the latch structure in the second stage latch unit comprises a fifth NMOS transistor and a sixth NMOS transistor, a drain of the fifth NMOS transistor is connected to a gate of the sixth NMOS transistor and a drain of the fifth PMOS transistor, a gate of the fifth NMOS transistor is connected to a drain of the sixth NMOS transistor and a drain of the sixth PMOS transistor, and a source of the fifth NMOS transistor is connected to a source of the sixth NMOS transistor and a floating ground signal.