JP2011114817A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing generation of a through-current in recovery from a standby mode by reducing a sub threshold leak current and a gate leak current during standby. <P>SOLUTION: Switching of high-threshold PMOS transistors PH1-PH6 connected between a NAND gate 1/inverters 2-6, for which an output level is fixed by a clock gate signal G and a high-potential power line VDD and of high-threshold NMOS transistors NH1-NH6 connected between the NAND gate 1/inverters 2-6 and a low-potential power line VSS is controlled according to standby control signals SB1, SB2 and inverse signals SB1N, SB2N thereof. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

  In a large-scale semiconductor integrated circuit, in order to reduce power consumption, a clock gating circuit that stops clock supply when a function is stopped is used.

  In order to reduce clock skew, a clock is also supplied using a clock tree in which a plurality of clock buffers are arranged in a tree shape.

  Further, in order to improve the load driving capability of the clock buffer, the threshold value of the transistor constituting the clock buffer is also lowered. However, if the threshold value of the transistor is lowered, there arises a problem that the subthreshold leakage current increases. Therefore, a switch by a high threshold transistor is inserted between the low threshold transistor and the power source to reduce the subthreshold leakage current.

  Patent Document 1 discloses a clock network power consumption reduction circuit in which a switch having a high threshold transistor for cutting off the connection to the power supplies VDD and VSS is inserted in each buffer of the clock tree to which the output of the gated clock is connected. Has been.

  However, in the circuit disclosed in Patent Document 1, there is a timing shift in switching of the high-threshold transistors at each stage when returning from the function stop state (switch off) to the operable state (switch on). Then, when the output of the previous stage is in a high impedance state, there is a problem that the subsequent buffer starts to operate first, and a large through current flows through the subsequent buffer.

  In order to solve this problem, Patent Document 2 discloses that each buffer in the clock tree is inserted with a switch with a high threshold transistor only in one of the power supplies VDD and VSS, so that the output of each buffer during standby is output. A semiconductor device is disclosed that fixes a potential and prevents a through current from flowing through each buffer when returning from a standby state to an operable state.

  By the way, with the recent progress of thinning of semiconductor integrated circuits, the gate oxide film of transistors tends to be thin. For this reason, the gate leakage current that flows due to the tunnel effect has increased compared to the prior art.

  For this reason, in a circuit in which the output potential of the previous stage is fixed in the standby state as in the circuit shown in Patent Document 2, the function stop state is caused by a potential difference generated between the gate electrode and the source electrode of the subsequent buffer. There is a problem that a gate leakage current sometimes flows.

JP 2006-287552 A (6th page, FIG. 4) JP 2008-53976 A (page 6, FIG. 4)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can reduce a subthreshold leakage current and a gate leakage current during standby and prevent a through current from flowing when returning from a standby mode.

  According to one aspect of the present invention, a plurality of logic gate circuits connected in cascade and a high threshold voltage first circuit connected between a high potential power supply line and each high potential power supply terminal of the plurality of logic gate circuits are connected. 1 MOS transistor, a high-potential second MOS transistor connected between a low-potential power line and a low-potential power terminal of each of the plurality of logic gate circuits, and the plurality of logic gate circuits Stopped and connected to a first signal line for inputting a function stop control signal for fixing each output potential to either a high potential or a low potential, and a logic gate circuit whose output potential at the time of the function stop is a high potential The switching of the second MOS transistor and the first MOS transistor connected to the logic gate circuit whose output potential when the function is stopped is low is controlled. A second signal line for inputting the first standby control signal, the first MOS transistor connected to the logic gate circuit having a high output potential when the function is stopped, and the output potential when the function is stopped And a third signal line for inputting a second standby control signal for controlling the switching of the second MOS transistor connected to the logic gate circuit having a low potential. The

  According to the present invention, it is possible to reduce the subthreshold leakage current and the gate leakage current during standby, and to prevent a through current from flowing when returning from the standby state.

1 is a logic circuit diagram showing an example of a configuration of a semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram showing the semiconductor device shown in FIG. 1 at a transistor level. FIG. 6 is an operation explanatory diagram of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating an operation state in a standby mode of the semiconductor device according to the first embodiment of the invention. FIG. 3 is a diagram illustrating an operation state during the return to the normal operation mode of the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a logic circuit diagram showing an example of a configuration of a semiconductor device according to Embodiment 2 of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

  FIG. 1 is a logic circuit diagram showing an example of the configuration of a clock buffer 10 which is a semiconductor device according to Embodiment 1 of the present invention.

  The clock buffer 10 has a NAND gate 1 as a clock gating circuit in the first stage, and five stages of inverters 2 to 6 are cascaded to the output of the NAND gate 1. Note that the number of inverters is not limited to five, but may be any number according to the necessity in circuit design.

  High threshold PMOS transistors PH1 to PH6 are respectively connected between the high potential power supply terminals of the NAND gate 1 and the inverters 2 to 6 and the high potential power supply line VDD.

  Also, high threshold NMOS transistors NH1 to NH6 are connected between the low potential power supply terminals of the NAND gate 1 and the inverters 2 to 6 and the low potential power supply line VSS, respectively.

  A clock signal CLK and a clock gate signal G are input to the NAND gate 1. When the clock gate signal G is logic “0”, clock gating is performed, and the output of the NAND gate 1 is fixed to the “H” level. The output of the NAND gate 1 is sequentially inverted and transmitted, and the outputs of the inverters 2, 3, 4, 5, and 6 are also fixed to “L”, “H”, “L”, “H”, and “L”. The

  Further, the standby control signal SB1 and the standby control signal SB2 are input to the clock buffer 10.

  Standby control signals SB1 and SB2 are inverted by inverters IV1 and IV2, respectively, and inverted signals SB1N and SB2N are generated.

  The standby control signals SB1 and SB2 and the inverted signals SB1N and SB2N are input to the gate electrodes of the high threshold PMOS transistors PH1 to PH6 and NMOS transistors NH1 to NH6. The input destination is determined based on the output levels of the NAND gate 1 and the inverters 2 to 6 at the time of clock gating.

  That is, the standby control signal SB1 is input to the gate electrodes of the NMOS transistors NH1, NH3, and NH5 connected to the NAND gate 1, the inverter 3, and the inverter 5 whose output level at the time of clock gating is 'H', respectively. An inverted signal SB2N of the standby control signal SB2 is input to the gate electrodes of the transistors PH1, PH3, and PH5.

  Further, the inverted signal SB1N of the standby control signal SB1 is input to the gate electrodes of the PMOS transistors PH2, PH4, and PH6 connected to the inverter 2, the inverter 4, and the inverter 6 whose output level is “L” during clock gating, respectively. The standby control signal SB2 is input to the gate electrodes of the NMOS transistors NH2, NH4, and NH6.

  By controlling the switching of the high threshold PMOS transistors PH1 to PH6 and the NMOS transistors NH1 to NH6 by the standby control signals SB1 and SB2, it is possible to prevent an off-leakage current from flowing through the NAND gate 1 and the inverters 2 to 6 in the standby mode.

  FIG. 2 is a circuit diagram when the logic gate, that is, NAND gate 1 and inverters 2 to 6 of the circuit shown in FIG. 1 are formed of MOS transistors.

  In the NAND gate 1, NMOS transistors N11 and N12 connected in series are connected in series to PMOS transistors P11 and P12 connected in parallel.

  In the inverter 2, a PMOS transistor P2 and an NMOS transistor N2 are connected in series. The inverters 3 to 6 have the same configuration as the inverter 2.

  Here, the outputs of the NAND gate 1 and the inverters 2 to 6 are represented as O1 to O6.

  Next, referring to FIG. 3 to FIG. 5, the high-threshold PMOS transistor when the clock buffer 10 of the present embodiment is shifted from the normal operation mode to the standby mode and is returned from the standby mode to the normal operation mode. The switching control of PH1 to PH6 and NMOS transistors NH1 to NH6 will be described.

  FIG. 3 is a diagram showing a waveform of an input signal related to standby operation control and a switching state of a high threshold PMOS transistor and an NMOS transistor, and FIG. 4 is a diagram showing an internal operation state in the standby mode. FIG. 5 is a diagram illustrating an operation state inside the circuit during the return from the standby mode to the normal operation mode.

  In the following description, only operations of the NAND gate 1 and the inverters 2 and 3 will be described. Since the operations of the inverters 4 to 6 are the same as those of the inverter 1 or the inverter 2, the description thereof is omitted.

  In this embodiment, as shown in FIG. 3, the standby operation is controlled by changing the signal levels of the clock gate signal G, the standby control signal SB1, and the standby control signal SB2 with a time difference.

  That is, when shifting from the normal operation mode to the standby mode, first, the clock gate signal G is changed from “1” to “0”, and then the standby control signal SB1 is changed from “1” to “0”. Finally, the standby control signal SB2 is changed from “1” to “0”.

  As described above, when shifting from the normal operation mode to the standby mode, first, the clock gate signal G is changed from ‘1’ to ‘0’.

  As a result, the output O1 of the NAND gate 1 is fixed to the 'H' level. Further, the output O2 of the inverter 2 is fixed to the “L” level, and the output O3 of the inverter 3 is fixed to the “H” level.

  Next, the standby control signal SB1 is changed from “1” to “0”.

  As a result, the high threshold NMOS transistor NH1 connected to the NAND gate 1, the high threshold PMOS transistor PH2 connected to the inverter 2, and the high threshold NMOS transistor NH3 connected to the inverter 3 are turned off.

  The high-threshold transistors that are turned off are all connected to a power supply line having a potential opposite to the output levels of the outputs O1 to O3. In other words, the NMOS transistor N11 of the NAND gate 1, the PMOS transistor P2 of the inverter 2, the NMOS transistor N3 of the inverter 3, and the low potential power supply line VSS or the high potential which are turned off when the lock gate signal G becomes “0”. It is a transistor connected between the power supply line VDD.

  Therefore, by turning off the high threshold NMOS transistor NH1, the PMOS transistor PH2, and the NMOS transistor NH3, the NMOS transistor N11, the PMOS transistor P2, and the NMOS transistor N3 in the off state are transferred to the low potential power supply line VSS or the high potential power supply line VDD. Therefore, it is possible to prevent the subthreshold current from flowing.

  Finally, the standby control signal SB2 is changed from “1” to “0”.

  This turns off the high threshold PMOS transistor PH1 connected to the NAND gate 1, the high threshold NMOS transistor NH2 connected to the inverter 2, and the high threshold PMOS transistor PH3 connected to the inverter 3. The buffer 10 is in a standby mode.

  In the standby mode, the output O1 of the NAND gate 1, the output O2 of the inverter 2, and the output O3 of the inverter 3 are in a high impedance state, but almost no subthreshold current flows through the high-threshold MOS transistor that is turned off. The output levels of the outputs O1 to O3 are temporarily maintained as they are.

  FIG. 4 is a circuit diagram showing the internal state of the circuit in the standby mode.

  As described above, in the standby mode, the output O1 of the NAND gate 1 is temporarily held at the ‘H’ level, and the output O2 of the inverter 2 is temporarily held at the ‘L’ level. Therefore, a gate leakage current may occur in the gate electrode of the NMOS transistor N2 of the inverter 2 and the PMOS transistor P3 of the inverter 3 to which the output is input.

  However, in this embodiment, the high threshold NMOS transistor NH2 and the PMOS transistor PH3 are turned off by the standby control signal SB2, so that the source electrodes of the NMOS transistor N2 and the PMOS transistor P3 become high impedance ('HZ'), and the respective gates thereof. The gate leakage current between the electrodes does not continue to flow beyond the subthreshold current in the high threshold MOS transistor.

  That is, it is possible to prevent the gate leakage current from continuing to flow in the standby mode.

  Next, the procedure for inputting the clock gate signal G, the standby control signal SB1, and the standby control signal SB2 when the clock buffer 10 of this embodiment is returned from the standby mode to the normal operation mode will be described.

  When returning from the standby mode to the normal operation mode, as shown in FIG. 3, first, the standby control signal SB2 is changed from “0” to “1”, and then the standby control signal SB1 is changed from “0”. Then, the clock gate signal G is changed from “0” to “1”.

  First, when the standby control signal SB2 is changed from "0" to "1", the high threshold PMOS transistor PH1, NMOS transistor NH2, and PMOS transistor PH3 are turned on as shown in FIG. However, at this time, since the high threshold NMOS transistor NH1, the PMOS transistor PH2, and the NMOS transistor NH3 are still in the off state, no through current flows through the NAND gate 1 and the inverters 2 and 3.

  The high threshold PMOS transistor PH1, NMOS transistor NH2, and PMOS transistor PH3 are transistors connected to the power supply line having the same potential as the output levels of the outputs O1 to O3, and the output levels of the outputs O1 to O3 are the NAND gates. 1 and the subthreshold leakage of the transistors constituting the inverters 2 and 3 are set to the same potential as the low potential power supply line VSS or the high potential power supply line VDD without depending on the input level. Therefore, no current flows between the outputs O1 to O3 and the low potential power supply line VSS or the high potential power supply line VDD.

  Thereafter, the standby control signal SB1 is changed from “0” to “1”, and finally the clock gate signal G is changed from “0” to “1”, whereby the clock buffer 10 returns to the normal operation mode. .

  According to this embodiment, the output level is fixed by the clock gate signal G which is a function stop control signal, and the connection is made between the logic gate circuit at each stage of the clock buffer 10 and the high potential power line VDD. By switching the switching of the high threshold NMOS transistor connected between the high threshold PMOS transistor and the low potential power supply line VSS by the standby control signal SB1 and the standby control signal SB2, the standby mode is set. It is possible to prevent the subthreshold current and the gate leakage current from flowing through the logic gate circuit of each stage of the clock buffer 10 in the standby mode, and also prevent the through current from flowing when returning to the normal operation.

  FIG. 6 is a logic circuit diagram showing an example of the configuration of the clock buffer 20 which is a semiconductor device according to the second embodiment of the present invention.

  The clock buffer 20 is obtained by expanding the inverters 3 to 6 of the clock buffer 10 of the first embodiment into a clock tree structure. Here, two stages of inverters are set as one buffer, and this buffer is arranged in a tree shape.

  That is, a buffer consisting of inverters 31 and 41 and a buffer consisting of inverters 32 and 42 are connected to the output of inverter 2, and a buffer consisting of inverters 51 and 61 and inverters 52 and 62 are connected to the output of the buffer consisting of inverters 31 and 41. A buffer consisting of inverters 53 and 63 and a buffer consisting of inverters 54 and 64 are connected to the output of the buffer consisting of inverters 32 and 42.

  As in the first embodiment, a high-threshold PMOS transistor is connected to the high-potential power line VDD, and a high-threshold NMOS transistor is connected to the low-level power line VSS.

  The switching between the high threshold PMOS transistor and the NMOS transistor is also controlled by the standby control signals SB1 and SB2 and the inverted signals SB1N and SB2N, respectively, as in the first embodiment.

  For example, switching of the high-threshold PMOS transistor PH31 connected between the inverter 31 and the high-potential power line VDD is controlled by the inverted signal SB2N of the standby control signal SB2, and between the inverter 31 and the low-potential power line VSS. Switching of the connected high threshold NMOS transistor NH31 is controlled by a standby control signal SB1. The switching of the high threshold PMOS transistor PH41 connected between the inverter 41 and the high potential power line VDD is controlled by the inverted signal SB1N of the standby control signal SB1, and between the inverter 41 and the low potential power line VSS. Switching of the connected high threshold NMOS transistor NH41 is controlled by a standby control signal SB2.

  With this connection, in the present embodiment, the same control as in the first embodiment can be performed with respect to the transition from the normal operation mode to the standby mode and the return from the standby mode to the normal operation mode.

  According to the present embodiment, even if the clock buffer whose output level is fixed by the clock gate signal G has a clock tree structure, the sub-threshold current and the gate leakage current are generated in the logic gate circuit in each stage in the standby mode. It is possible to prevent the current from flowing, and to prevent a through current from flowing through the logic gate circuit at each stage when returning to the normal operation.

1 NAND gates 2-6, 31-64. IV1, IV2 Inverters PH1-PH6, PH31-PH64 High threshold PMOS transistors NH1-NH6, NH31-NH64 High threshold NMOS transistors P11, P12, P2-P6 PMOS transistors N11, N12, N2-N6 PMOS transistors 10, 20 Clock buffer

Claims (4)

A plurality of cascaded logic gate circuits;
A high-threshold first MOS transistor connected between a high-potential power line and a high-potential power terminal of each of the plurality of logic gate circuits;
A high-threshold second MOS transistor connected between a low-potential power line and each low-potential power terminal of each of the plurality of logic gate circuits;
A first signal line for inputting a function stop control signal for stopping the function of the plurality of logic gate circuits and fixing each output potential at either a high potential or a low potential;
The second MOS transistor connected to the logic gate circuit whose output potential when the function is stopped is high and the first MOS connected to the logic gate circuit whose output potential when the function is stopped is low A second signal line for inputting a first standby control signal for controlling switching of the transistor;
The first MOS transistor connected to the logic gate circuit whose output potential when the function is stopped is high and the second MOS transistor connected to the logic gate circuit whose output potential when the function is stopped is low A semiconductor device comprising: a third signal line for inputting a second standby control signal for controlling switching of the transistor. When shifting from normal operation mode to standby mode,
First, the function stop control signal is set to a level for instructing function stop, then the first standby control signal is set to a level for instructing switching off, and finally, the second standby control signal is instructed to switch off. Is the level to be
When returning from standby mode to normal operation mode,
First, the second standby control signal is set to a level for instructing switching on, then the first standby control signal is set to a level for instructing switching on, and finally, the function stop control signal indicates a functional operation. The semiconductor device according to claim 1, wherein the semiconductor device is at a level to be used. A plurality of cascaded logic gate circuits,
The first stage is a clock gating circuit that stops the clock by the function stop control signal, and the subsequent stages are all inverters.
3. The semiconductor device according to claim 1, comprising a clock buffer. The semiconductor device according to claim 3, wherein the clock buffer has a clock tree structure.

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