JP2013090278A - Output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output circuit that allows improving reliability even if a circuit outputting a high-voltage signal is configured by low-withstand-voltage transistors.SOLUTION: In an output circuit, an output section 1 includes PMOS transistors P11 and P12 that are connected between a high-voltage power-supply terminal VCCH and an output terminal Z, and NMOS transistors N11 and N12 that are connected between a ground potential terminal GND and the output terminal Z. A pre-buffer section 2 receiving a low-voltage input signal IN outputs gate voltages PG and NG with a smaller amplitude than the VCCH to the PMOS transistor P11 and the NMOS transistor N11. A constant voltage VG lower than the VCCH is applied to gate terminals of the PMOS transistor P12 and the NMOS transistor N12, a substrate bias voltage VBP lower than the VCCH is applied to a substrate of the PMOS transistor P12, and a substrate bias voltage VBN higher than the ground potential is applied to a substrate of the NMOS transistor N12.

Description

  Embodiments described herein relate generally to an output circuit.

  With the recent miniaturization of semiconductor integrated circuits, the internal power supply voltage of semiconductor integrated circuits has been lowered to a low voltage of 1V or less. On the other hand, in the interface with the outside, there are cases where it is still necessary to output a high voltage signal such as 3 V from the semiconductor integrated circuit. As one of the countermeasures, the output circuit has been configured with a high breakdown voltage transistor. However, as miniaturization progresses, apart from the development of low breakdown voltage transistors for internal circuits, the development load becomes very heavy to develop high breakdown voltage transistors for output circuits.

  In view of this, there has been proposed a system in which an output circuit that outputs a high voltage signal is constituted by a low breakdown voltage transistor. In this system, a MOS transistor to which a low voltage system gate voltage is applied is connected in series with a MOS transistor to which a high voltage system gate voltage is applied. As a result, the electric field strength applied to the gate oxide film or the like is divided between the high voltage and the low voltage, such as “gate-source (drain)” and “source-drain” voltages of each MOS transistor. Can be reduced.

  However, even in this method, when there is a defect such as an open failure in the MOS transistor to which the voltage of the high voltage power supply or the gate voltage of the low voltage system is applied, the MOS to which the gate voltage of the high voltage system is applied A problem arises in that the breakdown voltage of the transistor is excessive and the reliability of the output circuit is lowered. It is also a concern to secure a margin for withstand voltage of the MOS transistor to which a low-voltage gate voltage is applied.

JP 2000-295089 A JP 2005-33530 A

  The problem to be solved by the present invention is to provide an output circuit capable of improving the reliability even if a circuit for outputting a high voltage signal is constituted by a low breakdown voltage transistor.

  In the output circuit of the embodiment, the output unit includes a first PMOS transistor and a second PMOS transistor connected in series between the high-voltage power supply terminal and the output terminal, and between the ground potential terminal and the output terminal. The first and second NMOS transistors are connected in series to each other, and a pre-buffer unit to which an input signal of a low voltage level is input includes the first PMOS transistor and the first NMOS transistor. A gate voltage having an amplitude smaller than the high voltage is output. A constant voltage lower than the high voltage is applied to the gate terminals of the second PMOS transistor and the second NMOS transistor, and a first substrate bias voltage lower than the high voltage is applied to the substrate of the second PMOS transistor. And a second substrate bias voltage higher than the ground potential is applied to the substrate of the second NMOS transistor.

FIG. 3 is a circuit diagram showing an example of the configuration of the output circuit of the first embodiment. The figure for demonstrating the effect of a substrate bias voltage application. A circuit diagram showing an example of composition of an output circuit of a 2nd embodiment. The circuit diagram which shows the example of a structure of the output part of the output circuit of 3rd Embodiment. The circuit diagram which shows the example of a structure of the output part of the output circuit of 4th Embodiment. The circuit diagram which shows the example of a structure of a substrate bias voltage generation circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

(First embodiment)
FIG. 1 is a circuit diagram illustrating an example of a configuration of an output circuit according to the first embodiment.

  The output circuit of this embodiment includes a PMOS transistor P11 (first PMOS transistor) and a PMOS transistor P12 (second PMOS transistor) connected in series between the high voltage power supply terminal VCCH and the output terminal Z, and a ground. An output unit 1 having an NMOS transistor N11 (first NMOS transistor) and an NMOS transistor N12 (second NMOS transistor) connected in series between the potential terminal GND and the output terminal Z, and a low voltage (VCCL) ) Level input signal is input, and the pre-buffer unit 2 outputs the gate voltages PG and NG having an amplitude smaller than that of the high voltage VCCH to the PMOS transistor P11 and the NMOS transistor N11.

  Here, the high voltage VCCH for external output is, for example, 3V, and the low voltage VCCL for the internal circuit is, for example, 1V. At this time, if a MOS transistor having a withstand voltage of 2V is used in the internal circuit, the output circuit of the present embodiment is configured by a MOS transistor having the same withstand voltage (2V) as the internal circuit.

  When the withstand voltage is 2V, the rating of the MOS transistor is that the “gate-source (drain) voltage” is 2V, the “source-drain voltage” is 2V, and the “source-drain-substrate voltage” is Assume 3V.

  In order to use this low breakdown voltage MOS transistor, the gate voltage VG of the PMOS transistor P12 and the NMOS transistor N12 is fixed at 1 / 2VCCH, for example.

  FIG. 1 also shows an example of the configuration of the internal circuit of the prebuffer unit 2.

  In this example, the pre-buffer unit 2 includes a pull-up PMOS transistor P21 connected to the high voltage power supply terminal VCCH, a pull-down NMOS transistor N21 whose conduction is controlled by a low voltage level input signal IN, and a PMOS transistor. It has three stages of diodes D1, D2, D3 connected in the forward direction between P21 and the NMOS transistor N21, and an inverter IV1 operating at a low voltage VCCL for inverting the input signal IN.

  Here, the output of the inverter IV1 is further inverted by the inverter IV2 and input to the gate terminal of the NMOS transistor N21.

  In the prebuffer unit 2, the output PG of the pull-up PMOS transistor P21 is input to the gate terminal of the PMOS transistor P11 of the output unit 1, and the output NG of the inverter IV1 is supplied to the gate terminal of the NMOS transistor N11 of the output unit 1. Entered.

  Accordingly, when the input signal IN is 'H' (1V), the output NG is GND (0V). Since the NMOS transistor N21 is turned on at this time, the output PG is approximately 1.5 to 2.1V when the forward voltages of the diodes D1, D2, and D3 are 0.5 to 0.7V.

  On the other hand, when the input signal IN is ‘L’ (0V), the output NG is VCCL (1V). Since the NMOS transistor N21 is turned off at this time, the output PG becomes (VCCH− | Vthp |) when the threshold value of the PMOS transistor P21 is Vthp. That is, for example, when Vthp = −0.5V, the output PG is about 2.5V.

  Therefore, the pre-buffer unit 2 can also be composed of a low breakdown voltage MOS transistor having a breakdown voltage of 2V.

  In the output circuit of this embodiment, the substrate bias voltage VBP (first substrate bias voltage) lower than the high voltage VCCH is applied to the substrate of the PMOS transistor P12 of the output unit 1, and the ground potential is applied to the substrate of the NMOS transistor N12. A substrate bias voltage VBN (second substrate bias voltage) higher than GND is applied.

  FIG. 2 shows an example of substrate connection of a normal MOS transistor. In this case, the substrate of the PMOS transistor P12 is connected to the high voltage power supply terminal VCCH, and the substrate of the NMOS transistor N12 is connected to the ground potential terminal GND.

  Therefore, as shown in FIG. 2A, when the output to the output terminal Z is ‘L’, the “drain-substrate voltage” of the PMOS transistor P12 becomes VCCH. Further, as shown in FIG. 2B, when the output to the output terminal Z is 'H', the drain-substrate voltage of the NMOS transistor N12 becomes VCCH. Both are the values at the last minute rating of the low breakdown voltage transistor.

  On the other hand, in the present embodiment, the drain-substrate voltage of the PMOS transistor P12 when the output terminal Z is “L” is (VCCH−VBP), and the output terminal Z is “H”. The drain-substrate voltage of the NMOS transistor N12 is (VCCH-VBN).

  That is, a withstand voltage margin corresponding to VBP or VBN is obtained with respect to the rated voltage between the drain and the substrate.

  According to the present embodiment as described above, the output circuit for outputting a high voltage signal can be constituted by a low breakdown voltage MOS transistor. Further, by adjusting the substrate bias voltage applied to the substrate of the MOS transistor connected to the output terminal, the breakdown voltage margin between the drain and the substrate of the MOS transistor can be improved.

(Second Embodiment)
In the present embodiment, an example of an output circuit capable of ensuring a withstand voltage margin of a low withstand voltage MOS transistor to be used even when the voltage of the high voltage VCCH becomes higher than usual due to a change in power supply voltage or the like will be described.

  FIG. 3 is a circuit diagram showing an example of the configuration of the output circuit of the present embodiment.

  This embodiment is different from the first embodiment in that the output unit 1A includes a PMOS transistor P13 (third PMOS transistor) whose gate terminal is connected to the drain terminal between the high voltage power supply terminal VCCH and the PMOS transistor P11. The pre-buffer unit 2A includes a PMOS transistor P22 having a gate terminal connected to the drain terminal between the high-voltage power supply terminal VCCH and the pull-up PMOS transistor P21.

  Since the PMOS transistor P13 and the PMOS transistor P22 have a self-bias configuration in which the gate terminal is connected to the drain terminal, the drain terminal voltage is lower than the high voltage VCCH which is the source terminal voltage by the threshold voltage (absolute value thereof). Voltage.

  That is, when the threshold voltage of the PMOS transistor is Vthp, the voltage applied to the source terminals of the PMOS transistor P11 and the transistor P21 is (VCCH− | Vthp |).

  As a result, the effective power supply voltage of the entire circuit decreases by the threshold voltage of the PMOS transistor, and the withstand voltage margin of each MOS transistor increases accordingly.

  Therefore, according to the present embodiment as described above, even if the voltage of the high voltage VCCH fluctuates higher, if the fluctuation amount is equal to or less than the threshold voltage of the PMOS transistor, a sufficient breakdown voltage margin of each MOS transistor is ensured. can do.

(Third embodiment)
The output circuit of the present embodiment is obtained by replacing the output unit 1 of the output circuit of the first embodiment with an output unit 1B.

  FIG. 4 is a circuit diagram showing an example of the configuration of the output unit 1B of the present embodiment.

  The output unit 1B of the present embodiment has a clamp circuit 31 and a clamp circuit 32 added to the output unit 1 of the first embodiment.

  The clamp circuit 31 is connected between a node a, which is a connection point between the PMOS transistor P11 and the PMOS transistor P12, and the high voltage power supply terminal VCCH.

  The clamp circuit 32 is connected between a node b, which is a connection point between the NMOS transistor N11 and the NMOS transistor N12, and the ground potential terminal GND.

  FIG. 4 shows, as an example of the configuration of the internal circuit of the clamp circuit 31, a circuit in which a PMOS transistor P31 and a PMOS transistor P32 are connected in series, each having a drain terminal connected to a gate terminal. Further, as an example of the configuration of the internal circuit of the clamp circuit 32, a circuit in which an NMOS transistor N31 and an NMOS transistor N32 are connected in series, each having a drain terminal connected to a gate terminal is shown.

  The clamp circuit 31 functions to prevent the potential of the node a from being lowered when the potential of the node a is lowered from the assumed potential, and the clamp circuit 32 is used when the potential of the node b is tried to rise from the assumed potential. , Work to prevent the rise.

  The operation will be described taking the clamp circuit 31 as an example.

  The potential of the node a becomes the high voltage VCCH when outputting the “H” level to the output terminal Z.

  On the other hand, when outputting the 'L' level to the output terminal Z, the potential of the node a does not drop to the ground potential GND due to the action of the PMOS transistor P12, and (gate voltage VG + threshold voltage of the PMOS transistor P12) Become.

  However, if the PMOS transistor P12 has a defect in which a leak current flows due to, for example, a defect of an element, for example, the PMOS transistor P11 is turned off, so that the potential of the node a tends to decrease toward the ground potential GND. . If the ground potential GND is reduced as it is, the PMOS transistor P11 has a problem of excessive breakdown voltage.

  However, in the present embodiment, when the potential of the node a decreases to (VCCH− (the threshold value of the PMOS transistor P31 + the threshold value of the PMOS transistor P32)), a current flows through the clamp circuit 31, and the decrease in the potential of the node a is stopped. Take it.

  As a result, the potential of the node a is kept constant, and the breakdown voltage of the PMOS transistor P11 is secured.

  Similarly, the clamp circuit 32 operates when there is a defect that a leakage current flows through the NMOS transistor N12 when the 'H' level is output to the output terminal Z, and the potential of the node b increases, Stop the increase in the potential of b. As a result, the potential of the node b is kept constant, and the breakdown voltage of the NMOS transistor N11 is secured.

  According to the present embodiment, even if the MOS transistor connected to the output terminal has a leak failure, the potential at the other end of the MOS transistor can be kept constant. Thereby, the breakdown voltage of the MOS transistor connected to the other end of the MOS transistor can be ensured.

(Fourth embodiment)
The output circuit of this embodiment is obtained by replacing the output unit 1A of the output circuit of the second embodiment with an output unit 1C.

  FIG. 5 is a circuit diagram illustrating an example of the configuration of the output unit 1C of the present embodiment.

  The output unit 1C of the present embodiment is obtained by adding the clamp circuit 31 and the clamp circuit 32 described in the third embodiment to the output unit 1A of the second embodiment.

  Since the configurations and operations of the clamp circuit 31 and the clamp circuit 32 are the same as those in the third embodiment, the description thereof is omitted here.

  According to this embodiment, in addition to the effects obtained in the second embodiment, the effects described in the third embodiment can also be obtained.

(Substrate bias voltage generation circuit)
In each of the above embodiments, the substrate bias voltage VBP applied to the substrate of the PMOS transistor P12 and the substrate bias voltage VBN applied to the substrate of the NMOS transistor N12 may be input from the outside of the integrated circuit, It may be generated internally.

  FIG. 6 shows an example of a substrate bias voltage generation circuit used when the substrate bias voltage VBP and the substrate bias voltage VBN are generated inside the integrated circuit.

A substrate bias voltage generation circuit 100 shown in FIG. 6 includes a PMOS transistor P101 having a source terminal connected to a high voltage power supply terminal VCCH and a gate terminal connected to a drain terminal.
An NMOS transistor N101 having a source terminal connected to the ground potential terminal GND and a gate terminal connected to the drain terminal, and a PMOS transistor P102 connected in series between the drain terminal of the PMOS transistor P101 and the drain terminal of the NMOS transistor N101. And an NMOS transistor N102. The gate terminals of the PMOS transistor P102 and the NMOS transistor N102 are commonly connected to the connection point between the PMOS transistor P102 and the NMOS transistor N102.

  Since the PMOS transistor P101 has a self-bias configuration in which the gate terminal is connected to the drain terminal, the drain terminal voltage is lower than the high voltage VCCH, which is the source terminal voltage, by a threshold voltage. A substrate bias voltage VBP is output from the drain terminal of the PMOS transistor P101.

  Therefore, the substrate bias voltage VBP becomes (the threshold value of the VCCH-PMOS transistor P101).

  Since the NMOS transistor N101 has a self-bias configuration in which the gate terminal is connected to the drain terminal, the drain terminal voltage is higher than the ground potential GND, which is the source terminal voltage, by a threshold voltage. A substrate bias voltage VBN is output from the drain terminal of the NMOS transistor N101.

  Therefore, the substrate bias voltage VBN becomes (GND + the threshold value of the NMOS transistor N101).

  The potential Vm at the connection point between the PMOS transistor P102 and the NMOS transistor N102 is an intermediate potential between the substrate bias voltage VBP and the substrate bias voltage VBN.

  Therefore, this substrate bias voltage generation circuit 100 can also be formed of a low breakdown voltage MOS transistor.

  By using such a substrate bias voltage generation circuit, the substrate bias voltage VBP and the substrate bias voltage VBN applied to the output circuit can be automatically supplied inside the semiconductor integrated circuit.

  According to the output circuit of at least one embodiment described above, the reliability can be improved even if the circuit that outputs a high voltage signal is formed of a low breakdown voltage transistor.

  Moreover, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1, 1A, 1B, 1C Output unit 2, 2A Pre-buffer unit 100 Substrate bias voltage generation circuits P11 to P13, P21, P22, P31, P32, P101, P102 PMOS transistors N11, N12, N21, N31, N32, N101, N102 NMOS transistors IV1, IV2 Inverters D1-D3 Diode

Claims (6)

A first PMOS transistor and a second PMOS transistor connected in series between a high voltage power supply terminal and an output terminal, and a first NMOS transistor connected in series between a ground potential terminal and the output terminal And an output section having a second NMOS transistor;
A pre-buffer unit that receives an input signal at a low voltage level and outputs a gate voltage having an amplitude smaller than the high voltage to the first PMOS transistor and the first NMOS transistor;
A constant voltage lower than the high voltage is applied to the gate terminals of the second PMOS transistor and the second NMOS transistor,
A first substrate bias voltage lower than the high voltage is applied to a substrate of the second PMOS transistor;
An output circuit, wherein a second substrate bias voltage higher than a ground potential is applied to a substrate of the second NMOS transistor. The output unit is
The output circuit according to claim 1, further comprising a third PMOS transistor having a gate terminal connected to a drain terminal between the high-voltage power supply terminal and the first PMOS transistor. The output unit is
A first clamp circuit for preventing a drop in potential when a potential at a connection point between the first PMOS transistor and the second PMOS transistor is lowered from an assumed potential;
2. A second clamp circuit for preventing an increase in potential when a potential at a connection point between the first NMOS transistor and the second NMOS transistor is increased from an assumed potential. The output circuit according to 1 or 2. The pre-buffer unit is
A pull-up PMOS transistor connected to the high voltage power supply terminal;
A pull-down NMOS transistor whose conduction is controlled by the low voltage level input signal;
A diode connected in a forward direction between the pull-up PMOS transistor and the pull-down NMOS transistor;
An inverter operating at a low voltage for inverting the input signal at the low voltage level,
The output of the pull-up PMOS transistor is input to the gate terminal of the first PMOS transistor,
4. The output circuit according to claim 1, wherein an output of the inverter is input to a gate terminal of the first NMOS transistor. 5. The pre-buffer unit is
5. The output circuit according to claim 4, further comprising a PMOS transistor having a gate terminal connected to a drain terminal between the high-voltage power supply terminal and the pull-up PMOS transistor. 6. The output circuit according to claim 1, further comprising a substrate bias voltage generation circuit that generates the first substrate bias voltage and the second substrate bias voltage.

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