TWI674720B - Power protection circuit - Google Patents

Abstract

A power supply protection circuit according to an embodiment includes a first pad provided with a first voltage, a second pad provided with a second voltage different from the first voltage, first and second transistors, and a switch circuit. The first transistor includes a first terminal electrically connected to the first pad, a second terminal electrically connected to the first node and the back gate, and a gate electrically connected to the second node. The second transistor includes a first terminal electrically connected to the first node, a second terminal electrically connected to the second pad, and a back gate. When the gate of the second transistor is input with the first logic signal, the switch circuit electrically connects the second node to the first pad, and the gate of the second transistor is connected with the first logic signal. In the case of the second logic signal of the inverted logic level, the second node is electrically cut off from the first pad and electrically connected to the first node.

Description

Power protection circuit

The embodiment relates to a power protection circuit.

A power source protection circuit for protecting a power source of a semiconductor device from a surge is known.

The embodiment provides a power protection circuit capable of reducing leakage current flowing in the power protection circuit.

The power supply protection circuit according to the embodiment includes a first pad, a second pad, a first transistor, a second transistor, and a switch circuit. The first pad is supplied with a first voltage. The second pad is supplied with a second voltage different from the first voltage. The first transistor includes a first terminal electrically connected to the first pad, a second terminal electrically connected to the first node and a back gate, and a gate electrically connected to the second node. The second transistor includes a first terminal electrically connected to the first node, a second terminal electrically connected to the second pad, and a back gate. When the gate of the second transistor is input with a first logic signal, the switch circuit electrically connects the second node with the first pad, and when the gate of the second transistor is input with the first When the 1 logic signal is the second logic signal of an inverted logic level, the second node is electrically cut off from the first pad and electrically connected to the first node.

1‧‧‧ semiconductor device

11‧‧‧Solder Pad Group

12‧‧‧Interface circuit

13‧‧‧Power protection circuit

13-0‧‧‧Comparative Example Power Protection Circuit

14‧‧‧ Internal Circuit

C1‧‧‧Capacitor

C1a‧‧‧Capacitor

D1‧‧‧diode

D2‧‧‧Zina Diode

INV0‧‧‧ Inverter

INV1‧‧‧ Inverter

INV2‧‧‧ Inverter

INV3‧‧‧ Inverter

INV1b‧‧‧ Inverter

INV2b‧‧‧ Inverter

INV3b‧‧‧ Inverter

Is‧‧‧ on current

Is0‧‧‧ on current

N1‧‧‧node

N2‧‧‧node

N3‧‧‧node

N4‧‧‧node

N5‧‧‧node

N6‧‧‧node

P1‧‧‧pad

P2‧‧‧soldering pad

P3‧‧‧pad

R1‧‧‧ resistance

R1a‧‧‧ resistance

R2‧‧‧Resistor

R2b‧‧‧ resistance

R3‧‧‧ resistance

Tr0‧‧‧Transistor

Tr1‧‧‧Transistor

Tr1b‧‧‧Transistor

Tr2‧‧‧Transistor

Tr2b‧‧‧Transistor

Tr3‧‧‧Transistor

Tr3b‧‧‧Transistor

Tr4‧‧‧Transistor

Tr4b‧‧‧Transistor

Tr5‧‧‧Transistor

V1‧‧‧Voltage

V2‧‧‧Voltage

VDD‧‧‧Voltage

VSS‧‧‧Voltage

VT‧‧‧Voltage

VTb‧‧‧Voltage

FIG. 1 is a block diagram for explaining the structure of the semiconductor device according to the first embodiment.

FIG. 2 is a diagram illustrating a configuration of a power protection circuit of the semiconductor device according to the first embodiment. Illustrated circuit diagram.

FIG. 3 is a timing chart for explaining the operation of the power supply protection circuit of the semiconductor device according to the first embodiment.

FIG. 4 is a circuit diagram for explaining a configuration of a power supply protection circuit of a semiconductor device of a comparative example.

FIG. 5 is a graph for explaining the effect of the first embodiment.

Fig. 6 is a graph for explaining the effect of the first embodiment.

FIG. 7 is a circuit diagram for explaining a configuration of a power supply protection circuit of a semiconductor device according to a first modification of the first embodiment.

FIG. 8 is a circuit diagram for explaining a configuration of a power supply protection circuit of a semiconductor device according to a second modification of the first embodiment.

FIG. 9 is a circuit diagram for explaining a configuration of a power supply protection circuit of a semiconductor device according to a second modification of the first embodiment.

FIG. 10 is a circuit diagram for explaining a configuration of a power supply protection circuit of a semiconductor device according to a second modification of the first embodiment.

FIG. 11 is a circuit diagram for explaining a configuration of a power supply protection circuit of a semiconductor device according to a third modification of the first embodiment.

FIG. 12 is a timing chart for explaining the operation of the power supply protection circuit of the semiconductor device according to the third modified example of the first embodiment.

FIG. 13 is a circuit diagram for explaining a configuration of a power protection circuit of a semiconductor device according to a second embodiment.

FIG. 14 is a timing chart for explaining the operation of the power supply protection circuit of the semiconductor device according to the second embodiment.

FIG. 15 is a circuit diagram for explaining a configuration of a power supply protection circuit of a semiconductor device according to a first modification of the second embodiment.

FIG. 16 is a circuit diagram for explaining a configuration of a power supply protection circuit of a semiconductor device according to a second modification of the second embodiment.

FIG. 17 is a circuit diagram for explaining a configuration of a power supply protection circuit of a semiconductor device according to a second modification of the second embodiment.

FIG. 18 is a circuit diagram for explaining a configuration of a power supply protection circuit of a semiconductor device according to a second modification of the second embodiment.

FIG. 19 is a circuit diagram for explaining a configuration of a power supply protection circuit of a semiconductor device according to a third modified example of the second embodiment.

FIG. 20 is a timing chart for explaining an operation of a power supply protection circuit of a semiconductor device according to a third modified example of the second embodiment.

Hereinafter, embodiments will be described with reference to the drawings. In the following description, constituent elements having the same function and configuration are denoted by common reference symbols.

1. First embodiment

The power supply protection circuit of the first embodiment will be described.

1.1 About composition

First, the configuration of a semiconductor device including the power supply protection circuit according to the first embodiment will be described.

1.1.1 Structure of semiconductor devices

FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device according to the first embodiment. The semiconductor device 1 includes, for example, a semiconductor wafer which is connected to an external device (not shown) from a semiconductor device. The input signal performs specific processing and outputs the output signal.

The semiconductor device 1 performs signal I / O (Input / Output) communication with an external device, for example. The signal I / O is a data entity that is transmitted and received between the semiconductor device 1 and an external device, and includes input signals and output signals.

Various voltages are supplied to the semiconductor device 1. The voltage supplied to the semiconductor device 1 includes, for example, the voltages VDD and VSS. The voltage VDD is a reference voltage for driving the semiconductor device 1, and is, for example, 1.8V. The voltage VSS is a ground voltage and is smaller than the voltage VDD. The voltage VSS is, for example, 0V.

The semiconductor device 1 includes a pad group 11, an interface circuit 12, a power protection circuit 13, and an internal circuit 14.

The pad group 11 includes pads P1 and P2 for voltage supply. The pads P1 and P2 share voltages VDD and VSS with the power protection circuit 13, respectively. Furthermore, in the example of FIG. 1, each of the pads P1 and P2 is shown as one functional block, but it is not limited thereto, and a plurality of pads P1 and P2 may be provided. When each of the pads P1 and P2 is provided in a plurality of wafers, the plurality of pads P1 and P2 may be distributed in a plurality of locations in the wafer.

The pad group 11 includes, for example, a pad P3 for signal transmission and reception. The pad P3 transmits an input signal received from an external device to the interface circuit 12. The pad P3 outputs a signal received from the interface circuit 12 to the outside of the semiconductor device 1 as an output signal.

When the interface circuit 12 receives an input signal from the pad P3 as a signal I / O, the interface circuit 12 sends the input signal to the internal circuit 14. When the interface circuit 12 receives an output signal from the internal circuit 14, the interface circuit 12 outputs the output signal to the outside through the pad P3.

The power protection circuit 13 and the interface circuit 12 share a voltage VDD. The power protection circuit 13 has, for example, a function of sharing a voltage VDD with the interface circuit 12, and the voltage VDD is based on the voltage VDD and VSS reduces the voltage caused by the surge when the voltage VDD generates a surge. The details of the power protection circuit 13 will be described later. In addition, for example, when a plurality of pads P1 and P2 are provided, the power supply protection circuit 13 is provided corresponding to the layout of the plurality of pads P1 and P2 in the chip.

The internal circuit 14 is a circuit having a functional configuration that performs specific processing of the semiconductor device 1. When the internal circuit 14 receives a signal from the interface circuit 12, it performs a specific process and generates an output signal as a result of the specific process.

1.1.2 About the composition of the power protection circuit

Next, the configuration of the power supply protection circuit of the semiconductor device according to the first embodiment will be described using FIG. 2.

As shown in FIG. 2, the power protection circuit 13 includes transistors Tr1, Tr2, and Tr3, resistors R1 and R2, a capacitor C1, and inverters INV1, INV2, and INV3. The transistor Tr1 is, for example, a MOS (Metal Oxide Semiconductor) transistor having a p-channel polarity. The transistors Tr2 and Tr3 are, for example, MOS transistors having n-channel polarity. Transistors Tr1 to Tr3, resistors R1 and R2, capacitors C1, and inverters INV1 to INV3 can function as RCT (Resistance Capacitor Triggered) MOS circuits.

As described above, the power supply protection circuit 13 is supplied with the voltages VDD and VSS through the pads P1 and P2, respectively.

The first terminal of the resistor R1 is connected to the pad P1, and the second terminal of the resistor R1 is connected to the node N1. The first terminal of the capacitor C1 is connected to the node N1, and the second terminal is connected to the pad P2. The resistor R1 and the capacitor C1 function as a RC (resistor capacitor) timer, and operate based on a time constant determined by the resistance value and capacitance of each. Specifically, the voltage at node N1 is associated with Changes in voltage following the pad P1 with a time delay based on the time constant.

The inverters INV1 and INV2 are connected in series between the nodes N1 and N2. Specifically, the input terminal of the inverter INV1 is connected to the node N1, and the output terminal is connected to the input terminal of the inverter INV2. The output terminal of the inverter INV2 is connected to the node N2.

The input terminal of the inverter INV3 is connected to the node N2, and the output terminal is connected to the gate of the transistor Tr3.

The inverters INV1 to INV3 may be configured to output a signal having a value corresponding to the potential difference between the pads P1 and P2, for example.

The first terminal and the back gate of the transistor Tr1 are connected to the pad P1, the second terminal is connected to the node N3, and the gate is connected to the node N2. That is, the first terminal and the second terminal of the transistor Tr1 function as a source and a drain, respectively. Furthermore, the back gate is also called the "subject".

The first terminal of the resistor R2 is connected to the node N3, and the second terminal of the resistor R2 is connected to the node N4.

The first terminal of the transistor Tr2 is connected to the pad P1, the second terminal and the back gate are connected to the node N4, and the gate is connected to the node N3. The first terminal of the transistor Tr3 is connected to the node N4, the second terminal and the back gate are connected to the pad P2, and the gate is connected to the output terminal of the inverter INV3. That is, the first terminal of the transistor Tr2 and the first terminal of the transistor Tr3 function as a drain, and the second terminal of the transistor Tr2 and the second terminal of the transistor Tr3 function as a source.

Transistors Tr2 and Tr3 have the following functions: they turn on when the voltage of pad P1 rises sharply, so that the ON current Is flows from the first end to the second end, and alleviates the sudden change in voltage caused by the voltage of the pad P1 Influence of the interface circuit 12. Furthermore, it is preferable that the transistors Tr2 and Tr3 have gate sizes which are the same size as each other. The gate size is, for example, a ratio (W / L) of the gate width W to the gate length L. The gate sizes of transistors Tr2 and Tr3 are larger than the gate sizes of other transistors Tr1.

Moreover, the transistors Tr1 to Tr3 are preferably switched to an on state or an off state at a certain voltage (for convenience, referred to as a voltage VT) between the voltage VDD and the voltage VSS. More preferably, the voltage VT is set between the voltage VDD and the voltage VDD / 2. The transistor Tr1 is turned on when a voltage lower than the voltage VT is applied to the gate, and is turned off when a voltage higher than the voltage VT is applied to the gate. The transistors Tr2 and Tr3 are turned off when a voltage lower than the voltage VT is applied to the gate, and are turned on when a voltage higher than the voltage VT is applied to the gate. In this way, it is preferable that the transistor having p-channel polarity and the transistor having n-channel polarity be turned off when one side is turned on and the other side is turned on when one side is turned off. On state.

In the following description, for the voltage applied to the gates of the transistors Tr1 to Tr3, the logic level of the voltage lower than the voltage VT is referred to as "L" level, and the voltage higher than the voltage VT is referred to as "H" Level.

In addition, the inverters INV1 to INV3 may be configured similarly to the transistors Tr1 to Tr3 to switch the logic level of the signal output from the output terminal according to the voltage input to the input terminal being less than or greater than the voltage VT. More specifically, the inverters INV1 ~ INV3 can also output the “H” level from the output when the “L” level is input to the input terminal, and output the “H” level from the output terminal when the “H” level is input to the input terminal. L "level. With this configuration, the inverters INV1 to INV3 function as signal control circuits, for example, and switch the logic bits of the signals input to the gates of the transistors Tr2 and Tr3 according to whether the voltage value of the node N1 exceeds the voltage VT. quasi.

1.2 About the operation of the power protection circuit

Next, the operation of the power supply protection circuit of the semiconductor device according to the first embodiment will be described.

FIG. 3 is a timing chart for explaining the operation of the power protection circuit of the first embodiment. Illustration. FIG. 3 schematically shows an operation of the power protection circuit 13 when a surge is generated and when power is constantly supplied as an example. As an example of the surge, FIG. 3 shows a case where a surge is generated based on a Human Body Model (HBM). In the following description, the periods during which the power supply protection circuit 13 operates when a surge is generated are referred to as “operation periods when the power surge is generated”, and the periods during which the power protection circuit 13 operates when power is constantly supplied. It is expressed as "normal operation period".

As shown in FIG. 3, the voltage VDD is not supplied to the semiconductor device 1 before time T10. Therefore, the pads P1 and P2 become, for example, the voltage VSS. The nodes N1, N2, N3, and N4 then all become the voltage VSS ("L" level). The transistors Tr2 and Tr3 are then turned off, and the on-current Is does not flow.

At time T10, a surge is generated, so the voltage of the pad P1 rises sharply, and then gradually approaches the voltage VSS. The voltage at the node N1 is gradually increased because the capacitor C1 is charged in response to the surge, but it decreases again as the voltage of the pad P1 decreases. Therefore, the node N1 remains at the "L" level during the operation period when the surge is generated.

The inverter INV1 then outputs the "H" level. The "H" level output from the inverter INV1 is input to the inverter INV2. Thereby, the inverter INV2 outputs the "L" level to the node N2. Therefore, the "L" level output from the inverter INV2 is input to the gate of the transistor Tr1 and the input terminal of the inverter INV3.

The inverter INV3 outputs the "H" level by being input to the "L" level. The "H" level output from the inverter INV3 is input to the gate of the transistor Tr3, so that the transistor Tr3 is turned on.

In addition, the transistor Tr1 is turned on by being input with the "L" level, and the voltage at the node N3 is electrically connected to the pad P1 and changes in the same manner as the pad P1 to the "H" level. therefore, The transistor Tr2 is turned on.

In this way, the resistor R1 and the capacitor C1 function as a trigger circuit, and the transistors Tr2 and Tr3 are turned on with the generation of a surge as a trigger. Since the transistors Tr2 and Tr3 are both turned on during the operation when the surge is generated, the switching current Is flows with the transistors Tr2 and Tr3 as current paths, and flows from the pad P1 toward the pad P2.

By operating as described above, the power supply protection circuit 13 stops the on-current Is flowing during the surge generation operation.

On the other hand, during normal operation, the node N1 reaches the voltage VDD with the capacitor C1 being fully charged. That is, the node N1 becomes "H" level.

When the node N1 becomes the "H" level, the inverter INV1 outputs the "L" level. The "L" level output from the inverter INV1 is input to the inverter INV2. Thereby, the inverter INV2 outputs the "H" level to the node N2. Therefore, the "H" level output from the inverter INV2 is input to the gate of the transistor Tr1 and the input terminal of the inverter INV3.

The inverter INV3 outputs the "L" level by being input to the "H" level. The "L" level output from the inverter INV3 is input to the gate of the transistor Tr3, so that the transistor Tr3 is turned off.

The transistor Tr1 is turned off by being input with the "H" level. As a result, the node N3 is electrically cut off by the self-pad P1, but it remains in a state of being connected to the node N4 via the resistor R2. At this time, the voltages at the nodes N3 and N4 become the voltage V1. The magnitude of the voltage V1 is between the voltage VDD and VSS, and is smaller than the voltage VT ("L" level), for example. When the gate sizes of the transistors Tr2 and Tr3 are the same, the voltage V1 is, for example, about VDD / 2. Therefore, the transistor Tr2 is turned off.

By operating in the above manner, the power supply protection circuit 13 activates power during normal operation. Both the crystals Tr2 and Tr3 are turned off, thereby preventing the on-current Is from flowing. The voltages at the nodes N3 and N4 are maintained at the voltage V1.

1.3 Effects of this embodiment

According to the first embodiment, the leakage current flowing in the power protection circuit can be reduced. This effect will be described below.

In order to prevent a surge from being applied to an internal circuit when an electrostatic discharge (ESD: Electrostatic Discharge) is generated, a method of using an RCTMOS circuit as a power source protection circuit has been proposed.

The RCTMOS circuit must force a short circuit between the power source and the ground when a surge is generated, so a transistor with a large gate size is used. Therefore, the leakage current generated by the transistor will increase correspondingly according to its gate size. The dominant factors among the factors that cause leakage current include gate leakage and GIDL (Gate Induced Drain Leakage). Gate leakage is mainly caused by the potential difference between the gate and the drain of the transistor. GIDL is mainly generated in accordance with the potential difference between the back gate and the drain of the transistor, and the potential difference between the gate and the drain. It is known that the leakage current and the potential difference between the drain and the source increase exponentially correspondingly.

According to the first embodiment, the first terminal of the transistor Tr1 is connected to the pad P1, the second terminal is connected to the node N3, and the gate is connected to the node N2. The node N2 becomes the "L" level when the node N1 is at the "L" level, and becomes the "H" level when the node N1 is at the "H" level. That is, the transistor Tr1 is turned on because the gate is input to the "L" level when the node N1 is at the "L" level. Therefore, during the operation period when the surge is generated, the node N3 is electrically connected to the pad P1. Therefore, the "H" level can be input to the gate of the transistor Tr2, and the transistor Tr2 can be turned on. On the other hand, when the node N1 is at the "H" level, the gate of the transistor Tr1 is input to the "H" position And it becomes disconnected. Thereby, during the normal operation period, the node N3 is electrically cut off from the pad P1. Therefore, the "L" level can be input to the gate of the transistor Tr2, so that the transistor Tr2 is turned off.

In addition, the resistor R2 electrically connects the node N3 and the node N4. Thereby, during the normal operation period, the voltage of the node N3 is maintained at the voltage of the node N4. The node N4 is an intermediate node between the transistors Tr2 and Tr3, and thus becomes a voltage V1 which is an intermediate potential between the voltage VDD and the voltage VSS. Therefore, the gate and back gate of the transistor Tr2 can be made to the voltage V1.

The inverter INV3 includes an input terminal connected to the node N2 and an output terminal connected to the gate of the transistor Tr3. Accordingly, the inverter INV3 outputs the "H" level when the node N1 is at the "L" level, and outputs the "L" level when the node N1 is at the "H" level. Therefore, the transistor Tr3 can be turned on during the operation period when a surge occurs, and the transistor Tr3 can be turned off during the normal operation period.

The above effect will be specifically described using a comparative example.

FIG. 4 is a circuit diagram for explaining a configuration of a power protection circuit of a comparative example. As shown in FIG. 4, the power supply protection circuit 13-0 of the comparative example includes a resistor R1, a capacitor C1, a plurality of inverters INV0 and a transistor Tr0 connected in series. The power supply protection circuit 13-0 corresponds to a configuration in which the transistors Tr1 and Tr2 and the resistor R2 are removed from the power supply protection circuit 13 of the first embodiment. More specifically, the transistor Tr0 includes a gate connected to the first terminal of the pad P1, a second terminal connected to the pad P2, and a gate connected to the output terminals of the plurality of inverters INV0.

Hereinafter, a comparison between the characteristics of the power protection circuit 13-0 of the above-mentioned comparative example and the characteristics of the power protection circuit 13 of the first embodiment will be described with reference to FIGS. 5 and 6.

5 and 6 are graphs for explaining the effect of the first embodiment. In FIGS. 5 and 6, the characteristics of the power protection circuit 13 of the first embodiment and the power protection circuit of the comparative example are shown. The characteristics of Road 13-0 are shown in a comparative manner.

First, the effect shown in FIG. 5 will be described. In FIG. 5, the logarithm shows the magnitude of the leakage current when the voltage VDD is constantly applied to the pad P1 (normal operation period). That is, FIG. 5 shows the magnitude of the leakage current in a state where the on-current Is for flowing the short circuit between the pads P1 and P2 is not flowing in the power protection circuit. Specifically, in FIG. 5, the leakage current of the power protection circuit 13-0 is represented by a curve L1, and the leakage current of the power protection circuit 13 is represented by a curve L2.

As shown in FIG. 5, the leakage current in the power protection circuit 13 can be suppressed to be lower than the leakage current in the power protection circuit 13-0. Specifically, when the voltage supplied to the pad P1 is the voltage VDD, the power protection circuit 13 can reduce the leakage current to about 1/1000 compared to the power protection circuit 13-0. Moreover, the magnitude of the leakage current of the power protection circuit 13 when the voltage VDD is supplied can be suppressed to be equal to the magnitude of the leakage current of the power protection circuit 13-0 when the voltage VDD / 2 is supplied.

The reason is that during normal operation, the potential difference between the back gate and the drain of the transistor Tr0 and the potential difference between the gate and the drain is the voltage VDD. In contrast, the back gate of the transistor Tr2 and Tr3 The potential difference between the drain and the drain and the potential difference between the gate and the drain are reduced to a voltage of about VDD / 2.

More specifically, the gate of the transistor Tr2 is connected to the node N3, and the potential difference between the gate of the transistor Tr2 and the drain of the transistor Tr2 becomes about VDD / 2. By inputting the "L" level from INV3, the potential difference between the gate of transistor Tr3 and node N4 becomes smaller than the voltage VDD / 2. This reduces the potential difference between the gates and the drains of the transistors Tr2 and Tr3, thereby reducing the leakage current caused by the gate leakage.

Furthermore, the back gate of the transistor Tr2 is connected to the node N4, and the potential difference between the back gate of the transistor Tr2 and the drain of the transistor Tr2 becomes a voltage of about VDD / 2. The back gate of transistor Tr3 is connected to pad P2, and the potential difference between the back gate of transistor Tr3 and node N4 becomes a voltage. Around VDD / 2. Thereby, the potential difference between the back gate and the drain of the transistors Tr2 and Tr3 is reduced, thereby reducing the leakage current caused by GIDL.

The power supply protection circuit 13 of the first embodiment is designed so that the gate sizes of the transistors Tr2 and Tr3 are the same. Thereby, the voltage V1 is equal to the voltage VDD / 2. Therefore, the potential difference between the back gate and the drain of the transistors Tr2 and Tr3 and the potential difference between the gate and the drain become the voltage VDD / 2, and the leakage current can be minimized.

Next, the effect shown in FIG. 6 will be described. In FIG. 6, it is assumed that the operation is performed when a surge is generated, and the magnitude of the on-current Is corresponding to the voltage VDD supplied to the pad P1 is shown. Specifically, in FIG. 6, the on-current of the power protection circuit 13-0 is represented by the curve L3, and the leakage current of the power protection circuit 13 is represented by the curves L4 and L5. The curve L4 shows the case where the transistors Tr2 and Tr3 are applied with the same gate size as the transistor Tr0. The curve L5 shows the case where the transistor Tr2 and Tr3 use a gate size twice the size of the transistor Tr0.

As shown in FIG. 6, when the gate sizes are the same, the turn-on current Is flowing in the power protection circuit 13 is smaller than the turn-on current Is0 flowing in the power protection circuit 13-0. The reason is that since the transistors Tr2 and Tr3 are connected in series between the pads P1 and P2, the gate size of the transistor in the power protection circuit 13 becomes substantially smaller. Therefore, when the gate size is the same, the ESD protection characteristic of the power protection circuit 13 is reduced compared to the power protection circuit 13-0.

However, in general, the correlation between the turn-on current and the gate size is linear. Therefore, as shown by the curve L5, by making the gate size of the power supply protection circuit 13 approximately twice as large, for example, an on-current 2Is equal to or greater than the on-current Is0 can flow.

Furthermore, it is considered that by increasing the gate size, the leakage current also increases linearly with respect to an increase in the gate size. However, as shown in FIG. 5, the power supply protection circuit 13 is improved exponentially (reduced to about 1/1000 times) relative to the power supply protection circuit 13-0, so it can be sufficiently Make up for the effect of reducing the ESD protection characteristics due to the larger gate size (about 2 times increase). Therefore, leakage current can be reduced without damaging ESD protection characteristics.

1.4 Variation of the first embodiment

The semiconductor device of the first embodiment is not limited to the above-mentioned example, and various changes can be applied.

1.4.1 First modification

For example, the power protection circuit 13 may include a transistor instead of the resistor R2.

Fig. 7 is a circuit diagram showing a configuration of a power protection circuit according to a first modification of the first embodiment. As shown in FIG. 7, the transistor Tr4 includes a first terminal connected to the node N3, a second terminal connected to the node N4, and a gate connected to the node N2. The transistor Tr4 has, for example, n-channel polarity.

The transistor Tr4 is turned off when the "N" level is supplied to the node N2, that is, during the period when the surge is generated. Thereby, the node N3 can be electrically cut off from the node N4, so that the voltage supplied to the transistor Tr2 can be more stable. The transistor Tr4 is turned on when the "N" level is supplied to the node N2, that is, during the normal operation period. Thereby, the node N3 can be electrically connected to the node N4 when no on-current Is flows in the transistor Tr2. Therefore, the potential of the gate of the transistor Tr2 can be maintained at the intermediate potential V1 of the pads P1 and P2, thereby reducing the leakage current.

1.4.2 Second modification

The trigger circuit in the power supply protection circuit 13 is not limited to having a timer function based on the RC time constant, and may include other trigger circuits that do not have a timer function. FIG. 8, FIG. 9, and FIG. 10 are circuit diagrams showing a configuration of a power protection circuit according to a second modification of the first embodiment.

FIG. 8 shows an example in which a plurality of diodes D1 connected in series are used instead of the capacitor C1. As shown in FIG. 8, the plurality of diodes D1 includes an input terminal (anode) connected to the node N1, and Connected to the output (cathode) of pad P2. The plurality of diodes D1 are set, for example, to the on state when the voltage of the pad P1 rises to such an extent that the on-current Is must flow to protect the internal circuit 14 from ESD damage.

With this configuration, when the plurality of diodes D1 are turned on, the voltage at the node N1 decreases due to the voltage drop generated by the resistor R1, and becomes the "L" level. Thereby, the transistors Tr2 and Tr3 can be turned on, and the on-current Is can flow. When the voltage of the pad P1 returns to the normal operating range, the plurality of diodes D1 are turned off. Therefore, the voltage drop generated by the resistor R1 basically disappears, and the voltage at the node N1 becomes the "H" level. Thereby, the on-current Is can be stopped.

FIG. 9 shows an example in which a Zener diode D2 is used instead of the capacitor C1. As shown in FIG. 9, the Zener diode D2 includes an input terminal (cathode) connected to the node N1 and an output terminal (anode) connected to the pad P2. The zener diode D2 is set to, for example, a falling state when the voltage of the pad P1 rises to such an extent that the on-current Is must flow to protect the internal circuit 14 from ESD damage.

With this structure, when the Zener diode D2 is in a falling state, the voltage at the node N1 is reduced due to the voltage generated by the resistor R1, and becomes the "L" level. Thereby, the transistors Tr2 and Tr3 can be turned on, and the on-current Is can flow. In addition, when the voltage of the pad P1 returns to the normal operating range, the Zener diode D2 recovers from the falling state. Therefore, the voltage drop generated by the resistor R1 basically disappears, and the voltage at the node N1 becomes the "H" level. Thereby, the on-current Is can be stopped.

An example in which a transistor Tr5 and a resistor R3 are used instead of the capacitor C1 is shown in FIG. 10. As shown in FIG. 10, the transistor Tr5 includes a first terminal connected to the node N1 and a second terminal connected to the pad P2. The resistor R3 includes a first terminal connected to the gate of the transistor Tr5 and a second terminal connected to the pad P2. end. The transistor Tr5 is set in the same manner as the Zener diode D2 in FIG. 9 so that, for example, when the voltage of the pad P1 rises to a level where the on-current Is must flow to protect the internal circuit 14 from ESD damage, the transistor Tr5 is in a falling state.

By constituting in this way, when the transistor Tr5 is in a falling state, the voltage at the node N1 is reduced due to the voltage generated by the resistor R1, and becomes the "L" level. Thereby, the transistors Tr2 and Tr3 can be turned on, and the on-current Is can flow. In addition, when the voltage of the pad P1 returns to the normal operating range, the transistor Tr5 recovers from the falling state. Therefore, the voltage drop generated by the resistor R1 basically disappears, and the voltage at the node N1 becomes the "H" level. Thereby, the on-current Is can be stopped.

1.4.3 Third modification

In addition, for example, the power protection circuit 13 may be provided with an RC timer in a direction opposite to the pads P1 and P2.

FIG. 11 is a circuit diagram showing a configuration of a power protection circuit according to a third modified example of the first embodiment. FIG. 11 shows an example in which the capacitor C1a and the resistor R1a are used instead of the resistor R1 and the capacitor C1.

As shown in FIG. 11, the capacitor C1a includes a first terminal connected to the pad P1 and a second terminal connected to the node N1. The resistor R1a includes a first terminal connected to the node N1 and a second terminal connected to the pad P2. The resistor R1a and the capacitor C1a function as an RC timer, and operate based on a time constant determined by the resistance value and the capacitance of each of them.

In FIG. 11, the inverter INV2 is removed. That is, the output terminal of the inverter INV1 is connected to the node N2.

FIG. 12 is a timing chart showing the operation of the power protection circuit according to the third modified example of the first embodiment. FIG. 12 corresponds to FIG. 3 of the first embodiment.

As shown in FIG. 12, a surge is generated at time T10. As a result, the voltage of the pad P1 rises sharply, and then gradually approaches the voltage VSS. Node N1 follows the voltage rise of pad P1. Therefore, the node N1 remains at the "H" level during the operation period when the surge is generated. The inverter INV1 then outputs the "L" level. Therefore, the "L" level output from the inverter INV1 is input to the gate of the transistor Tr1 and the input terminal of the inverter INV3 via the node N2.

Thereby, the transistors Tr2 and Tr3 are both turned on, and the on-current Is uses the transistors Tr2 and Tr3 as current paths, and flows from the pad P1 toward the pad P2. In addition, since the operations of the transistors Tr1 to 3 and the inverter INV3 are the same as those of FIG. 3, the description is omitted.

By operating in the above manner, the power supply protection circuit 13 stops the on-current Is flowing during the operation period when the surge is generated.

On the other hand, during normal operation, the voltage at the node N1 becomes the voltage VSS. That is, the node N1 becomes the "L" level during the normal operation period. With this, the inverter INV1 outputs the "H" level. Therefore, the "H" level output from the inverter INV1 is input to the gate of the transistor Tr1 and the input terminal of the inverter INV3.

As a result, the transistors Tr2 and Tr3 are both turned off, and the on-current Is does not flow. In addition, since the operations of the transistors Tr1 to 3 and the inverter INV3 are the same as those of FIG. 3, the description is omitted.

By operating as described above, in the power supply protection circuit 13, the on-current Is does not flow during the normal operation period. The voltages at the nodes N3 and N4 are maintained at the voltage V1.

In this way, when the RC timer is mounted in the reverse direction, the same signals as those in the first embodiment can be input to the transistors Tr2 and Tr3. Therefore, the same effect as that of the first embodiment can be produced.

In addition, this modification can be similarly applied to the second modification. That is, the trigger circuit is not limited to having a timer function based on the RC time constant, and other functions without a timer function. The trigger circuit can also be installed in the opposite direction. Specifically, in FIG. 11 of this modification, a configuration may be adopted in which a plurality of diodes, a zener diode, and a transistor are included instead of the capacitor C1a. In this case, the same effect as that of this modification can be produced.

2. Second Embodiment

Next, a semiconductor device according to a second embodiment will be described. The semiconductor device of the first embodiment is configured such that an on-current Is flows through a transistor having an n-channel polarity. On the other hand, the semiconductor device of the second embodiment differs from the first embodiment in that the on-current Is flows through a transistor having a p-channel polarity. Hereinafter, the same constituent elements as those in the first embodiment are denoted by the same reference numerals and descriptions thereof will be omitted, and only the parts different from the first embodiment will be described.

2.1 About the composition of the power protection circuit

A configuration example of a power supply protection circuit of the semiconductor device according to the second embodiment will be described with reference to FIG. 13. FIG. 13 corresponds to FIG. 2 in the first embodiment.

As shown in FIG. 13, the power protection circuit 13 includes transistors Tr1b, Tr2b, and Tr3b, resistors R1 and R2b, a capacitor C1, and inverters INV1b and INV3b. The transistor Tr1b has, for example, n-channel polarity. The transistors Tr2b and Tr3b have, for example, p-channel polarity. The configuration of the resistor R1 and the capacitor C1 is the same as that of FIG. 2 of the first embodiment, and therefore description thereof is omitted.

The inverter INV1b includes an input terminal connected to the node N1 and an output terminal connected to the node N2. The input terminal of the inverter INV3b is connected to the node N2, and the output terminal is connected to the gate of the transistor Tr2b. The inverters INV1b and INV3b may be configured to output, for example, a signal having a value corresponding to the potential difference between the pads P1 and P2.

The first terminal and the back gate of the transistor Tr1b are connected to the pad P2, the second terminal is connected to the node N5, and the gate is connected to the node N2. That is, the first and second ends of the transistor Tr1b are used as the source and sink, respectively. Extremely functional.

The first terminal of the resistor R2b is connected to the node N5, and the second terminal is connected to the node N6.

The first terminal and back gate of the transistor Tr2b are connected to the pad P1, the second terminal is connected to the node N6, and the gate is connected to the output terminal of the inverter INV3b. The first terminal and the back gate of the transistor Tr3b are connected to the node N6, the second terminal is connected to the pad P2, and the gate is connected to the node N5. That is, the first terminal of the transistor Tr2b and the first terminal of the transistor Tr3b function as a source, and the second terminal of the transistor Tr2b and the second terminal of the transistor Tr3b function as a drain. It is preferable that the transistors Tr2b and Tr3b have gate sizes that are equal to each other.

In addition, the transistors Tr1b to Tr3b are preferably switched to an on state or an off state at a certain voltage (for convenience, referred to as a voltage VTb) between the voltage VDD and the voltage VSS. More preferably, the voltage VTb should be set between the voltage VDD / 2 and the voltage VSS. The transistor Tr1b is turned on when a voltage higher than the voltage VTb is applied to the gate, and is turned off when a voltage lower than the voltage VTb is applied to the gate. The transistors Tr2b and Tr3b are turned off when a voltage higher than the voltage VTb is applied to the gate, and are turned on when a voltage lower than the voltage VTb is applied to the gate. In this way, it is preferable that the transistor having p-channel polarity and the transistor having n-channel polarity be turned off when one is on, and the other is turned on when one is off. On state.

In the following description, for the voltage applied to the gates of the transistors Tr1b to Tr3b, the logic level lower than the voltage VTb is referred to as the "L" level, and the voltage higher than the voltage VTb is referred to as the "H "Level.

In addition, the inverters INV1b and INV3b can switch signals output from the output terminal based on the signal input to the input terminal under the voltage VTb similarly to the transistors Tr1b to Tr3b. More specifically, the inverters INV1b and INV3b can also be inputted with the “L” level at the input terminal. The output terminal outputs the "H" level. When the input terminal is input with the "H" level, the output terminal outputs the "L" level.

2.2 Operation of power protection circuit

Next, the operation of the power supply protection circuit of the semiconductor device of the second embodiment will be described.

FIG. 14 is a timing chart for explaining the operation of the power protection circuit of the second embodiment. FIG. 14 schematically illustrates an operation of the power protection circuit 13 when a surge is generated and when power is constantly supplied as an example.

As shown in FIG. 14, the operation before time T10 is the same as that of the first embodiment, so the description is omitted.

At time T10, a surge is generated, so the voltage of the pad P1 rises sharply, and then gradually approaches the voltage VSS. The node N1 is charged into the capacitor C1 in response to the surge, so the voltage slowly rises, but decreases again as the voltage of the pad P1 decreases. Therefore, the node N1 remains at the "L" level during the operation period when the surge is generated.

Along with this, the inverter INV1b outputs a "H" level to the node N2. Therefore, the "H" level output from the inverter INV1b is input to the gate of the transistor Tr1b and the input terminal of the inverter INV3b.

The inverter INV3b outputs the "L" level by being input to the "H" level. The "L" level output from the inverter INV3b is input to the gate of the transistor Tr2b, so that the transistor Tr2b is turned on.

The transistor Tr1b is turned on when the "H" level is input. The voltage of the node N5 follows the action of the node N6 by being electrically connected to the node N6 and the pad P2. However, the voltage of the node N5 is between the voltage VSS and the voltage VDD, so that the transistor Tr3b can be formed. The voltage is the ON state. That is, the node N5 becomes the "L" level.

In this way, since the transistors Tr2b and Tr3b are both kept on during the operation period when the surge is generated, the on current Is flows from the transistor P1 toward the solder pad P2 with the transistors Tr2b and Tr3b as current paths.

On the other hand, during normal operation, the node N1 reaches the voltage VDD with the capacitor C1 being fully charged. That is, the node N1 becomes "H" level.

When the node N1 becomes the "H" level, the inverter INV1b outputs the "L" level. Therefore, the "L" level output from the inverter INV1b is input to the gate of the transistor Tr1b and the input terminal of the inverter INV3b.

The inverter INV3b outputs the "H" level by being input to the "L" level. The "H" level output from the inverter INV3b is input to the gate of the transistor Tr2b, so that the transistor Tr2b is turned off.

The transistor Tr1b is turned off by being input with the "L" level, and the node N5 is electrically cut off from the pad P2, but remains connected to the node N6 through the resistor R2b. At this time, the voltages at the nodes N5 and N6 become the voltage V2. The magnitude of the voltage V2 is between the voltages VDD and VSS, and is greater than the voltage VTb ("H" level), for example. When the gate sizes of the transistors Tr2b and Tr3b are equal, the voltage V2 becomes, for example, about VDD / 2. Therefore, the transistor Tr3b is turned off.

By operating as described above, in the power supply protection circuit 13, during the normal operation period, the transistors Tr2b and Tr3b are both turned off, thereby preventing the on-current Is from flowing. The voltages at the nodes N5 and N6 are maintained at the voltage V2.

2.3 Effects of this embodiment

According to the second embodiment, the first end of the transistor Tr1b is connected to the pad P2, the second end is connected to the node N5, and the gate is connected to the node N2. Node N2 becomes on time when node N1 is at the "L" level The "H" level becomes the "L" level when the node N1 is at the "H" level. That is, when the transistor Tr1b is at the "L" level, the transistor Tr1b is turned on by inputting the "H" level to the gate. Thereby, the node N5 is electrically connected to the pad P2 during the operation period when the surge is generated. Therefore, the "L" level can be input to the gate of the transistor Tr3b, and the transistor Tr3b can be turned on. On the other hand, when the node N1 is at the "H" level, an "L" level is input to the gate of the transistor Tr1b, and the state is turned off. Thereby, during the normal operation period, the node N5 is electrically cut off from the pad P2. Therefore, the "H" level can be input to the gate of the transistor Tr3b, and the transistor Tr3b can be turned off.

In addition, the resistor R2b electrically connects the node N5 and the node N6. Thereby, during the normal operation period, the voltage of the node N5 is maintained at the voltage of the node N6. The node N6 is an intermediate node between the transistors Tr2b and Tr3b, and therefore becomes a voltage V2 which is an intermediate potential between the voltage VDD and the voltage VSS. Therefore, the gate and back gate of the transistor Tr3b can be made to the voltage V2.

The inverter INV3b includes an input terminal connected to the node N2 and an output terminal connected to the gate of the transistor Tr2b. Accordingly, the inverter INV3b outputs the "L" level when the node N1 is at the "L" level, and outputs the "H" level when the node N1 is at the "H" level. Therefore, the transistor Tr2b can be turned on during the operation period when a surge is generated, and the transistor Tr2b can be turned off during the normal operation period.

Therefore, when the polarity of the transistor through which the on-current Is flows is p-channel, the transistors Tr2b and Tr3b can be operated in the same manner as in the first embodiment. Therefore, the same effect as that of the first embodiment can be produced.

2.4 Variations of the second embodiment

The semiconductor device according to the second embodiment is not limited to the above example, and various changes can be applied.

2.4.1 First modification

For example, the power protection circuit 13 may include a transistor instead of the resistor R2b.

Fig. 15 is a circuit diagram showing a configuration of a power protection circuit according to a first modification of the second embodiment. As shown in FIG. 15, the transistor Tr4b includes a first terminal connected to the node N5, a second terminal connected to the node N6, and a gate connected to the node N2. The transistor Tr4b has, for example, a p-channel polarity.

The transistor Tr4b is turned off when the "H" level is supplied to the node N2, that is, when the surge is generated. Thereby, the node N5 can be electrically cut off from the node N6, and the voltage supplied to the transistor Tr3b can be more stable. The transistor Tr4b is turned on when the "N" level is supplied to the node N2, that is, during the normal operation period. Thereby, the node N5 can be electrically connected to the node N6 when the switching current Is does not flow in the transistor Tr3b. Therefore, the potential of the gate of the transistor Tr3b can be maintained at the intermediate potential V2 of the pads P1 and P2, and further, the leakage current can be reduced.

2.4.2 Second modification

The power supply protection circuit 13 is not limited to having a timer function based on the RC time constant as a trigger circuit, and may include other trigger circuits having no timer function. FIG. 16, FIG. 17, and FIG. 18 are circuit diagrams showing a configuration of a power protection circuit according to a second modified example of the second embodiment.

FIG. 16 shows an example in which a plurality of diodes D1 connected in series are used instead of the capacitor C1. As shown in FIG. 16, the plurality of diodes D1 include an input terminal (anode) connected to the node N1 and an output terminal (cathode) connected to the pad P2. The plurality of diodes D1 are set, for example, to the on state when the voltage of the pad P1 rises to such an extent that the on-current Is must flow to protect the internal circuit 14 from ESD damage.

With this configuration, when the plurality of diodes D1 are turned on, the voltage at the node N1 decreases due to the voltage drop generated by the resistor R1, and becomes the "L" level. With this, you can make The transistors Tr2b and Tr3b are turned on, and a turn-on current Is flows. When the voltage of the pad P1 returns to the normal operating range, the plurality of diodes D1 are turned off. Therefore, the voltage drop generated by the resistor R1 basically disappears, and the voltage at the node N1 becomes the "H" level. Thereby, the on-current Is can be stopped.

FIG. 17 shows an example in which a Zener diode D2 is used instead of the capacitor C1. As shown in FIG. 17, the Zener diode D2 includes an input terminal (cathode) connected to the node N1 and an output terminal (anode) connected to the pad P2. The zener diode D2 is set to, for example, a falling state when the voltage of the pad P1 rises to such an extent that the on-current Is must flow to protect the internal circuit 14 from ESD damage.

By constituting in this way, when the Zener diode D2 becomes a falling state, the voltage at the node N1 decreases due to the voltage drop generated by the resistor R1, and becomes the "L" level. Thereby, the transistors Tr2b and Tr3b can be turned on, and the on-current Is can flow. In addition, when the voltage of the pad P1 returns to the normal operating range, the Zener diode D2 recovers from the falling state. Therefore, the voltage drop generated by the resistor R1 basically disappears, and the voltage at the node N1 becomes the "H" level. Thereby, the on-current Is can be stopped.

FIG. 18 shows an example in which a transistor Tr5 and a resistor R3 are used instead of the capacitor C1. As shown in FIG. 18, the transistor Tr5 includes a first terminal connected to the node N1 and a second terminal connected to the pad P2. The resistor R3 includes a first terminal connected to the gate of the transistor Tr5 and a second terminal connected to the pad P2. The transistor Tr5 is set in the same manner as the Zener diode D2 in FIG. 17, for example, when the voltage of the pad P1 rises to a level where the on-current Is must flow to protect the internal circuit 14 from ESD damage. .

By constituting in this way, when the transistor Tr5 is in a falling state, the voltage at the node N1 is reduced due to the voltage generated by the resistor R1, and becomes the "L" level. With this, the transistor can be made Tr2b and Tr3b are turned on, and a turn-on current Is flows. In addition, when the voltage of the pad P1 returns to the normal operating range, the transistor Tr5 recovers from the falling state. Therefore, the voltage drop generated by the resistor R1 basically disappears, and the voltage at the node N1 becomes the "H" level. Thereby, the on-current Is can be stopped.

2.4.3 Third modification

In addition, for example, the power protection circuit 13 may be provided with an RC timer in a direction opposite to the pads P1 and P2.

FIG. 19 is a circuit diagram showing a configuration of a power protection circuit according to a third modified example of the second embodiment. FIG. 19 shows an example in which the capacitor C1a and the resistor R1a are used instead of the resistor R1 and the capacitor C1.

As shown in FIG. 19, the capacitor C1a includes a first terminal connected to the pad P1 and a second terminal connected to the node N1. The resistor R1a includes a first terminal connected to the node N1 and a second terminal connected to the pad P2. The resistor R1a and the capacitor C1a function as an RC timer, and operate based on a time constant determined by the resistance value and the capacitance of each of them. Specifically, the voltage of the node N1 follows the voltage of the pad P2 with a time delay based on the time constant.

In a third modification of the second embodiment, the power supply protection circuit 13 further includes an inverter INV2b. An input terminal and an output terminal of the inverter INV2b are connected to an output terminal and a node N2 of the inverter INV1b, respectively.

Fig. 20 is a timing chart showing the operation of a power protection circuit according to a third modified example of the second embodiment.

As shown in FIG. 20, a surge is generated at time T10. As a result, the voltage of the pad P1 rises sharply, and then gradually approaches the voltage VSS. Node N1 follows the voltage rise of pad P1. Therefore, the node N1 remains at the "H" level during the operation period when the surge is generated. The inverter INV1b then outputs "L" level, the inverter INV2b outputs "H" level. The "H" level output from the inverter INV2b is input to the gate of the transistor Tr1b and the input terminal of the inverter INV3b.

Thereby, the transistors Tr2b and Tr3b are both turned on, and the on current Is flows with the transistors Tr2b and Tr3b as current paths, and flows from the pad P1 toward the pad P2. In addition, since the operations of the transistors Tr1b to 3b and the inverter INV3b are the same as those of FIG. 14 of the second embodiment, the description is omitted.

By operating in the above manner, the power supply protection circuit 13 stops the on-current Is flowing during the operation period when the surge is generated.

During normal operation, the voltage at the node N1 becomes the voltage VSS. That is, the node N1 becomes the "L" level during normal operation. Thereby, the inverter INV1b outputs the "H" level, and the inverter INV2b outputs the "L" level. Therefore, the "L" level output from the inverter INV2b is input to the gate of the transistor Tr1b and the input terminal of the inverter INV3b.

As a result, the transistors Tr2b and Tr3b are both turned off, and the on-current Is does not flow. In addition, since the operations of the transistors Tr1b to 3b and the inverter INV3b are the same as those of FIG. 14 of the second embodiment, the description is omitted.

By operating in the above manner, in the power supply protection circuit 13, the on-current Is does not flow during the normal operation period. The voltages at the nodes N5 and N6 are maintained at the voltage V2.

Thus, even when the RC timer is mounted in the reverse direction, the same signals as those of the second embodiment can be input to the transistors Tr2b and Tr3b. Therefore, the same effect as that of the second embodiment can be produced.

In addition, this modification can be similarly applied to the second modification. That is, the trigger circuit is not limited to having a timer function based on the RC time constant, and other trigger circuits that do not have a timer function may be installed in the opposite direction. Specifically, in FIG. 19 of this modification, it may be configured The capacitor C1a is replaced by a plurality of diodes, a Zener diode, and a transistor. In this case, the same effect as that of this modification can be produced.

5. Other

In addition, in each embodiment and each modification, the following matters can also be applied.

For example, an example in which a three-level inverter is connected in series to the transistor Tr3 of the first embodiment and the transistor Tr2b of the third modification of the second embodiment has been described, but it is not limited to this. For example, an arbitrary odd-numbered inverter may be connected in series to the transistor Tr3 of the first embodiment and the transistor Tr2b of the third modification of the second embodiment.

In addition, the example in which the transistor Tr3 of the third modification of the first embodiment and the transistor Tr2b of the second embodiment are connected in series with a two-stage inverter has been described, but the invention is not limited to this. For example, an arbitrary even-numbered inverter may be connected in series to the transistor Tr3 of the third modified example of the first embodiment and the transistor Tr2b of the second embodiment.

Although several embodiments of the present invention have been described, these embodiments are proposed as examples, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the invention described in the scope of patent application and its equivalent scope.

[Related applications]

This application has priority over Japanese Patent Application No. 2017-127992 (application date: June 29, 2017). This application contains all contents of the basic application by referring to the basic application.

Claims (18)

A power protection circuit includes: a first pad that is supplied with a first voltage; a second pad that is supplied with a second voltage different from the first voltage; and a first transistor that includes an electrical connection to The first end of the first pad is electrically connected to the second end and back gate of the first node, and the gate is electrically connected to the second node; the second transistor includes an electrical connection to the above. The first end of the first node is electrically connected to the second end of the second pad and the back gate; and a switching circuit that, when the first logic signal is input to the gate of the second transistor, the above The second node is electrically connected to the first pad, and when the gate of the second transistor is input with a second logic signal having a logic level opposite to that of the first logic signal, the second The node is electrically disconnected from the first pad and electrically connected to the first node. For example, the power protection circuit of claim 1, wherein the first transistor and the second transistor have the same polarity. For example, the power protection circuit of claim 2, wherein the switching circuit includes a third transistor, and the third transistor includes a first terminal electrically connected to the first pad and a second terminal electrically connected to the second node. The two terminals have different polarities from the first transistor and the second transistor. If the power supply protection circuit of item 3 is requested, wherein the gate input and The logic signals input to the gates of the second transistor are inverted logic signals. For example, the power protection circuit of claim 4, wherein the switch circuit further includes a first resistor, and the first resistor includes a first terminal electrically connected to the first node and a second terminal electrically connected to the second node. . For example, the power protection circuit of claim 4, wherein the switch circuit further includes a fourth transistor, and the fourth transistor includes a first terminal electrically connected to the first node and a second terminal electrically connected to the second node. The terminal and the gate are electrically connected to the third transistor gate. The power protection circuit of claim 6, wherein the fourth transistor has a polarity different from that of the third transistor. For example, the power protection circuit of claim 1, wherein the first voltage is greater than the second voltage. For example, the power protection circuit of claim 1, wherein the first voltage is smaller than the second voltage. If the power protection circuit of claim 3 further comprises: a trigger circuit, which is electrically connected between the first pad and the second pad, and outputs a trigger signal to the third node; and a signal control circuit, which According to whether the voltage value of the trigger signal exceeds a certain threshold, the logic level of the logic signal input to the gate of the second transistor and the gate of the third transistor is switched. The power supply protection circuit according to claim 10, wherein the trigger circuit includes: a second resistor including a first terminal electrically connected to the first pad and a second terminal electrically connected to the third node; and The capacitor includes a first terminal electrically connected to the third node and a second terminal electrically connected to the second pad. The power supply protection circuit according to claim 10, wherein the trigger circuit includes: a second resistor including a first terminal electrically connected to the first pad and a second terminal electrically connected to the third node; and The fifth transistor includes a first terminal electrically connected to the third node and a second terminal electrically connected to the second pad. The power supply protection circuit according to claim 10, wherein the trigger circuit includes: a second resistor including a first terminal electrically connected to the first pad and a second terminal electrically connected to the third node; and The diode includes a first end electrically connected to the third node and a second end electrically connected to the second pad. For example, the power protection circuit of claim 13, wherein the diode includes a Zener diode. The power supply protection circuit of claim 10, wherein the trigger circuit includes: a capacitor including a first terminal electrically connected to the first pad, and a second terminal electrically connected to the third node; and a second terminal The resistor includes a first terminal electrically connected to the third node and a second terminal electrically connected to the second pad. For example, the power protection circuit of claim 10, wherein the trigger circuit includes: a fifth transistor, which includes a first terminal electrically connected to the first pad and a second terminal electrically connected to the third node; A second resistor includes a first terminal electrically connected to the third node and a second terminal electrically connected to the second pad. The power supply protection circuit according to claim 10, wherein the trigger circuit includes a diode including a first terminal electrically connected to the first pad and a second terminal electrically connected to the third node; and The second resistor includes a first terminal electrically connected to the third node and a second terminal electrically connected to the second pad. The power protection circuit according to claim 17, wherein the diode includes a zener diode.