JPS6043840A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable to simply set the output state of an output circuit to be used for a direct current characteristic test by a method wherein a switching gate circuit and a simple circuit such as a test circuit, which is used in common for all output circuits, are added. CONSTITUTION:An internal logic circuit LOG is constituted of a gate array formed by a master slice system. An output signal formed by the internal logic circuit LOG is transmitted to an output circuit OB through a switching gate circuit G in order to facilitate the direct current characteristic test of the output circuit OB. The other input terminal of the switching gate circuit G and its switching control terminal are respectively supplied in common with a signal formed by a test circuit TST. The test circuit TST is supplied with the test mode signal utilizing an aging inable signal terminal AE.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique effective for testing DC characteristics of semiconductor integrated circuit devices, such as CMO3 integrated circuit devices constituting a gate array.

[Background technology]

C of CMOS gate array etc. consisting of many gate circuits
When testing direct current characteristics of an MO3 integrated circuit device, it is necessary to set the output signal level of the output circuit to a high level or low level, or to set the device to a high impedance state to measure leakage current. However, in a gate array whose internal circuit is made up of a large number of gate circuits, its logical configuration becomes complex, so if you try to specify the level of the output terminal to be tested based on a combination of input signals, you will have to create a huge number of test patterns. It will be necessary to form. This results in a drawback that the number of testing steps becomes enormous.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that allows DC characteristics testing of an output circuit to be easily performed using a simple circuit configuration.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a switching gate circuit is provided between the output terminal of the internal logic circuit that forms the signal to be output and the input terminal of the output circuit, and a storage means that receives and stores signals input in series from a predetermined external terminal. The output state of the output circuit is determined by decoding the stored information stored by the storage means and forming a test signal and a switching signal to be supplied to the switching gate circuit. .

〔Example〕

FIG. 1 shows a block diagram of an embodiment in which the present invention is applied to a CMOS gate array. In the figure, each circuit block surrounded by a dotted line is formed on a semiconductor substrate such as single crystal silicon by a known CMO3 integrated circuit manufacturing technique. Although not particularly limited, the CMO3 integrated circuit device VLSI of this embodiment consists of a gate array consisting of about 20 gates, and each circuit function is configured by a master slice method.

The internal logic circuit LOG is composed of a gate array formed by the master slice method as described above.

The signal to be output formed by this internal logic circuit LOG is
The signal is transmitted to the output circuit OB via the switching gate circuit G. That is, one input terminal of the switching gate circuit G is supplied with a signal to be output formed by the internal logic circuit LOG. And, although not particularly limited, the other input terminal of these switching gate circuits G,
The switching control terminal is connected to a test circuit T, which will be explained next.
Signals formed by the STs are commonly supplied to each.

Although not particularly limited, the test circuit TST is supplied with its test mode signal using the aging enable signal terminal AE. In addition, by using the predetermined input terminal INm (No. 8), the test circuit TST is prevented from responding excessively in the lightning operation state. This can be explained with reference to FIG. This will become clearer from the explanation of the specific circuit.

FIG. 2 shows the output circuit OB and the switching gate circuit G.
A circuit diagram of a specific embodiment of the TST is shown.

The output circuit OB is composed of the following circuits.

In other words, p-channel MO3F with push-pull shape
An output stage circuit is configured by ETQ L and n-channel MO3FETQ2. Above output MO3FETQI
Alternatively, depending on the alternative ON state of Q2, in addition to sending out a high level or low level output signal, the above MO3F
The following gate circuit and inverter are provided to provide a three-state output function in which both ETQI and Q2 are turned off and the output is in a high impedance state.

The output signal of the Nant gate circuit G1 is a p-channel MO
It is transmitted to the gate of 3FETQI. On the other hand, the output signal of NOR gate circuit G2 is
will be communicated to the gate. Said gate circuit G1. ,G,2
A signal to be output through an inverter IVI is commonly supplied to one input terminal of the inverter IVI. Also, internal logic circuit L
The output enable signal EN formed by OG and the aging enable signal AE supplied from E to the external terminal are supplied to a NOR gate circuit G6. The output signal of the NOR gate circuit G6 is supplied to the other input terminal of the NOR gate circuit G1 through the inverter lV3.

Further, the output signal of the inverter IV3 is supplied to the input terminal of the inverter IV2, and the output signal thereof is supplied to the other input terminal of the NOR gate circuit G2.

The switching gate circuit G includes an OR gate circuit G3 and an AND gate circuit G4. It is composed of G5 and inverter IV4. That is, the signal formed by the internal logic circuit LOG to be output is supplied to one input terminal of the AND gate circuit G4. In addition, a test circuit T to be described later
The signal T formed by ST is connected to the AND gate circuit G5.
is fed to one input of In order to selectively switch these gate circuits G4 and G5, the test circuit TST
The switching signal C formed by the above is supplied to the other input terminal of the AND gate circuit G5.

Further, the switching signal C is supplied to the other input terminal of the AND gate circuit G4 through the inverter IV4.

Although not particularly limited, the test circuit TST utilizes a counter circuit C0UNT that forms a pulse signal from the aging enable terminal AE. Although not particularly limited, the most significant bit signal of this counter circuit C0UNT is used as the switching signal C. Further, a decoder circuit DCH which receives the remaining bit signals of the counter circuit C0NT and detects a specific bit pattern generates a signal T which determines the output level during testing. Although not particularly limited, in order to prevent the test circuit TST from responding excessively and entering the test mode in the normal operating state, the signal at the predetermined input terminal INm is set to the counter circuit cour<T. Terminal R
supplied to

The other output circuits OB and switching gate circuits G are also configured by circuits similar to those described above, and the signals T and D formed by the aging enable signal AE and the test circuit TST are applied to these output circuits OB and switching gate circuits G. Commonly supplied.

Next, the operation for testing the DC characteristics of this example circuit will be explained.

A plurality of pulses are input from the external terminal AE, and the most significant bit of the signal C is set to logic "1", thereby fixing the terminal AE to logic "1". The AND gate circuit G5 is opened by the logic "1" of the signal C, whereas the AND gate circuit G4 is opened by the logic "O" of the inverted signal passed through the inverter IV4.
'' is supplied, so that it is closed. As a result, the signal T formed by the test circuit TST is supplied to the input terminal of the output circuit OB. Also, the logic of the terminal Aπ is set to "1"; Since the output enable signal EK formed by the internal logic circuit LOG is also set to logic "1", if the signal T is logic "0", the output signals of the Nand gate circuit G1 and the NOR gate circuit G2 are both logic "0". Therefore, p-channel MO3FETQI
turn on, n-channel MOS FET Q
2 is turned off. Thereby, the bar f level for the DC characteristic test can be sent from the output terminal OUT.

Also, due to the counting operation of the counter circuit C0UNT,
By setting the output signal T of the decoder circuit DCH to the logic "1", the output signals of the NOR gate circuit G1 and the Nant gate circuit G2 both become the logic "1", so that the p-channel MO5FET QI is turned off. The n-channel MO3FET Q2 can be turned on. Thereby, a low level signal for DC characteristic testing can be sent from the output terminal OUT.

When both MO3-FETQI and G2 are turned off to bring the output into a high impedance state,
The external terminal AE may be set to logic "O". In this case, the output signal of the Nant gate circuit G1 becomes logic "1" due to its logic "0" regardless of the signal 'r, and p
Channel MO3FETQ1 is turned off. Also,
By passing the impark IV3, the signal AE is inverted and becomes logic "1" and is supplied to the NOR gate circuit G2. Therefore, the output signal of the NOR gate circuit G2 becomes logic "0" regardless of the signal T, turning the n-channel MO3FET Q2 off. Thereby, a DC characteristic test such as leakage current measurement of the output terminal OUT can be performed.

Note that the external terminal AE is used during aging, and is fixed to a logic pulse 1" in the normal operating state. Therefore, in the normal operating state, the counter circuit C0UNT performs its counting operation. Therefore, the test mode state described above will not occur.Also, the counting operation is performed in response to noise etc. °ζ is also reset every time the signal from the input terminal INm arrives, so the above-mentioned test mode state does not occur. It is reset before the bit pattern required to enter the test mode is reached.
This can prevent the ST from responding excessively.

〔effect〕

By simply adding a simple circuit such as an ill switching gate circuit and a test circuit commonly used for all output circuits, it is possible to easily set the output state of the output circuit for DC characteristics testing. . As a result, it is not necessary to form a complicated input test pattern, so that it is possible to improve test efficiency.

(2) Multiple types of tests can be performed without increasing the number of external terminals by using external terminals that are not used in normal operating conditions and by forming a test mode signal with a counter circuit, such as the aging enable Nishikishi. The effect is that mode control can be performed.

(3) By commonly supplying the test signals formed by the test circuit to the output circuits, it is possible to simultaneously perform DC characteristic tests on a plurality of output circuits according to the test capability of the tester.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the Examples described in F, and it is understood that various changes can be made without departing from the gist thereof. Needless to say. For example, the circuit that forms the test mode signal may utilize a shift register. In addition, a dedicated test terminal is provided.1. It may also be possible to perform a test operation as described above.

In this case, if a counter circuit is used, only one terminal needs to be added.

[Application field]

In the above explanation, the invention made by the present inventor was mainly applied to the CMOS gate array, which is the technical field that is the background of the invention, but the invention is not limited to this. The present invention can be widely used in logic integration devices such as gate arrays made up of insulated gate field effect transistors (insulated gate field effect transistors) or bipolar transistors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the invention, and FIG. 2 is a circuit diagram showing a specific embodiment thereof. LOG: Internal logic circuit, C: Switching gate circuit,
OB...output circuit, T s'r..., test circuit, C
0UNT: Counter circuit, DCR: Decoder circuit

Claims (1)

[Claims] 1. A switching gate circuit that selectively transmits an output signal formed by an internal logic circuit and a test signal to an input terminal of an output circuit, and a switching gate circuit that selectively transmits an output signal formed by an internal logic circuit and a test signal to an input terminal of an output circuit, and a signal that is input in series from a predetermined external terminal. A semiconductor device characterized in that it is provided with a storage means for receiving and storing a signal, and decoding the stored information stored by the storage means to form a test signal and a switching signal to be supplied to the switching gate circuit. Integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the storage means is a counter circuit. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the predetermined external terminals share an aging enable signal heir that controls the output state of the output circuit. 4. The second or third claim characterized in that the input signal supplied from a specific input signal terminal is commonly applied to the input terminal of the counter circuit.
The semiconductor integrated circuit device described in .