JPH04343079A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable execution of an electrical test of an input/output or three- state terminal without setting the state of the terminal by an actual operation, by providing a logic circuit for a test which set the state of the input/output terminal on the basis of a test signal. CONSTITUTION:When logic values of test signals T1 and T2 are made to be 0, both of a P-type transistor 8 and an N-type transistor 9 are turned OFF and execution of a test of a leak current thereof and an input leak current of an input buffer 11 is enabled. When the signal T1 is made to be 0 and the signal T2 to be 1, the transistor 8 is turned ON, while the transistor 9 is turned OFF, and an output current of the transistor 8 can be tested. When the signal T1 is made to be 1 and the signal T2 to be 0, moreover, the transistor 8 is turned OFF and the transistor 9 ON irrespective of logic values of signals G and X determining gate levels of the transistors 8 and 9, when an internal circuit is in a state of operation, and thus an output current of the transistor 9 can be tested. Accordingly, the test of an input/output terminal or a three-state terminal can be executed without setting the state of the terminal by an actual operation.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electrical testing of terminals of semiconductor integrated circuits.

0002

2. Description of the Related Art Conventionally, when electrical testing of input/output bidirectional or three-state terminals is performed, a device is set to an actual operating state and is actually operated. For example, when performing an input leak test on an input/output terminal, you can actually operate the device, hold the operation at the timing when it enters the input state, connect a DC unit to the terminal, and measure the input leak current. Ta.

0003

[Problems to be Solved by the Invention] However, as shown above, in the conventional technology, electrical testing of input/output terminals or 3-state terminals is performed under actual operating conditions, but the test is complicated and practical. Testing time also increases to bring the device into operation.

The present invention enables electrical testing of input/output terminals or 3-state terminals without putting the semiconductor integrated circuit into an actual operating state, and reduces test costs by facilitating testing and shortening test time. purpose.

[0005]

[Means for solving the problems] A plurality of input/output terminals (input terminals, output terminals, or input/output bidirectional terminals) according to the present invention
A semiconductor integrated circuit having a test signal input terminal,
The present invention is characterized by further comprising a test logic circuit that sets the state of the input/output terminal based on the test signal input from the test signal input terminal.

[0006]

[Operation] By using the present invention, the terminal state (directivity, output state) can be set by simply inputting an electrical signal to the test signal input terminal after power is applied to the semiconductor integrated circuit.

[0007]

[Example] The present invention will be explained in detail below based on an example.

FIG. 1 is a circuit diagram of an embodiment of the present invention. T1 and T2 are test signals used during electrical testing, which are input from the outside, and in this embodiment, C
Determine the gate levels of transistors 8 and 9 in the MOS inverter. G and X are signals that determine the gate levels of the transistors 8 and 9 when the internal circuit is actually in operation. 1 is a logic circuit, 2, 3, 4, 5
is an AND gate, 6 and 7 are OR gates, 8 is a P-type transistor, 9 is an N-type transistor, 10 is an input/output bidirectional terminal, and 11 is an input buffer.

The logic circuit 1 which inputs the four signals mentioned above to the transistors 8 and 9 used in this embodiment is set according to the following procedure.

First, in order to set the terminal to a high impedance state, the logic values of the P-type transistor 8 and N-type transistor 9 are both set to be in the off state when the logic values of T1 and T2 are both set to 0. (state 1). next,
In order to set the terminal to an H level output state, if the logical value of T1 is 0 and the logical value of T2 is 1, the P-type transistor 8 is set to be in the on state and the N-type transistor 9 is to be in the off state. (State 2). Next, in order to set the terminal to the L level state, when the logical value of T1 is set to 1 and the logical value of T2 is set to 0, the P-type transistor 8 is set to be in the off state and the N-type transistor 9 is to be in the on state. (State 3).

[0011] By the above procedure, the terminal state can be set without actually operating the internal circuit during an electrical test. Next, in order to provide an actual operating state, when the logical value of T1 and T2 is set to 1, if the logical value of G is 0, the output is determined by the logical value of X, and if the logical value of G is 1 , transistors 8 and 9 are both turned off and set to a high impedance state (state 4). Table 1 shows a logic value table of a logic circuit that performs the above operation.

0012

[Table 1]

The logical formula for turning on transistors 8 and 9 is: P=inverted T2+T1・T2・inverted X+T1・T2・
G・X…(1) N=T1・Inverted T2+T1・T2
・Reversal G・Reverse X... (2).

The logic circuit 1 includes AND gates 2, 3,
4 and 5 and OR gates 6 and 7, and the input signal is input from the OR gate 6 to the gate of the P-type transistor 8, and from the OR gate 7 to the gate of the N-type transistor 9.

Next, the operating state will be explained.

State 1 The logic values of both T1 and T2 are set to 0. At this time, X, G
Regardless of the logical value of , both P-type transistor 8 and N-type transistor 9 are in the off state. That is, at this time P
It becomes possible to perform electrical tests on the leakage currents of the type transistor 8 and the N-type transistor 9 and the input leakage current of the input buffer 11.

State 2 The logical value of T1 is set to 0, and the logical value of T2 is set to 1. At this time G
, X, the P-type transistor 8 is on and the N-type transistor 9 is off. That is, at this time, it becomes possible to conduct an electrical test of the output current of the P-type transistor 8.

State 3 The logical value of T1 is set to 1, and the logical value of T2 is set to 0. At this time, regardless of the logical values of X and G, the P-type transistor 8 is turned off and the N-type transistor 9 is turned on. That is, at this time, it becomes possible to conduct an electrical test of the output current of the N-type transistor 9.

State 4 The logical values of T1 and T2 are both fixed to 1. At this time, if the logical value of G is 0, the output is determined by the logical value of X,
When the logical value of G is 1, both the P-type transistor 8 and the N-type transistor 9 are turned off. The states of the P-type transistor 8 and N-type transistor 9 change depending on the logical values of X and G, and state 4 indicates an actual operating state.

The case where an electrical test is also performed when the terminal is in three states has been described above, but when conducting an electrical test only for the input/output state, the logic value of G is fixed to 0. Furthermore, the present invention is characterized by setting an input state, an output state, or a high impedance state and an actual operating state, and is not limited to this embodiment.

[0021]

[Effects of the Invention] As explained in detail above, by using the present invention, it is possible to
Since electrical testing of input/output or 3-state terminals can be performed, electrical testing can be easily performed, and test costs can be reduced by shortening test time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

[Explanation of symbols]

1 Logic circuit 2, 3, 4, 5 And gate 6,7 Orgate 8 P-type transistor 9 N-type transistor 10 Input/output bidirectional terminal 11 Input buffer

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having a plurality of input/output terminals, the state of the input/output terminal is set based on a test signal input terminal and a test signal input from the test signal input terminal. A semiconductor integrated circuit characterized in that it is provided with a logic circuit for testing.