JPS61248298A - Prom circuit - Google Patents

Prom circuit

Info

Publication number
JPS61248298A
JPS61248298A JP60091455A JP9145585A JPS61248298A JP S61248298 A JPS61248298 A JP S61248298A JP 60091455 A JP60091455 A JP 60091455A JP 9145585 A JP9145585 A JP 9145585A JP S61248298 A JPS61248298 A JP S61248298A
Authority
JP
Japan
Prior art keywords
prom
connector
circuit
writing
proms
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60091455A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Takao
鷹尾 良行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60091455A priority Critical patent/JPS61248298A/en
Publication of JPS61248298A publication Critical patent/JPS61248298A/en
Pending legal-status Critical Current

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  • Read Only Memory (AREA)

Abstract

PURPOSE:To attain all kinds of writing methods by connecting all signal lines and power supply lines between PROM circuits and its reading circuit through connectors, and in case of PROM writing, separating the PROM circuit simply from its reading circuit. CONSTITUTION:In case of reading out the contents of the PROMs 1a, 1b, connector pins 12, 15 are connected with each other by a short connector 16 to read out the contents. In case of writing data in the PROMs 1a, 1b, the connector pin 15 is separated from the short connector 16 and a PROM writing connector 20 is connected to the connector pin 15 to write the data in the PROMs. Since the PROMs are separated from the reading circuit 9 in case of writing, any influence will not be exerted upon the reading circuit 9. Thus, data can be simply written on any kinds of PROMs.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はPROM回路(プログラマブル・リード・オ
ンリ・メモリ回路)、特にその書込みに関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PROM circuit (programmable read-only memory circuit), and particularly to writing thereof.

〔従来の技術〕[Conventional technology]

第2図は、たとえばインテル社のマニュアル1sBc 
86/14/30 Single Board Com
puter f(ardwareReference 
Manual (1982年発行)の3heet 2及
び5heet 5等を簡略化して示した従来のPROM
回路のブロック図である。図において(la)、(lb
) tiそれぞれPROM を表し、図中の(アドレス
)はアドレスバス入力端子、(データ)はデータバス入
力端子、CEはチップセレクト信号入力端子、娼はプロ
グラム信号入力端子であり 、(2a)、(2b)はそ
れぞれPROM(la)、(lb)  を接続するIC
ソケット、(3)はPROM(la) 、 (lb) 
 のデータバス141はPROM(la)、(lb) 
 ヘのアドレスバス、(5)はPROM(la)、(l
b)へのチップセレクト信号、(6)はチップセレクト
信号を発生するためのアドレスデコーダ、(7)はF 
ROM (la) 、 (lb)  に対するプログラ
ム信号、(8)はCPUである。
Figure 2 shows, for example, Intel's manual 1sBc.
86/14/30 Single Board Com
puter f(ardwareReference
Conventional PROM that simplifies 3heet 2 and 5heet 5 etc. from Manual (published in 1982)
It is a block diagram of a circuit. In the figure (la), (lb
) ti each represents a PROM, (address) in the figure is an address bus input terminal, (data) is a data bus input terminal, CE is a chip select signal input terminal, and 2 is a program signal input terminal. (2a), ( 2b) are ICs that connect PROMs (la) and (lb), respectively.
Socket, (3) is PROM (la), (lb)
The data bus 141 of PROM (la), (lb)
Address bus (5) to PROM (la), (l
(6) is the address decoder for generating the chip select signal, (7) is the F
Program signals for ROM (la) and (lb), (8) is the CPU.

第2図に示す例ではPROM (la)、(lb)の読
出しがCPU (8)から行われるばかシでなく PR
OM (la)、(lb)への書込みもまたCPU(8
)から行われ、したがってCPU (8)はPROM(
la) 、 (lb)  に対しデータ信号、アドレス
信号、チップセレクト信号(5)、プログラム信号(7
)を出力する。
In the example shown in Fig. 2, reading of PROMs (la) and (lb) is not done from CPU (8), but from PR
Writing to OM (la), (lb) is also done by the CPU (8
), therefore the CPU (8) is performed from the PROM (
la), (lb), data signal, address signal, chip select signal (5), program signal (7)
) is output.

PROM(la)、(lb)からの読出しについては一
般によく知られているので、第2図の装置においてPR
OM (la)、(lb)への書込みを行う場合の動作
について以下に説明する。
Reading from PROMs (la) and (lb) is generally well known, so in the device shown in FIG.
The operation when writing to OM (la) and (lb) will be described below.

CPU T8)はPROM (la)、(lb)のいず
れかのアドレス位置にデータを書込む場合にはそのアド
レス位置を示すアドレス信号をアドレスバス(4)上に
出力する。このアドレス信号のうち上位のビットはアド
レスデコーダ(6)によシブコードされてチップセレク
ト信号(5)となシ、PROM (la)、(lb)の
いずれかが選択され、アドレス信号のうちアドレスデコ
ーダ(6)に入力される上位のビットを除いたアドレス
信号はPROM (la)、(lb)に並列に入力され
、チップセレクト信号(5)によって選択された方のP
ROM内のラッチ(図示せず)により保持される。
When writing data to an address location in either PROM (la) or (lb), the CPU T8) outputs an address signal indicating the address location onto the address bus (4). The upper bit of this address signal is subcoded by the address decoder (6) and becomes a chip select signal (5), which selects either PROM (la) or (lb). The address signal excluding the upper bits input to (6) is input in parallel to PROMs (la) and (lb), and the address signal input to PROM (la) and (lb) is input to
It is held by a latch (not shown) in the ROM.

次に、CPUt81はプログラム信号(7)を出力し、
データバス(3)上にデータを出力する。チップセレク
ト信号(5)により選択されたPROMの中のアドレス
信号により定められるアドレス位置にデータバス(5)
上のデータが書込まれる。
Next, CPUt81 outputs a program signal (7),
Output data on the data bus (3). The data bus (5) is placed at the address position determined by the address signal in the PROM selected by the chip select signal (5).
The above data will be written.

また、他の書込方法としては、書込みを行うべきF R
OM″IkそのICソケットから引き抜いた上でPRO
M書込装置に接続して書込みを行う方法もある。
In addition, as another writing method, the FR to be written
OM″Ik Pull it out from the IC socket and then PRO
There is also a method of writing by connecting to an M writing device.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来のPROM回路は以上のように構成されているので
、CPU(8)からの書込みを行う時には、PROMを
読出しの場合と同様な接続状態のままにしておいて、書
込みのために必要な比較的大きな電力を与えなければな
らぬので、周辺素子を破壊するおそれがあったシ、この
周辺素子破壊等の事故を避けるためには書込方式に色々
な制限を加えなければならぬ等の問題点があった。
The conventional PROM circuit is configured as described above, so when writing from the CPU (8), the PROM is left in the same connection state as when reading, and the comparison necessary for writing is performed. Since a large amount of electric power must be applied, there is a risk of destroying peripheral elements, and in order to avoid accidents such as destruction of peripheral elements, various restrictions must be placed on the writing method. There was a point.

また書込みを行うためPROMをICソケットから抜き
取る方法では、誤挿入とかICソケットとの接触不良を
おこすおそれがある等の問題点があった。
Furthermore, the method of removing the PROM from the IC socket for writing has had problems such as incorrect insertion or poor contact with the IC socket.

この発明は上記のような問題点を解決するためになされ
たもので、PROMに対し、あらゆる種類の書込み方式
を使用することができるF ROM回路を得ることを目
的としている。
The present invention was made to solve the above-mentioned problems, and aims to provide a FROM circuit that can use all kinds of writing methods for PROM.

〔問題点を解決するための手段〕[Means for solving problems]

この発明では、PROM回路とその読出回路との間のす
べての信号線及び電源線をコネクタを経て接続するよう
にし、PROM書込みの場合はPROM回路をその読出
し回路から容易に分離できるようにした。
In this invention, all signal lines and power supply lines between a PROM circuit and its readout circuit are connected through connectors, so that the PROM circuit can be easily separated from its readout circuit in the case of PROM writing.

〔作用〕[Effect]

PROM書込みの場合はPROM回路をその読出し回路
から分離した上で書込みを行うので、あらゆる種類の書
込み方式が可能となる。
In the case of PROM writing, since writing is performed after separating the PROM circuit from its reading circuit, all kinds of writing methods are possible.

〔実施例〕〔Example〕

以下この発明の実施例を図面について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図はこの発明の一実施例を示すブロック図で、第1
図において(la)、(lb)はそれぞれ第2図の同一
符号と同−又は相当部分を示し、(9)はPROM(l
a)。
FIG. 1 is a block diagram showing one embodiment of the present invention.
In the figure, (la) and (lb) indicate the same or corresponding parts as the same reference numerals in Fig. 2, and (9) indicates the PROM (l
a).

(1b)の読出しを行う読出回路、(10)は読出し回
路からの信号線で、第2図の回路のデータバス(3)、
アドレスバス(4)、チップセレクト信号線(5)に相
当する信号を含み、(11)はPROM (la)、(
lb)に対する電源線、(12)は信号線(10)と電
源線(11)の接続された読出回路側のコネクタピン、
(13)は信゛号線(10)に対応しPROM (la
)、(lb)に接続される信号線、(14)は電源線(
11)に対応しPROM (la)、(lb)に接続さ
れる電源線、(15)は信号線(13)と電源線(14
)の接続されたPROM側のコネクタビン、(16)は
読出回路側のコネクタピン(12)とPROM側のコネ
クタビン(15)とを接続する短絡コネクタ、(17)
はPROMに書込みを行うPROM書、込装置、(18
)はPROM書込装置(17)から出力されるPROM
書込み信号線、(19)はPROM書込装置(17)か
ら出力されるPROM書込み電源線、(20)はPRO
M書込み信号線(18)、PROM書込み電源線(19
)が接続されるPROM書込み用コネクタである。
(1b) is a readout circuit that performs readout, (10) is a signal line from the readout circuit, and the data bus (3) of the circuit in FIG.
Contains signals corresponding to address bus (4) and chip select signal line (5), (11) is PROM (la), (
(12) is the connector pin on the readout circuit side to which the signal line (10) and power line (11) are connected;
(13) corresponds to the signal line (10) and PROM (la
), (lb) are connected to the signal line, (14) is the power supply line (
11) and the power line connected to PROM (la) and (lb), (15) is the signal line (13) and power line (14).
) is connected to the connector pin on the PROM side, (16) is a short-circuit connector that connects the connector pin (12) on the readout circuit side and the connector pin (15) on the PROM side, (17)
is a PROM writing and programming device (18) that writes to PROM.
) is the PROM output from the PROM writing device (17)
Write signal line, (19) is PROM write power supply line output from PROM writing device (17), (20) is PRO
M write signal line (18), PROM write power supply line (19)
) is the PROM write connector to which it is connected.

PROM (la)、(lb)を読出す場合は、コネク
タビン(12)と(15)とは短絡コネクタ(16)に
よって接続されており、読出しが行われる。
When reading PROMs (la) and (lb), the connector bins (12) and (15) are connected by a shorting connector (16), and reading is performed.

PROM (la)、(lb)に対して書込みを行うと
きはコネクタビン(15) e短絡コネクタ(16)か
ら離脱した上、PROM書込み用コネクタ(20)をコ
ネクタビン(15)へ接続しPROMへの書込みを行う
When writing to PROM (la), (lb), disconnect from the connector bin (15) e short-circuit connector (16), connect the PROM write connector (20) to the connector bin (15), and write to the PROM. Write.

この場合PROMは読出回路(9)から離脱しているの
で、PROMへの書込みによって続出回路(9)に影響
を及ぼすことはない。
In this case, since the PROM is separated from the readout circuit (9), writing to the PROM does not affect the subsequent readout circuit (9).

なお、上記実施例では、通常の読出し時にはコネクタビ
ン(12)と(15)とを短絡コネクタ(16)で接続
したが、この接続は他のどのような方法で行ってもよく
、コネクタビン(15)が着脱容易な接続装置を経てコ
ネクタビン(12)に接続される構造であればよい。
In the above embodiment, the connector bins (12) and (15) are connected by the short-circuit connector (16) during normal reading, but this connection may be made by any other method. 15) may be connected to the connector bin (12) via an easily attachable/detachable connecting device.

また、コネクタには同様の機能を持つものならどの様な
形式のものを使用しても良い。
Moreover, any type of connector may be used as long as it has a similar function.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、PROMを読出回路か
らコネクタの離脱によって電気的に分離できるように構
成し、分離した状態でPROMへの書込みを行うように
したので、PROMの書込みによって読出回路に悪影響
を及は°すことなく、どのような種類のPROMに対し
ても簡単に書込みを行うことができ、また書込みのため
に複雑な回路をF ROMカード上に付加する必要がな
く装置の原価を低減することができるという効果がある
As described above, according to the present invention, the PROM is configured so that it can be electrically separated from the readout circuit by detaching the connector, and writing to the PROM is performed in a separated state. It is possible to easily write to any type of PROM without adversely affecting the PROM, and there is no need to add complex circuitry to the PROM card for writing, making it easier for the device to operate. This has the effect of reducing cost.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示すブロック図、′第2
図は従来のPROM回路のブロック図である。 (la)、(lb)はそれぞれPROM 、  (10
)は読出回路側の信号線、(11)tel:読出回路側
の電源線、(12)は読出回路側のコネクタビン、(1
3)はPROM側の信号線、(14)はPROM側の電
源線、(15)はPROM側のコネクタビン、(16)
は短絡コネクタ、(17)はPROM書込装置、(18
)fiPROM ’!込み信号線、(19)はPROM
書込み電源線、(20)はPROM書込み用コネクタで
ある。 尚、各図中同一符号は同−又は相当部分を示す。
FIG. 1 is a block diagram showing one embodiment of the present invention;
The figure is a block diagram of a conventional PROM circuit. (la) and (lb) are PROM and (10
) is the signal line on the readout circuit side, (11) tel: power supply line on the readout circuit side, (12) is the connector pin on the readout circuit side, (1
3) is the signal line on the PROM side, (14) is the power line on the PROM side, (15) is the connector pin on the PROM side, (16)
is the short-circuit connector, (17) is the PROM writing device, and (18) is the short-circuit connector.
)fiPROM'! Included signal line, (19) is PROM
The write power supply line (20) is a PROM write connector. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (3)

【特許請求の範囲】[Claims] (1)PROM回路(プログラマブル・リード・オンリ
・メモリ回路)の読出しを行う読出回路から上記PRO
Mに到るアドレス信号線及びデータ信号線を含む信号線
ならびに電源線がそれぞれ接続される第1のコネクタの
それぞれのピン、 上記PROMに接続されている上記信号線ならびに電源
線がそれぞれ接続される第2のコネクタのそれぞれのピ
ン、 上記第1のコネクタと上記第2のコネクタの互に対応す
るピン間を接続する着脱容易な接続装置を備えたPRO
M回路。
(1) From the reading circuit that reads the PROM circuit (programmable read-only memory circuit) to the PRO
Respective pins of the first connector to which signal lines including address signal lines and data signal lines up to M and power supply lines are respectively connected, and the signal lines and power supply lines connected to the PROM are respectively connected. Each pin of a second connector, a PRO equipped with an easily attachable/detachable connecting device that connects between corresponding pins of the first connector and the second connector.
M circuit.
(2)着脱容易な接続装置は、上記第1のコネクタのそ
れぞれのピンと上記第2のコネクタのそれぞれのピンと
の間を接続する短絡コネクタを備えたことを特徴とする
特許請求の範囲第1項記載のPROM回路。
(2) The easily attachable/detachable connecting device includes a short-circuit connector that connects each pin of the first connector and each pin of the second connector. PROM circuit as described.
(3)第2のコネクタのそれぞれのピンは、上記第2の
コネクタと上記接続装置との接続を離脱した状態におい
てPROM書込装置からの信号線及び電源線にそれぞれ
接続されPROMに対し書込みを行うことができること
を特徴とする特許請求の範囲第1項記載のPROM回路
(3) Each pin of the second connector is connected to the signal line and power line from the PROM writing device when the connection between the second connector and the connecting device is disconnected, and writes to the PROM. A PROM circuit according to claim 1, characterized in that it can perform
JP60091455A 1985-04-26 1985-04-26 Prom circuit Pending JPS61248298A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60091455A JPS61248298A (en) 1985-04-26 1985-04-26 Prom circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60091455A JPS61248298A (en) 1985-04-26 1985-04-26 Prom circuit

Publications (1)

Publication Number Publication Date
JPS61248298A true JPS61248298A (en) 1986-11-05

Family

ID=14026839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60091455A Pending JPS61248298A (en) 1985-04-26 1985-04-26 Prom circuit

Country Status (1)

Country Link
JP (1) JPS61248298A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06132056A (en) * 1992-10-14 1994-05-13 Nec Corp Connector for writing contents of eprom
JPH06132055A (en) * 1992-10-14 1994-05-13 Nec Corp Mounting system for eprom

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06132056A (en) * 1992-10-14 1994-05-13 Nec Corp Connector for writing contents of eprom
JPH06132055A (en) * 1992-10-14 1994-05-13 Nec Corp Mounting system for eprom

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