JPS60136999A - Memory integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the packaging density and to attain ease of handling in using a memory integrated circuit by changing over selectively the 1st circuit system leading a data fed to an input terminal for address designation and the 2nd circuit system leading the data for chip selection. CONSTITUTION:When a memory integrated circuit 21a where a defective cell exists in a designated memory area with an address data line A12 at L level and a memory integrated circuit 21b where a defective cell exists in a designated memory area with the A12 at H level are used in pairs, a detection circuit of the memory integrated circuit 21a detects the H level and the memory integrated circuit 21b detects the L level. Since the memory integrated circuit operated actually is different depending whether the address data line A12 is at H level or L level while a CS signal is at H level, the two memory integrated circuits 21a, 21b are used as one memory integrated circuit. The handling of the memory integrated circuits is conducted easily and the circuit constitution contributes to the improved packaging density.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention 8A uses a memory integrated circuit as a non-defective part (re-ν cell) by not specifying the address of an area including a defective cell. The present invention relates to improvements in such memory integrated circuit devices.

[Technical background of the invention]

As is well known, in memory integrated circuits.

For example, in cases where one memory cell is defective, the address of the area containing the defective cell is not specified, and the remaining memory area is used. For example, take a 64-bit memory integrated circuit having 8 words with 8 bits per word.

It depends on whether this memory integrated circuit requires 13 address gate lines A and %All, or whether the most significant bit address gate line AJ is at the high level or the low level. , the entire memory area of the memory integrated circuit J1 [64 bits] as shown in FIG.
For this, two keys A and B each having 32 bits are specified. Therefore, 1. For example, if one memory cell in memory area A specified by address data line All at H level is defective, then if one memory cell in memory area B specified by address data line All at L level is defective,
Use only.

In the end, the memory integrated circuit 1'I is used as 32 bits.

In this case, in order to specify the above memory area B, the memory y
When connecting the integrated circuit 1 to a printed wiring board (not shown),
Bin P1□ to which address data line AI2 is connected as shown in FIG.

It is fixed at the L level by grounding it via a jumper wire 12 or the like. Conversely, if one memory cell in the 9mKB memo specified by the address data line A and the drop level is defective, the above-mentioned bin PL! is connected to the power supply terminal 13 to which a direct current voltage (VDD) is applied and fixed at H level, so that the memory area A is used.

[Problems with Background Art] However, the conventional memory integrated circuit device having the above-described configuration also has a problem in that connecting the jumper wire 12 increases the number of work steps required by the user. In addition, when using the /Yashal product, it is necessary to process the printed wiring board in advance so that the above-mentioned bin pat can be connected to either the Mt source terminal No. 3 or the ground terminal with a jumper wire J2. This also results in an increase in the number of man-hours for the user's work, as well as a decrease in the mounting density on the printed wiring board.

Here, in the case where only half of the memory area of the memory integrated circuit 11 is partially utilized as described above.

Normally, the memory integrated circuit 1 is not used in a critical condition, and as shown in FIG. Memory integrated circuits JJ and b in which defective cells exist in the memory area designated by the H level are often used in pairs so that 64 as a whole has a bit memory function. In this case, the address data line A6”-A
11 is connected to the address data input pins PG to Pit of the memory integrated circuits 11a and 11b, and the address data input pins R1m of the memory integrated circuits JJa and JJb are fixed at H level and L level, respectively. Note that the input/output Cl10) data bus and read μ writing control signal R/W are connected to the memory integrated circuit 11a as usual.
They are respectively connected to the data input/output bin group I10 of ILB and the readout control signal input pin R/W.

Here, the memory integration port K1Ja.

Since the two memory integrated circuits 11b need to be used as having one 64-bit memory function, the two memory integrated circuits 11a and 11b have the same logic level (for example, H
Selected by the chip select (CS) signal (level)
It's a dream come true. However, C8 at the same logical level
If you simply supply the chip select signal input pin C8 of each memory integrated circuit 11a, Ilb to Gakujun, two memory integrated circuits JJa, JJb will be selected at the same time. Data reading or ill:glance will be performed for the data.

Therefore, even if C3fTh becomes H rep/l/, All
The signal actually supplied to the one select signal input bin C8 of the memory integrated circuit 11n and Jlb must selectively become 11 and 11 depending on whether the signal is H level or L level.

Therefore, the most significant bit address data A, and C
S (-f1 is NOT circuit J4 and NAND circuit J5 'e 16 yo F)'f By processing in processing circuit 17, bAl
Memory integrated circuit JJ depending on whether l is H level or L level.
It becomes necessary to control the chip select signal input bin C3 of a and JJb to be selectively brought to the H level. therefore.

The above processing IP! There is also the problem that the valve configuration in which the valve I approximately J7 is provided becomes complicated, and the mounting density on the printed wiring board also decreases.

[Purpose of the invention]

This issue was made in consideration of the above circumstances,
It is an object of the present invention to provide an extremely good method of tearing a memory integrated circuit, which can facilitate handling when a memory integrated circuit is used as a partially non-defective product, and which can also contribute to improved mounting placement.

[A essential point of the invention]

That is, the memory integrated circuit bag according to the present invention does not specify the address of the area including the defective cell, and is the memory integrated circuit bag not specified. In the memory integrated circuit device to be used, data supplied to this input terminal is input to an input terminal that is formed inside the memory integrated circuit and specifies the address of a predetermined chain acid. a first circuit system that guides the data supplied to the input terminal for designation, and a second circuit system that guides the data supplied to the input terminal for chip consumption;
By providing a smoke cutting means that can be switched to selectively operate the first and second circuit systems,
The present invention is characterized in that the function of the input terminal can be changed.

[Embodiments of the invention]

Hereinafter, an embodiment in which the present invention is applied to a 64-bit memory integrated circuit will be described in detail with reference to one drawing. As shown in FIG. 4, the address data input pin Pit to which the most significant bit address data line All of the memory integrated circuit 2 is connected is connected to two types of circuit systems described below within the integrated circuit 2. It is connected. First, the first circuit system guides data supplied to pin pH to a memory cell (not shown) via a switch 5Fs (described later) and an OR circuit 22, and uses it for addressing.

Further, the second circuit system transmits the data supplied to the pin pH to the detection circuit 23. lead to the memory cell via the input signal fS and the OR circuit 22.

This is used for address specification. here.

” The detection circuit 23 detects the pin P1. This is to detect whether the r-wave supplied to the circuit is at H level or L level.

Either one may be detected as needed, but here it is assumed that the H level is detected.

When this detection circuit 23 detects the ■ level,
A chip select (C8) control signal is generated to place the memory integrated circuit 21 in a state in which reading/writing is not possible and the memory integrated circuit 2 is in a selected state. 1, when the above data is at L level, the detection circuit 23 does not output the C8 control signal, and the switch S2 and OR
Even if an address is specified via the circuit 22, data will not be read or written to that address.

Here, the switches St and St are configured such that one of them is turned on and the other is turned off.
This is a switching means for selectively switching and using the circuit system. This switch y-8I, S is composed of, for example, a fuse, and one of the fuses is short-circuited.

By opening the other fuse.

It is designed to be turned on, turned on, and turned off.

For example, if all memory cells are found to be normal as a result of testing the memory integrated circuit 2, the manufacturer of the memory integrated circuit 21 installs a switch S as shown in FIG. The switch S is turned on and the switch S is turned off to provide it to the user. Then, the user pins
It can be used by connecting the address data line All to H as usual.

On the other hand, as a result of testing the memory integrated circuit 21, for example, the address data line AI! If there is an abnormality in the memory cell in the memory area specified by the L level, the manufacturer turns off the switch S,
is provided to the user as an on state. Then.

As shown in FIG. 5, the user connects the C8 signal line 24, which is supplied with the C S fM signal which selects the memory integrated circuit 21 at H level, to the pin P.

By doing this, when the C8 signal is at L level, the detection circuit z3 does not generate the C8 control signal, and the memory integrated circuit 21 is in a state where no read/write operation is performed, and has no relation to the I10 data bus. It will be done. Also.

When the C8 signal is at H level, the C8 signal is output from the detection circuit 23.
Since the locking signal is generated, the memory integrated circuit 21 is enabled for reading and filling operation, and the memory integrated circuit 21 is in the selected state, and the H level C8 signal is sent to the detection circuit 23, the switch fS, and AI! via the OR circuit 22. is now used to specify the memory area (normal memory area) specified at the H level.

Once, according to the configuration of the above embodiment, the user pinned the C8 other number line 24 to the pin p1! It is possible to easily use the memory integrated circuit 211 as a partially good product by just connecting it, making it extremely easy to handle compared to the conventional method using Soyanper grade, and reducing the packaging density on the printed wiring board. This can also contribute to improvement. Also.

For example, if there is an abnormality in a memory cell within the memory head area specified by address data line 811 or H level, the detection circuit 23 will output data at L level while detecting C8 at H level (M number). If it is supplied to the memory cell side via the input 'fS and the OR circuit 22, the AI.

It is possible to specify a memory area (normal memory area) specified at L level. In this way, depending on which memory area is abnormal, the Ministry of Manufacturing may
By appropriately setting the characteristics of the pin ptt, the user can
By simply connecting the CS signal line 24 to the memory integrated circuit 21, it becomes possible to easily use the memory integrated circuit 21 as a partially non-defective product.

Here, by adopting the configuration as in the above embodiment, as shown in FIG. .

Memo 9 where address data line A11 is designated at H level Memory integrated circuit with defective cells in FM area 2.
When using 1b bare, the memory integrated circuit 21m
Assuming that the detection circuit detects the H level, and the memory integrated circuit ZJb detects the L level, one memory integrated circuit 21m, 21bO and each bit ypH and C8fm
Signal input bin C8K, address data line AI! and C
3f- lines 24 can be directly connected to each other. That is, when the C8 signal becomes H level, both memory integrated shield circuits; lla and 21h are selected, but the address data line AI! The memory integrated circuit 2 is actually operated depending on whether it is at H level or L level.
Since the memory integrated circuits 1a and 21b are different, the two memory integrated circuits 21a and 21b can be used as if they were one memory integrated circuit, and the processing circuit 17 can be used as if it were a single memory integrated circuit. Since the same line can be connected to the same bins of both memory integrated circuits 21a and 21b, as shown in FIG. The bottles can be connected to each other and connected to a printed wiring board (not shown).This can fully contribute to improving the packaging density on the printed wiring board.

It should be noted that the present invention is not limited to the above-mentioned examples, and can be implemented with various modifications without departing from the spirit of the invention.

〔Effect of the invention〕

Therefore, as described above in detail, according to the present invention, an extremely good memory integrated circuit device can be provided which can facilitate handling when a memory integrated circuit is used as a partially non-defective product, and which can also contribute to an improvement in packaging density. can be provided.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of the use of a partially non-defective memory integrated circuit, Figures 2 and 3 are block diagrams showing conventional memory integrated circuit devices, and Figures 4 and 5 are block diagrams of the conventional memory integrated circuit device. FIGS. 6 and 7 are a block diagram showing an embodiment of the memory integrated circuit device according to the invention, and FIGS. 6 and 7 are a block diagram and a side view, respectively, showing an example of how the embodiment is used. 2 No. . . Memory integrated circuit, 22 . . . OR circuit. 23...Detection circuit, 24...CS (i3 2-in.

Claims (1)

[Claims] In a memory integrated circuit device in which a memory integrated circuit is used without specifying the address of an area including a defective cell, data that is formed inside the memory integrated circuit and that specifies the address of a predetermined area is input. a first circuit system that uses the data supplied to the input terminal for addressing, and a second circuit system that directs the data supplied to the input terminal for chip selection. and a switching means capable of switching to selectively operate the first and second circuit systems.