JPS58200571A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To largely improve the yield of semiconductor memory with less regions of redundant memory by a method wherein transfer gates are provided between a column switch and a sense-up, and the signals which specify input- output blocks are inputted into the gates. CONSTITUTION:When a defective memory cell exists at the main memory region 40, the level of the signal 54 is 1, then only the redundant memory cell 50 is selected, and thus the information is passed through the forth transfer gates 62 and 64 of the input-output block wherein bit lines 51 and 51', the data lines 55 and 55' of the column switch 52, and the defective memory exist, then inputted into the sense-up 46 and transferred to an output buffer. Since the signal 54 of 1 level is inputted into a NAND circuit 57, the NAND circuit 57 turns at 0 level and thus the second and forth transfer gates 62 and 64 turn into the state of selection, when specifying signals 56 are all 1 (when selecting the input-output block wherein the defective memory cell exists).

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that can improve the yield of semiconductor memories by replacing a main memory area in which defective memory cells exist with a redundant memory area.

In order for semiconductor memory to be widely used in society, it is necessary to provide semiconductor memory to society at low cost.

To this end, it is important for semiconductor manufacturers to realize semiconductor memories with high yields.

Regarding the manufacturing of semiconductor memory, when the capacity of semiconductor memory was small, there was no need to adopt a configuration with a redundant memory area within the semiconductor memory chip.
It was possible to obtain perfectly good semiconductor memory with a relatively high yield.

However, with the rapid progress of VLSI technology, the capacity of semiconductor memory has increased from 64 bits to 25eK bits. It is becoming more and more difficult to obtain semiconductor memories that are completely good in terms of yield.

As an example of a conventional semiconductor memory, FIG. 1 shows the configuration of a static random access memory (SRAM). In Figure 1, 1 is the main memory cell, 2 is the row address, 3 is the row decoder, 4 is the column address,
6 is a column decoder, 6 is an input/output circuit, 7 is an input/output control signal, 8 is an input/output control circuit, and 9 is an input/output terminal.

In static RAM, externally applied row address 2 and column address 4 signals are decoded by row decoder 3 and column decoder 5, respectively, to select the X direction and Y direction, and select a specific one from main memory cell 1. A memory cell is selected. The information of the memory cell selected in this way is sent to the input/output circuit 61, amplified, and outputted through the input/output terminal 9.

In a semiconductor memory, the process by which information of a memory cell selected by the row decoder 3 and column decoder 6 enters the sense amplifier of the input/output circuit 6 will be described below with reference to FIG. In Figure 2, 1o is the main memory, i
Nicell region, 1σ is one memory cell 11, 11'
is a bit line, 12 is a column switch, 13 is a word line, 14 is an output signal from a column decoder, 15
, 16' is a data line, 16 is a sense amplifier, 1
7.17' indicates the output line to the output buffer 7.

Below, the signal path to the memory cell 1o' color output Hanofer will be explained. The information on 10' is output to bit lines 11 and 11', passes through the transfer gate of column switch 12, and is transferred to data line 1.
6 and 15', and enters the sense amplifier 16. The information D1D of the memory cell 10' is amplified by the sense amplifier 16 and transferred to the output buffer through 17.degree. 17'.

As described above, in the conventional semiconductor memory, a redundant memory area is not provided, and if even one bit of defective memory cell exists in the main memory area 1o, the semiconductor memory is considered to be a defective product. If the configuration is such that a perfectly good semiconductor memory is obtained using only the main memory area 10, as the semiconductor memory capacity increases to 64 bits and 266 bits in the future, the yield will not increase and the semiconductor memory will be Providing products to society at low prices is becoming increasingly difficult.

The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a semiconductor memory with a redundant memory area, improve the yield, and provide a low manufacturing cost of the semiconductor memory.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 3 shows the configuration of a semiconductor memory according to an embodiment of the present invention having such a redundant memory +7- area. In FIG. 3, 31 is a main memory area, 22 is a row address, 23 is a row decoder, 24 is a column address, 26 is a column decoder, 26 is an input/output circuit, 27 is an input/output control signal, and 28 is an input/output control circuit. , 29 are input/output terminals, 3o is a redundant memory area, 31 is a matching circuit that generates an output signal only when an address input signal corresponding to the main memory area where the defective memory cell exists is input, and 32 is from the matching circuit 31. 33 indicates a preliminary input/output circuit.

First, the semiconductor memory is designed to select the main memory area 21. Test the semiconductor memory with an LSI tester to determine whether even if a defective memory exists, it can be repaired using the redundant memory area 30. If the defect can be repaired using the redundant memory area 30, the person with the defective memory cell The output block and column address are fixed in a nonvolatile memory (such as Heath POM) existing in the matching circuit 31. By doing this, when a column address signal in which a defective memory cell exists in the main memory area 21 is input, 1-F, -
A signal that activates only the output signal of the preliminary decoder 32 is outputted by the multiplication circuit 31, and a memory cell in the redundant memory area 30 is selected. The signal selected here is outputted to the input/output terminal 29 via the input/output circuit 33.Next, in the semiconductor memory having the redundant memory area shown in FIG. The process by which the information of the memory cell 21.30 selected by the decoder 32 enters the sense amplifier of the input/output circuit 26.33 will be explained in detail with reference to FIG.

In FIG. 4, 4o is the main memory cell area of one output block, 40' is one main memory cell, 41.41
' is a bit line in the main memory area, 42 is a column switch in the main memory cell area, 43 is a word line, 44
is the output signal from the column decoder in the main memory area,
45. 45' is the data line of the main memory area, 46
is the sense amplifier, 47.47' is the output line to the output buffer, 5o is the redundant memory cell area, 50' is one redundant memory cell, 51.61' is the bit line of the redundant memory area, 52 is the redundant memory area The column switch 54 is a signal pre-decoded by the i-decoder so as to select the redundant memory area 5o instead of the main memory area 4o when a column address in which a defective memory cell exists is input, 55. Reference numeral 55' denotes a data line for the redundant memory area, and this data line 65.degree. 65' is input to the sense amplifier of each input/output coupler. Further, 66 is a signal specifying an input/output block in which a defective memory cell exists, 57 is a large power NAND circuit, and 68
is an inverter, 60 is a part of the input/output circuit of the single output circuit block, and 51, 62, 63°64 are the first . Second
．． Third. This is the fourth transfer gate.

However, in the following explanation, the static R of the byte configuration
In AM, it is assumed that the redundant memory area 50 has only one column.

First, when there is no defective memory cell in the main memory cell area, the level of the signal 54 is "0", and one of the output signals 44 from the column decoder is selected. At this time, one memory cell 40' in the main memory IJ-cell area 4o is selected, this information is output to the bit line 41.41', the transfer gate of the column switch 42, the data line 4.5. ,45',
The diameter of the first and third transfer gates 61 and 63 is
The signal is input to the sense amplifier 46, where it is amplified and transferred to the output buffer 7. At this time, the second or fourth transfer game (62, 64) is closed.

Next, when there is a defective memory cell in the main memory area 40, the signal 640 level is "1", and at this time,
−゛The output signal 44 from the column decoder is all “0”
(described later), and only the redundant memory cell 5o is selected. The information of the redundant memory cell 50 is output to the bit line 51.51', to the data line 55.55' of the transfer gate of the column switch 52, and to the fourth transfer gate 62.6 of the input/output coupler where the defective memory cell exists.
4, the signal is input to the sense amplifier 46, where it is amplified and transferred to the output buffer. That is, ``11
Since the level signal 54 is input manually to the NAND circuit 57,
When the designation signals 56 are all "1" (when selecting an input/output block in which a defective memory cell exists), the NAND circuit 57 becomes "0" level and the second. At the time of the fourth transfer gate, the first. Third transfer gate 61.6
3 is closed; however, since this is a byte-configured semiconductor memory, the first to fourth transfer gates 61 to 64 are closed.
There are a number corresponding to input and output blocks, that is, 8 sets, and the second . The fourth transfer gate 62,64 opens and the first
．． Only one of the eight sets of third transfer gates 61 and 63 is closed, and this one set is B. ,B1
．． It is specified by the signal B2, and B of the signal 56. ,
B1. B2 is fixed in a non-volatile memory (Head's ROM, etc.). Regarding the remaining 7 sets, 1st. The third transfer gates 61 and 63 are open, and the second and fourth transfer gates 62 and 64 are closed.

Next, one embodiment of the matching circuit is shown in FIG.

In FIG. 5, 70 is a column address signal, and 71 is a fixed column address corresponding to the main memory area where the defective memory cell exists. 72 is an Ex-NOR circuit; 73 is a terminal having a nonvolatile memory capable of writing a "0" level when there is no defective memory cell in the main memory area and a "1" level when there is a defective memory cell in the main memory area; 74 is a large power NAND.

75 is an inverter, and 76 is an output.

First, when a defective memory cell exists in the main memory area 21, the nonvolatile memory connected to the terminal 73 is set to "1".
The level is fixed, and the column address information 71 in which the defective memory cell exists is fixed in the nonvolatile memory. By doing this, the level of the output cuff 6 becomes the "1" level only when the column address signal 7o corresponds to a column address where a defective memory cell exists. This signal 76 is used as signal 54 in FIG. The inverted signal of this signal 76 is input to the column decoder 2sK in the main memory area, and the gate is configured so that the output detection force 44 is all "0". By doing this, the column address where the defective memory cell exists When a column address signal corresponding to address r is input, a redundant memory cell 50 is selected,
At other times, main memory cell 4o can be selected.

In the above explanation, the case where a defective memory cell exists in one of the eight output blocks of the main memory area has been described, but when the defective memory cell exists in two different input/output blocks (( It goes without saying that this defect can be relieved by having two matching circuits having the above configuration and two sets of redundant memory cells, etc. As explained above, according to the present invention, the main memory area Even if there is a defective memory cell in the memory cell, its function can be replaced by a redundant memory cell. 1. A transfer gate is provided between the column switch and the sense amplifier, and a signal identifying the input/output coupler is sent to this gate. By inputting, with less redundant memory area,
It has high industrial value because it significantly improves the yield of semiconductor memory.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional semiconductor memory, FIG. 2 is a circuit diagram of a main part of a conventional semiconductor memory, and FIG. 3 is a configuration diagram of a semiconductor memory according to an embodiment of the present invention. is a circuit diagram of a main part of the semiconductor memory shown in FIG. 3, and FIG. 6 is a circuit diagram showing an embodiment of a matching circuit. 300ψ fist...redundant memory area, 31e...-L
Matching circuit, 32... Spare decoder, 60...
. . . redundant memory cell, 64 . . . output signal from matching circuit, 56 . Signal, 61.62, 83.64--1.
2nd゜3rd #4th transfer gate, 72...
・Φ・Ex-NOR circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 1θ Exit cover 11. centre. Figure 3 Figure 5 7θ r-^-)

Claims (1)

[Claims] A main memory, a redundant memory, a column switch connected to the main memory, a spare column switch connected to the redundant memory, and a first column switch connected to the column switch and the spare column switch, respectively. a second transfer gate; and the first transfer gate. and a sense amplifier for amplifying the output of the second transfer gate, the first transfer gate is made conductive when there is no defective memory cell in the main memory, and the sense amplifier amplifies the output of the second transfer gate. When Liesel exists, the second
A semiconductor memory device characterized in that a transfer gate of is made conductive.