JPH07260884A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit device in which the time required for testing a large number of RAM macros provided on one chip can be shortened without increasing the number of outer terminals for test. CONSTITUTION:An inner control circuit 14 normally delivers a data ND to a plurality of RAM macros 11 in order to read and write cell information. A switch circuit 15 connects the RAM macros 11 sequentially with a tester 16 based on a test mode signal TM and a macro selection signal SL and performs data holding test for each RAM macro 11. The switch circuit 15 can cause the tester 16 to perform write/read operation of a test data TD into/ from the RAM macro 11 based on the test mode signal TM and a macro selection signal SL. The switch circuit 15 disconnect RAM macros 11 not selected from the inner control circuit 14 based on the macro selection signal SL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in which a large number of macro cells forming a RAM and other logic circuits are contained in one chip.

In recent years, semiconductor integrated circuit devices have become highly integrated, and the number of RAM macros mounted on one chip and the storage capacity of each RAM macro are also increasing. When each RAM macro of such a semiconductor integrated circuit device is composed of an SRAM, whether or not the data retention time of each memory cell satisfies the specifications is checked by using a test terminal provided on a chip in advance. A data retention test, which is checked by an external test device, is performed in the shipping operation test. 1
With the increase of RAM macros mounted on the chip,
Since the time required for the data retention test tends to be long, it is necessary to shorten the time required for the data retention test.

[0003]

2. Description of the Related Art A test circuit mounted on a semiconductor integrated circuit device having a large number of RAM macros will be described with reference to FIG.

A plurality of bits of macro selection signals input from the external test equipment are input to a decoder (not shown),
The decoder outputs multi-bit selection signals SL0 to SLn. For example, in order to select the first RAM macro 1, 4-bit macro selection signals SL0 to SL3 are selected from the macro selection signals SL0 to SLn in the NAND circuit. 2a is input.

The output signal of the NAND circuit 2a is input to one input terminal of the NAND circuit 2b via the inverter circuit 3a. A test mode signal TM is input from the external tester to the other input terminal of the NAND circuit 2b.

The output signal of the NAND circuit 2b is input to the inverter circuit 3b and the switch circuit S
It is input to the control terminal T1L of W1 and the control terminal T2H of the switch circuit SW2.

The output signal of the inverter circuit 3b is supplied to the control terminal T1H of the switch circuit SW1 and the switch circuit SW.
2 and the control terminal T2L. The switch circuit S
W1 is closed when the control terminal T1H is at H level and the control terminal T1L is at L level, and is opened when the control terminal T1H is at L level and the control terminal T1L is at H level.

The switch circuit SW2 is closed when the control terminal T2H becomes H level and the control terminal T2L becomes L level,
When the control terminal T2H becomes L level and the control terminal T2L becomes H level, the circuit is opened.

The test data TD is input to the input terminal of the switch circuit SW1, and the output terminal is connected to the RAM macro 1. Normal data ND is input from the internal control circuit to the input terminal of the switch circuit SW2, and the output terminal is connected to the RAM macro 1. In FIG. 3, the signal lines for inputting the test data TD and the normal data ND are illustrated one by one, but the test data TD and the normal data ND are respectively composed of an address signal, input data, a clock signal, and the like. Therefore, a plurality of signal lines are connected to the RAM macro 1 via the switch circuits. A plurality of RAM macros to which such a test circuit is connected are provided on the same chip.

In the semiconductor integrated circuit device as described above, the test mode signal TM becomes L level during normal operation.
Then, the output signal of the NAND circuit 2b becomes H level regardless of the macro selection signals SL0 to SL3, and the output signal of the inverter circuit 3b becomes L level.

Then, the switch circuit SW1 is opened,
The switch circuit SW2 is closed. As a result, the normal data ND can be input to the RAM macro 1 from the internal gate circuit, and the write and read operations are performed by the normal data ND.

On the other hand, when the test mode signal TM becomes H level in the test mode, the NAND circuit 2b enters a state of waiting for the output signal of the inverter circuit 3a. In this state,
When all of the macro selection signals SL0 to SL3 become H level, the output signal of the NAND circuit 2a becomes L level and the output signal of the inverter circuit 3a becomes H level.

Then, the output signal of the NAND circuit 2b is L
And the output signal of the inverter circuit 3b becomes H level. Then, the switch circuit SW1 is closed and the switch circuit SW2 is opened.

As a result, the test data TD can be input to the RAM macro 1 from the external test apparatus, and the operation test of the RAM macro 1 is performed based on the test data TD.

In the data retention test, which is one of the operation tests, a write operation is performed on each memory cell in the RAM macro 1 by an external test device, and cell information is read from each memory cell after a certain data retention time satisfying the specifications. Is read and it is checked whether or not it matches the write data.

Such a data holding test is sequentially performed for each RAM macro selected based on the macro selection signals SL0 to SLn. Further, in the test mode, when the macro selection signals SL0 to SL3 are not all at the H level and the RAM macro 1 is not selected, N
The output signal of the AND circuit 2a becomes H level, and the output signal of the inverter circuit 3a becomes L level. Then NA
The output signal of the ND circuit 2b becomes H level, and the output signal of the inverter circuit 3b becomes L level. Then, the switch circuit SW1 is opened and the switch circuit SW2 is closed. As a result, the RAM macro 1 is connected to the internal control circuit.

[0017]

In the semiconductor integrated circuit device as described above, the R not selected in the test mode is used.
The AM macro is connected to the internal control circuit when the switch circuit SW2 is closed.

In this state, the RA from the internal control circuit
It is possible that a clock signal or the like is input to the M macro and the RAM macro is performing a self-refresh operation of cell information.

Therefore, in the data holding test, after writing predetermined data to the selected RAM macro, a certain data holding time is allowed to elapse and then a read operation is performed to check the cell information.

Therefore, since it is necessary to perform the above operation for each RAM macro, there is a problem that the test time increases and the test cost increases as the number of RAM macros increases.

Further, if the external test device simultaneously accesses the respective RAM macros from the external test terminals to perform the data retention test, the test time can be shortened, but R
As the number of AM macros increases, the number of test-dedicated terminals increases, so that there is a problem that the number of external terminals used for normal use decreases.

An object of the present invention is to provide a large number of R's provided on the same chip without increasing the number of external terminals for testing.
It is an object of the present invention to provide a semiconductor integrated circuit device that can reduce the test time of an AM macro.

[0023]

FIG. 1 is a diagram for explaining the principle of the present invention. That is, the internal control circuit 14 includes a plurality of RAMs.
The normal data ND is output to the macro 11 to perform a cell information write operation and a cell information read operation. Switch circuit 15
Is a test mode signal T input from the external test equipment 16.
RAM macro 1 based on M and a macro selection signal SL for selecting one of the RAM macros 11.
1 is sequentially connected to the external test apparatus 16 and each RAM macro 1
Perform the data retention test of 1. The switch circuit 15 is
The RAM macro 11 is selected based on the test mode signal TM and the macro selection signal SL so that the external test apparatus 16 can write and read the test data TD to and from the RAM macro 11. The switch circuit 15 cuts off the connection between the RAM macro 11 which is not selected based on the macro selection signal SL and the internal control circuit 14, and when the test mode signal TM is not input, the switch circuit 15 causes the internal control circuit 14 to operate. RAM
Connect to macro 11.

Further, as shown in FIG. 2, the switch circuit 15 connects the input terminal of the unselected RAM macro 11 to the power source VEE.

[0025]

When the test mode signal TM is input from the external test device 16 to the switch circuit 15 and the macro selection signal SL is input to the switch circuit 15 in the test mode, the external test device 16 is applied to the selected RAM macro 11. Thus, the write and read operations of the test data TD are performed. The non-selected RAM macro 11 is disconnected from the external test apparatus 16 and the internal control circuit 14. When the test mode signal TM is not input to the switch circuit 15, each RAM macro 11 is connected to the internal control circuit 14.

RA not selected in the test mode
The input terminal of the M macro 11 is connected to the power source VEE, and the self refresh operation of the cell information of the RAM macro 11 is stopped.

[0027]

An embodiment of a semiconductor integrated circuit device embodying the present invention will be described below. As shown in FIG. 2, a multi-bit macro selection signal input from an external test apparatus is input to a decoder (not shown), and multi-bit selection signals SL0 to SLn are output from the decoder, for example, the first RAM. In order to select the macro 11, the 4-bit macro selection signal S is selected from the macro selection signals SL0 to SLn.
L0 to SL3 are input to the NAND circuit 12a.

The output signal of the NAND circuit 12a is N
It is input to one input terminal of the AND circuit 12b and is input to one input terminal of the NAND circuit 12c via the inverter circuit 13a.

A test mode signal TM from an external tester is applied to the other input terminals of the NAND circuits 12b and 12c.
Is entered. The output signal of the NAND circuit 12b is
It is input to the inverter circuit 13b and also to the control terminal T11L of the switch circuit SW11. The output signal of the inverter circuit 13b is the switch circuit SW.
11 is input to the control terminal T11H.

The output signal of the NAND circuit 12c is input to the inverter circuit 13c and the control terminal T12L of the switch circuit SW12. The output signal of the inverter circuit 13c is input to the control terminal T12H of the switch circuit SW12.

The test mode signal TM is input to the control terminal T13L of the switch circuit SW13 and the inverter circuit 13d. The output signal of the inverter circuit 13d is input to the control terminal T13H of the switch circuit SW13.

The switch circuit SW11 has a control terminal T11.
When H becomes H level and control terminal T11L becomes L level, it is closed, control terminal T11H becomes L level and control terminal T11L becomes H level.
When it reaches the level, it is opened.

The switch circuit SW12 has a control terminal T12.
When H becomes H level and control terminal T12L becomes L level, it is closed, control terminal T12H becomes L level, and control terminal T12L becomes H level.
When it reaches the level, it is opened.

The switch circuit SW13 has a control terminal T13.
When H becomes H level and control terminal T13L becomes L level, it is closed, control terminal T13H becomes L level and control terminal T13L becomes H level.
When it reaches the level, it is opened.

The power supply VEE is input to the input terminal of the switch circuit SW11, and the output terminal is the RAM macro 11
Connected to. The test data TD is input to the input terminal of the switch circuit SW12, and the output terminal is the RAM.
It is connected to the macro 11.

Normal data ND is input from the internal control circuit to the input terminal of the switch circuit SW13, and the output terminal is connected to the RAM macro 11. In FIG. 2, the signal lines for inputting the test data TD and the normal data ND are shown one by one, but the test data TD and the normal data ND are respectively composed of an address signal, input data, a clock signal and the like. Therefore, each of the plurality of signal lines is connected to the RAM macro 11 via the switch circuit. A plurality of RAM macros to which such a test circuit is connected are provided on the same chip.

In the semiconductor integrated circuit device as described above, the test mode signal TM becomes L level during normal operation.
Then, the output signals of the NAND circuits 12b and 12c become the H level regardless of the macro selection signals SL0 to SL3,
The output signals of the inverter circuits 13b and 13c become L level. Further, the output signal of the inverter circuit 13d becomes H level.

Then, the switch circuit SW11 is opened, the switch circuit SW12 is opened, and the switch circuit 1 is opened.
3 is closed. As a result, the normal data ND can be input to the RAM macro 11 from the internal control circuit,
Write and read operations are performed using the normal data ND.

On the other hand, when the test mode signal TM becomes H level in the test mode, the output signal of the inverter circuit 13d becomes L level. Then, the switch circuit SW13
Is opened.

The NAND circuits 12b and 12c are in a state of waiting for the output signal of the inverter circuit 13a. In this state, when the macro selection signals SL0 to SL3 all become H level, the output signal of the NAND circuit 12a becomes L level and the output signal of the inverter circuit 13a becomes H level.

Then, the output signal of the NAND circuit 12c becomes L level, and the output signal of the inverter circuit 13c becomes H level.
It becomes a level. Then, the switch circuit SW12 is closed.

The output signal of the NAND circuit 12b is H level.
And the output signal of the inverter circuit 13b becomes L level. Then, the switch circuit SW11 is opened. Therefore, in this state, the RAM macro 11 is selected, and the write operation or the read operation of the test data TD can be performed from the external test apparatus via the switch circuit SW12.

Further, in the test mode, with the test mode signal TM at the H level, the macro selection signal SL0
In a state in which all of SL3 are not at the H level and another RAM macro is selected, the output signal of the NAND circuit 12a becomes the H level and the output signal of the inverter circuit 13a becomes the L level.

Then, the output signal of the NAND circuit 12b becomes L level and the output signal of the inverter circuit 13b becomes H level.
It becomes a level. As a result, the switch circuit SW11 is closed.

The output signal of the NAND circuit 12c is H.
And the output signal of the inverter circuit 13c becomes L level. Then, the switch circuit SW12 is opened. In this state, the input signal line of the RAM macro 11 is clamped to the power source VEE level.

Therefore, in this semiconductor integrated circuit device, the input signal line of the RAM macro, which is in the non-selected state in the test mode, is clamped to the power supply VEE, so that access to each memory cell such as self-refresh operation is performed in the RAM macro. Is stopped.

In such a semiconductor integrated circuit device,
When the data retention test of the RAM macro is performed, each RAM macro is sequentially selected based on the macro selection signals SL0 to SLn while the test mode signal TM is at the H level, and the memory cells in each RAM macro are tested. Write the data.

After the write operation of the test data is completed, each RAM macro is sequentially selected after a certain data holding time, cell information is sequentially read from the memory cells in each RAM macro, and the data holding time is checked. .

In such a data holding test, the RAM macros are sequentially selected to perform the write operation and the read operation of the test data TD, which is the same as in the conventional example, but the data holding operation is simultaneously performed to each RAM macro. Can be made.

Therefore, if the number of RAM macros is N,
The data retention time can be set to 1 / N of the conventional example. This data retention time is, for example, 10 to 10 times as long as the time required to write and read the test data.
Since the time required is about 20 times, the test time can be significantly shortened.

Further, the number of external terminals required for the data retention test is not increased. The technical ideas other than the claims that can be understood from the above embodiments will be described below along with their effects.

(1) In claim 1, the switch circuit clamps the input terminal of the unselected RAM macro to a constant potential in the state where the test mode signal is input.
The self-refresh operation of the RAM macro not selected is stopped.

[0053]

As described above in detail, the present invention shortens the test time required to perform the operation test of a large number of RAM macros provided on the same chip without increasing the number of external test terminals. A semiconductor integrated circuit device to be obtained can be provided.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an example.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 11 RAM macro 14 Internal control circuit 15 Switch circuit 16 External test device ND normal data TM Test mode signal SL macro selection signal TD test data

Claims (2)

[Claims] 1. A plurality of RAM macros (11), an internal control circuit (14) for outputting normal data (ND) to each of the RAM macros (11) to perform a write operation and a read operation of cell information, Based on the test mode signal (TM) input from the external tester (16) and the macro selection signal (SL) for selecting one of the RAM macros (11), the RAM macro (11) And a switch circuit (15) for sequentially performing a data retention test on each RAM macro (11) by sequentially connecting the external test device (16) to the external test device (16), wherein the switch circuit (15) comprises: The R based on the test mode signal (TM) and the macro selection signal (SL)
Select the AM macro (11) and select the RAM macro (1
1), the test data (TD) write and read operations by the external tester (16) are enabled, and the RAM macro (11) and the internal control circuit (14) which are not selected based on the macro selection signal (SL). When the test mode signal (TM) is not input, the internal control circuit (14) is connected to each RAM.
A semiconductor integrated circuit device characterized by being connected to a macro (11). 2. The semiconductor integrated circuit device according to claim 1, wherein the switch circuit (15) connects an input terminal of the unselected RAM macro (11) to a power supply (VEE).