JP2899387B2 - Semiconductor memory device and test method therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A semiconductor memory device and a method of testing the same can be tested under operating conditions suitable for actual use, and can perform accurate and highly reliable tests. A plurality of bit line pairs are connected to each bus line pair, and a data bus for transferring data written to a memory cell via each bit line pair; A plurality of bit line pairs connected to each bus line pair are selectively switched and connected to the bus line pair, and test data written to a memory cell via the selected bit line pair is transferred to the bus line pair. And a data compression circuit for simultaneously inputting test data from each of the bit line pairs connected to each of the bus line pairs and compressing the test data to determine whether each cell has a defect. A first branch bus for branching from the data bus and inputting test data of each bit line pair previously selected by the selection circuit to the data compression circuit; A second branch bus for inputting test data of each bit line pair selected next to the data compression circuit; a latch circuit provided for each bus line pair of the first branch bus; The test circuit is provided for each bus line pair of the bus, and the test data is latched by the latch circuit in synchronization with the selection operation of the selection circuit, and the latched test data is tested for the next selected bit line pair. A first switch circuit for inputting to the compression circuit in synchronization with data, and a bit line pair provided in each bus line pair of the second branch bus and selected next in synchronization with the selection operation of the selection circuit Only the test data of It consists a second switch circuit for inputting to the circuit.

The present invention relates to a semiconductor memory device and a test method therefor.

As the capacity of the semiconductor memory device increases, the test time has become longer. For this reason, a test mode in which a test is performed by compressing data is adopted to shorten the test time.
When this test is performed, it is desirable that the test be performed under the same operating conditions as normal, and that the circuit for the test mode be as small as possible in order to reduce the chip area.

2. Description of the Related Art Conventionally, as one of tests of a semiconductor memory device, there is a test in which test data is written in each cell, and the written data is read to check whether each cell is operating normally. And, for example, in the case of 1 mega dynamic RAM,
Since sequential writing / reading of one cell requires a very long test time, the test data written to a plurality of cells is simultaneously read, and the read test data is compressed to perform a test. The test mode was adopted to shorten the test time.

The test mode in which this data is compressed and tested is a 1-mega dynamic RAM (hereinafter referred to as DRAM) that has four I / O pins and reads the same test data written to four cells at a time. The four cells are inspected based on the read 4-bit test data to determine whether the four cells are normal. However, one mega DRA with one I / O pin
In M, only 1-bit cell can be written at a time, and only 1 bit can be read, so I / O
Inspection time is four times as long as four pins.

Therefore, in a 1-bit 1-mega DRAM, as shown in FIG. 8, four pairs of data bus lines D0, / D0 to D3, / D3 have bit line pairs B0, / B0 to B3, / B3 respectively. It is connected.
Each bit line pair B0, / B0 to B3, / B3 is connected to a memory cell 22 having one end connected to a word line WL via a transfer gate transistor T1 and a sense amplifier 21. Then, the test data written in the predetermined cells 22 on each of the four bit line pairs B0, / B0 to B3, / B3 respectively correspond via the bit line pairs B0, / B0 to B3, / B3. Data bus line pair
Output to D0, / D0 to D3, / D3. Each data bus line pair D0, / D0 ~
The test data output to D3 and / D3 is input to the data compression circuit 24 via the amplifier 23. That is, the test data from the four memory cells 22 is input to the data compression circuit 24 at the same time.

The data compression circuit 24 is connected to each data bus line pair D0, / D0 to D3, / D3
, That is, input of 4-bit test data and outputting 2-bit compressed data Z, / Z to the data output circuit 25. All of the 4-bit test data have the logical value “H”. When the compressed data of Z is “H” and / Z is “L”, when the 4-bit test data are all logical values “L” of each cell, Z is “L” and / Z is “H”. Output compressed data. Then, the data compression circuit 24 determines that Z./Z
Output compressed data of “H”.

Then, based on the compressed data Z and / Z, the data output circuit 25 outputs “H” when the compressed data Z is “H”, “H” when / Z is “L”, and “L” and / Z when the compressed data Z is “L”. At the time of "H", the test data DT of "L" is output to a predetermined output pin.
When the compressed data Z is "H" and / Z is "H", the test data DT of high impedance is output.

Therefore, in the test, the test data of the logical value “H” is written in each cell, the test data written in each cell is read, and the test data DT is “H” (Z = “H”, / Z =
If “L”), it is known that each cell has been normally written and has been read normally, and the cell has been in a high impedance state (Z =
If “H”, / Z = “H”), it is understood that at least one cell is not operating normally.

Also, test data of a logical value “L” is written in each cell,
The test data written in each cell is read, and if the test data DT is “L” (Z = “L”, / Z = “H”), each cell is written normally and read normally. And a high impedance state (Z = “H”, / Z =
If "H"), at least one cell is not operating normally.

As described above, since four memory cells can be inspected at the same time, the test time is reduced to 1/4 in the test mode in which a plurality of test data are compressed and tested.
Efficiency of the test work is achieved.

However, the capacity of semiconductor memory devices has been increasing more and more. For example, in a 1-bit 4-mega DRAM, even if a test is performed by the above-described method of compressing 4-bit test data, it is four times as large as a 1-bit 1-mega DRAM. It takes time.

Therefore, the test is performed by compressing the 8-bit test data. In this case, as shown in FIG. 9, in addition to the existing four pairs of bus line pairs D0, / D0 to D3, / D3 of the 1-bit 4M DRAM, another four pairs of bus line pairs D4 are used for testing. , / D4 to D7, / D7 to form a data bus having a total of eight bus line pairs.

Bit line pairs B0, / B0 to B7, / B7 are respectively connected to the eight data bus line pairs D0, / D0 to D7, / D7, and the respective bit line pairs B0, / B0 to B7, / D7. B7 is connected to a memory cell 22 via a transfer gate transistor T1 and a sense amplifier 21 as shown in FIG. Then, the test data written in the predetermined cells 22 on each of the eight bit line pairs B0, / B0 to B3, / B3 is the bit line pair B0, / B0 to B3.
Data bus line pair D0, / D0 to D7, / D7 via B7, / B7
And input to the data compression circuit 24 via the amplifier 23. That is, the test data from the eight memory cells 22 is input to the data compression circuit 24 at the same time.

The data compression circuit 24 compresses the eight test data in the same manner as described above, and checks the presence or absence of a defective memory cell based on the compressed data Z and / Z.

[Problems to be Solved by the Invention] However, in the above-described test method, the test is performed by an operation that does not conform to the normal operation of 4-bit read actually performed since 8-bit test data is read simultaneously. That is, when the 8-bit test data is read out simultaneously, a large current that does not normally flow inevitably flows. Then, there was a problem that noise was generated by the large current and an accurate test could not be performed.

When the test is performed by compressing the test data of 8 bits, four pairs of bus lines D4, / D4 to D7, / D7 used only for a test with a large circuit scale are provided, and similarly, Four amplifiers 23 having a large circuit scale must be provided, and the circuit scale becomes large as a whole.

The present invention has been made in order to solve the above-mentioned problems, and its purpose is to perform a test under operating conditions suitable for actual use, to perform a highly reliable test, and to realize a chip area. It is an object of the present invention to provide a semiconductor memory device capable of reducing the size and a test method thereof.

[Means for Solving the Problems] FIG. 1 is a principle explanatory diagram for explaining the principle of the present invention.

In the data bus 1, two bit line pairs B0, / B0, B4, / B4 to B3, / B3, B7, / B7 are respectively connected to the respective bus line pairs D0, / D0 to D3, / D3. The data written in the memory cell is transferred through each bit line pair. The selection circuit 2 includes two bit line pairs B0, / B connected to the bus line pairs D0, / D0 to D3 / D3.
0, B4, / B4 to B3, / B3, B7, / B7 to the bus line pair D0, / D0, respectively.
To D3, / D3, and the test data written in the memory cell is read out via the selected bit line pair.

The first branch bus 3 and the second branch bus 4 branch off from the data bus 1, respectively. The two branch buses 3 and 4 compress test data input to the two branch buses 3 and 4 to compress each test data. It is connected to a data compression circuit 5 for determining the presence or absence of a defect.

Each pair of bus lines of the first branch bus 3 is provided with a latch circuit 6 and a first switch circuit 7. The first switch circuit 7 synchronizes the selection operation of the selection circuit 2 with each bit line pair B0, / B
Each test data written to each memory cell read via 0, B1, / B1, B2, / B2, B3, / B3 is latched by the latch circuit 6. Then, the first switch circuit 7
Is the next selected bit line pair B4, / B4, B5, / B5, B6, / B6, B
7 and / B7, the test data written to the respective memory cells are prevented from being latched by the latch circuit 6, and the previously latched test data is synchronized with the inhibition to prevent the test data from being latched. To enter.

On the other hand, a second switch circuit 8 is provided for each bus line pair of the first branch bus 3, and each bit line pair B4, / 4 selected next in synchronization with the selection operation of the selection circuit 2. B4, B5,
Only test data written to each memory cell read via / B5, B6, / B6, B7, / B7 is input to the data compression circuit 5.

[Operation] The bit line pairs B0, / B0 to B3 of the bit line pairs B0, / B0 to B7, / B7 connected to the bus line pairs D0, / D0 to D3, / D3 by the selection circuit 2 respectively. , / B3, each test data written to the memory cell via the selected bit line pair B0, / B0 to B3, / B3 is provided to the first branch bus 3 by the first switch circuit 7. Latched by the latch circuit 6
It is not input to the data compression circuit 5.

At this time, each test data latched by the latch circuit 6 is not input to the data compression circuit 5 via the second branch bus 4 by the second switch circuit 8.

Subsequently, when the selection circuit 2 selects the bit line pair B4, / B4 to B7, / B7 from the bit line pair B0, / B0 to B7, / B7, the selected bit line pair B4, / B4 to B7 , / B7 is input to the data compression circuit 5 via the second switch circuit 8. At this time, each test data previously latched in the latch circuit 6 by the first switch circuit 7 is input to the data compression circuit 5 at the same time.

The data compression circuit 5 to which the test data read via the bit line pairs B0, / B0 to B7, / B7 are simultaneously input.
Performs data compression based on each test data and outputs compressed data Z./Z which is used as a material for determining whether or not each cell has a defect.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. The same components as those described in the conventional example are denoted by the same reference numerals, and detailed description is omitted.

In FIG. 2, a data bus 11 composed of four pairs of bus lines D0, / D0 to D3, / D3 is connected to eight pairs of bit lines B0, / B0 to B7, / B7 to form a bus line pair D0. , / D0 have bit line pairs B0, B0, B4, /
B4 is the bit line pair B1, / B1, B5, / B5 on the bus line pair D1, / D1.
However, the bus line pair D2, / D2 has the bit line pair B2, / B2, B6, / B6,
The bit line pairs B3, / B3, B7, / B7 are connected to the bus line pairs D3, / D3, respectively.

A first gate circuit 12 constituting a selection circuit is provided between the transfer gate transistor T1 and the data bus 11 for each of the bit line pairs B0, / B0 to B3, / B3. On the other hand, the bit line pairs B4, / B4 to B7, / B7 are provided with second gate circuits 13 which similarly constitute a selection circuit between the transfer gate transistor T1 and the data bus 11. The first gate circuit 12 opens the gate in response to the control signal φ1, and selects each bit line pair B0, / B0 to B0 of the selected word line WL.
3, test data X0, / X written to memory cell 22 on / B3
0 to X3, / X3 are output to each bus line pair D0, / D0 to D3, / D3. The second gate circuit 13 opens the gate in response to the control signal φ2, and selects each bit line pair B of the selected word line WL.
4, the test data X4, / X4 to X7, / X7 written to the memory cell 22 on / B4 to B7, / B7 are output to each bus line pair D0, / D0 to D3, / D3. ing.

Therefore, by the first and second gate circuits 12 and 13,
Test data X0, / X0 to X3, / X3 from the bit line pair B0, / B0 to B3, / B3 and test data X4, / from the bit line pair B4, / B4 to B7, / B7 to the data bus 11. X4 to X7 and / X7 can be alternately output.

The data bus 11 between the amplifier 23 composed of the inverter circuits INV1 and INV2 shown in FIG. 3 and the data output circuit 25 provided in each bus line pair D0, / D0 to D3, / D3 has a first branch bus 14 And the second branch bus 15 is branched. The first branch bus 14 has a third gate circuit 16 composed of an N-channel MOS transistor T2 opened by the control signal φ1 and a fourth gate circuit composed of an N-channel MOS transistor T3 opened by the control signal φ2 in each bus line pair. 17 are provided. Also, both gate circuits
A latch circuit 18 is provided between the gates 16 and 17. In this embodiment, as shown in FIG. 4, a known latch circuit using four inverters INV3 to INV6 is provided. , / X0 to X3, / X3 are latched. Then, the test data X0, /
X0 to X3, / X3 are input to the data compression circuit 24 by the gate circuit 17.

On the other hand, the second branch bus 15 is provided with a fifth gate circuit 19 comprising an N-channel MOS transistor T4 which is opened by the control signal φ2 for each bus line pair. Then, the test data X4, / X4 to X7, / X7 are input to the data compression circuit 24 by the gate circuit 19. As shown in FIG. 7, the control signals .phi.1 and .phi.2 output the control signal .phi.1 having the logical value "H" in the first half cycle and the control signal .phi.2 having the logical value "H" in the second half cycle during one test cycle. Is output.

The data compression circuit 24 is composed of first and second compression circuits 24a and 24b having the same circuit configuration as shown in FIG.
The first compression circuit 24a outputs test data X0 output via one bit line B0 to B7 in each bit pair B0, / B0 to B7, / B7.
~ X7 is input. In the first compression circuit 24a, four NOR circuits 30 to 33 are provided in the input stage, and the test data X
0, X1 is the test data X2, X3 in the NOR circuit 31, the NOR circuit 32
Test data X4 and X5, and test data X
6, X7 are input respectively.

The outputs of the NOR circuits 30 and 31 are input to the NAND circuit 34, and the outputs of the NOR circuits 32 and 33 are output to the NAND circuit 35.
The outputs of both NAND circuits 34 and 35 are output to the NOR circuit 3
Output to 6. The NOR circuit 36 is connected to the data output circuit 25 via a nut circuit 37, and outputs the compressed data Z output from the NOT circuit 37 to the data output circuit 25.

Therefore, when the test data X0 to X7 are all logical values of “H”, the compressed data Z becomes “H” and the test data X0 to X7
If all X7 are logical values of “L”, the compressed data Z becomes “L”. If at least one of the test data X0 to X7 has a different logical value from the others, the compressed data Z becomes “H”.

On the other hand, the second compression circuit 24b generates each bit pair B0, / B0 to B7, / B7
, Test data / X0 to / X7 output via the other bit lines / B0 to / B7 are input. In the second compression circuit 24b, four NOR circuits 40 to 43 are provided in the input stage, the test data / X0, / X1 is supplied to the NOR circuit 40, and the test data / X2, / X3 is supplied to the NOR circuit 41.
However, the test data / X4 and / X5 are input to the NOR circuit 42, and the test data / X6 and / X7 are input to the NOR circuit 43, respectively.

The outputs of the NOR circuits 40 and 41 are input to the NAND circuit 44, and the outputs of the NOR circuits 42 and 43 are output to the NAND circuit 45.
The outputs of both NAND circuits 44 and 45 are output to the NOR circuit 4
Output to 6. The NOR circuit 46 is connected to the data output circuit 25 via a NOT circuit 47, and outputs the compressed data / Z output from the NOT circuit 47 to the data output circuit 25.

Therefore, when the test data / X0 to / X7 are all logical values of "L", the compressed data / Z becomes "L" and the test data / X7
When 0 to / X7 are all logical values of "H", the compressed data / Z
Becomes "H". If at least one of the test data / X0 to / X7 has a different logical value from the others, the compressed data / Z
Becomes "H".

The compressed data Z and / Z are output to a predetermined 1-bit output buffer circuit of the data output circuit 25. The output buffer circuit is composed of N-channel MOS transistors T5 and T6 as shown in FIG. 6. The gate of the transistor T5 receives the compressed data Z and the gate of the transistor T6 receives the compressed data / Z. Then, the inspection data DT is output to the output pad based on the logical values of both data Z and / Z.

Therefore, when the compressed data Z is "H" and the compressed data / Z is "L", that is, when the test data X0 to X7 are all "H" and the test data / X0 to / X7 are all "L", the test data DT becomes "H". On the contrary, when the compressed data Z is "L" and the compressed data / Z is "H", that is, when the test data X0 to X7 are all "L" and the test data / X0 to / X7 are all "H", the inspection data DT becomes "L". When both the compressed data Z and / Z are "H", that is, at least one of the test data X0 to X7.
Test data / X with logical value different from the other
When at least one of 0 to / X7 has a logical value different from the other, the test data DT enters a high impedance state.

Next, the operation of the semiconductor memory device configured as described above will be described.

Now, in a state where test data having a logical value of "H" is written in predetermined cells on eight bit line pairs B0, / B0 to B7, / B7 in the cell array of the semiconductor memory device, When the selection signal SL is output and the word line WL corresponding to each cell 23 is selected, the test data of each cell 22 is read and output to each of the selection circuits 12 and 13.
At this time, since the written test data has a logical value of "H", if each cell 23 is a normal cell and is correctly read, each bit line B0, / B0 to B7, / B7 All of the test data X0 to X7 output via one of the bit lines B0 to B7 become "H". Conversely, the test data / X0 to / X7 output via the other bit pair / B0 to / B7 are all "L".
At this time, the control signals φ1 and φ2 have not been output yet, and the logical value is “L”.

Subsequently, when the control signal φ1 having the logical value “H” is output and input to the first gate circuit 12 and the third gate circuit 16, the first gate circuit 12 and the third gate circuit 16
Opens, and test data X0, / X0 corresponding to four bit line pairs B0, / B0-B3, / B3 of eight bit line pairs B0, / B0-B7, / B7
To X3 and / X3 are selected, and the data bus 11 and the first branch bus 14 are selected.
Are latched by the respective latch circuits 18 through the latch. At this time, the test data X0, / X0 to X3, / X3 latched by each latch circuit 18 is not input to the data compression circuit 24 because the fourth gate circuit 17 is not open. The fifth gate circuit 19
Test data X0, / X0 to X3, / X3
There is no input to the data compression circuit 24 via the branch bus 15.

After the latch of the test data X0, / X0 to X3, / X3 is completed, when the control signal φ1 becomes “L” and the first gate circuit 12 and the third gate circuit 16 are closed, the logical value becomes “H”. Is output to the second gate circuit 13, the fourth gate circuit 17, and the fifth gate circuit 19.

Then, each of the second gate circuit 13 and the fifth gate circuit
19 opens, test data corresponding to the remaining four bit line pairs B4, / B4 to B7, / B7 of the eight bit line pairs B0, / B0 to B7, / B7
X4, / X4 to X7, / X7 are selected and input directly to the data compression circuit 24 via the data bus 11 and the second branch bus 15. At this time, since the fourth gate circuit 17 is also opened, the test data X0, / X0 to X3, / X3 latched by the latch circuit 18 are simultaneously input to the data compression circuit 24. Since the third gate circuit 16 is already closed, the test data X4, / X4 to
X7 and / X7 are not latched by the latch circuit 18.

Therefore, the data compression circuit 24 simultaneously outputs 8 bits, that is, the test data X1, / X1 to X0 to / B0 to / B0 to B7, / B7.
X7 and / X7 are input, and data compression is performed based on the test data X1, / X1 to X7, / X7. And test data X0 ~
When X7 is all "H" and test data / X0 to / X7 are all "L", that is, when each read cell 23 is normal, the compressed data Z is "H" and the compressed data / Z is "H". The data output circuit 25 outputs test data DT having a logical value of “H” indicating that the data is normal.

On the contrary, when there is at least one defective cell among the read cells 23, at least one of the test data X0 to X7 is "L" and at least one of the test data / X0 to / X7 is "H". At this time, the compressed data Z becomes “H” and the compressed data / Z becomes “H”, and the data output circuit 25 outputs the test data DT in a high impedance state indicating that at least one defective cell exists.

Then, after simultaneously testing the eight cells 23, test data having a logical value "L" is written in the eight cells 23 and read out in the same manner as described above, and the test data written in the eight cells 23 is subjected to data compression. The data is input to the circuit 24 to perform data compression. In this case, when each cell 23 is normal, the compressed data Z becomes "L" and the compressed data / Z becomes "H", and the data output circuit 25 outputs test data of a logical value "L" indicating normality. Output DT.

On the contrary, when there is at least one defective cell among the read cells 23, at least one of the test data X0 to X7 is "L" and at least one of the test data / X0 to / X7 is "H". At this time, the compressed data Z becomes “H” and the compressed data / Z becomes “H”, and the data output circuit 25 outputs the test data DT in a high impedance state indicating that at least one defective cell exists.

Then, when the test data of the logical values “H” and “L” is written and the test of the eight cells 23 is completed, the test of the next other eight cells 23 is performed by the same method.

As described above, in this embodiment, first, the bit line pair B0, /
The test data X0, / X0 to X3, / X3 from B0 to B3, / B3 are latched by the latch circuit 18 using the data bus 11 and the first minute bus 14, and then the bit line pair B4, / B4 to Test data from B7, / B7
X4, / X4 to X7, / X7 are simultaneously transmitted to the test data X0, / X0 to X7, /
Since X7 is read, eight cells 22 can be tested in one test cycle, so that the test time is shortened and the test operation is made more efficient.

Further, the first and second branch buses 14 and 15 branched from the data bus 11 having a small chip area are provided without using a data bus having a large chip area only for a test. Can be reduced in overall chip area.

Further, since the 4-bit test data is output to the data bus 11 in two separate steps, a data bus which increases the chip area only for the test is added and the data bus 11 outputs 8 bits at the same time.
Compared to the method of transferring the test data of bits, the conditions are more suitable for actual use, and an accurate and highly reliable test can be performed without generating noise or the like due to an increase in drive current.

Note that the present invention is not limited to the above embodiment,
For example, in the above embodiment, the eight cells 22 are transferred to the four pairs of data buses 11 twice, but the number of branch buses is increased, and the cells are transferred to the four pairs of data buses 11 three times or more. Is also good. In this case, for example, by providing a total of three branch buses, providing a latch circuit for each of the two branch buses, and additionally providing a control signal φ3 and the like,
The test data of 12 cells can be output to the four pairs of data buses 11 in three times, and the test of 12 cells can be performed in one test cycle.

Further, in the above embodiment, the data bus 11 is embodied as four pairs of semiconductor memory devices, but may be embodied as a semiconductor memory device having more data buses.

[Effects of the Invention] As described in detail above, according to the present invention, a test can be performed under operating conditions suitable for actual use, and an accurate and highly reliable test can be performed. It has an excellent effect that can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a test circuit diagram of a semiconductor memory device showing an embodiment of the present invention, FIG. 3 is an electric circuit diagram showing an amplifier, and FIG. Similarly, an electric circuit diagram showing a latch circuit, FIG. 5 is an electric circuit diagram showing a data compression circuit, FIG. 6 is a circuit diagram showing a partial output portion of the data output circuit, and FIG. 7 is an operation waveform of a test circuit. FIG. 8 is a test circuit diagram of a conventional semiconductor memory device. FIG. 9 is a test circuit diagram of a conventional semiconductor memory device. In the figure, 1 is a data bus, 2 is a selection circuit, 3 is a first branch bus, 4 is a second branch bus, 5 is a data compression circuit, 6 is a latch circuit, 7 is a first switch circuit, and 8 is a second switch. , D0, / D0 to D3, / D3 are bus line pairs, and B0, / B0 to B7, / B7 are bit line pairs.

Claims (2)

(57) [Claims] A plurality of bit line pairs (B0, / B0 to B7, / B7) are connected to each bus line pair (D0, / D0 to D3, / D3), and each bit line pair (B0, A data bus (1) for transferring data written to the memory cells via B0 to B7, / B7), and each bus line pair (D0, / D0 to D3, / D3) of the data bus (1)
And a plurality of bit line pairs (B0, / B0 to B7, / B7) connected to the bus line pairs (D0, / D0 to D3, / D3), respectively. The test data written to the memory cell through the line pair is transferred to the bus line pair (D0, / D0 to D0).
And a selection circuit (2) for outputting to each of the bit line pairs (B0, / B0 to B7, / B7) connected to each bus line pair (D0, / D0 to D3, / D3). And a data compression circuit (5) for simultaneously compressing the test data and determining whether or not each cell has a defect. The data bus (1) branches to the selection circuit (2).
The test data of each bit line pair (B0, / B0 to B3, / B3) selected earlier is input to the data compression circuit (5).
A branch bus (3), a branch from the data bus (1), and the selection circuit (2)
The test data of each bit line pair (B4, / B4 to B7, / B7) selected next is input to the data compression circuit (5).
A branch bus (4); a latch circuit (6) provided in each bus line pair of the first branch bus (3); and a latch circuit (6) provided in each bus line pair of the first branch bus (3). Each test data is latched in the latch circuit (6) in synchronization with the selection operation of the circuit (2), and the latched test data is transferred to each bit line pair (B4, / B4 to B4) to be selected next.
A first switch circuit (7) input to the compression circuit (5) in synchronization with the test data of (7 / B7); and a bus line pair of the second branch bus (4), A second switch circuit (2) that inputs only the test data of the bit line pair (B4, / B4 to B7, / B7) selected next in synchronization with the selection operation of the circuit (2) to the compression circuit (5). 8) A semiconductor memory device comprising: And reading and latching test data of the same content written in the plurality of memory cells, and then reading test data of the same content written in the other memory cells.
Semiconductor for compressing test data of another plurality of memory cells and test data of a plurality of memory cells which have been previously read and latched, and inspecting the presence or absence of a defective memory cell based on the compressed data Test method for storage devices.