JPH02237063A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten a semiconductor memory in retrieval time by a method wherein a function of comparing a memory information inside the memory with an external data and outputting the comparison result is additionally provided inside a memory chip which constitutes a data base. CONSTITUTION:Two transistors Q and Q are used in a cell C which stores the information of one bit, and provided that the transistor Q is formed in a D-type or an E-type corresponding to the memory information, the other transistor Q is formed in an opposed type. For instance, if the transistors Q10, Q11, Q14, and Q15 are of a D type and the transistors Q12, Q13, Q16, and Q17 are of an E type, the other transistors Q10, Q11, Q14, and Q15 are of an E type and the transistors Q12, Q13, Q16, and Q17 are of a D-type. Two or more cells C10, C11... are connected in series to constitute a cell block CB1, which is selected when a block selection line BS becomes 'H' in level. The cells C10, C11... are driven not by a work line selected by addressing but by pairs of data lines DL0, DL1... and data lines DL0, DL1... of inverted level which are determined to be 'H' or 'L' in level basing on comparison data D0, D2....

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a semiconductor memory capable of quickly retrieving stored information, the present invention relates to a semiconductor memory in which each word line is selected to form a memory cell, with the aim of reducing the maximum time required to retrieve one piece of data. In a semiconductor memory in which a plurality of transistors are connected in series to form a cell block and this is connected to a bit line via a block selection transistor, the transistors constituting the memory cell are a pair of depletion type and enhancement type transistors, and a word line is a data line given comparison data and an inverted data line given its inverted level, and the correspondence relationship between the depletion type and enhancement type transistors of a pair of series-connected memory cells, the data line, and the inverted data line is the relationship between the data line and the inverted data line. 1, O, and is configured such that comparison data is applied to a selected cell block through a data line and an inverted data line, and when a match occurs, current flows from the bit line to the selected cell block.

[Industrial application field]

The present invention relates to a semiconductor memory that allows quick retrieval of stored information.

Computer systems equipped with databases need to quickly retrieve information stored in memory.

[Conventional technology]

The memory used for the database includes a mask ROM as shown in FIG. The example in the figure is an enhancement type MOS} transistor Q, which is selected by the block selection line BS.
and the eight word lines WL o to WL,
S} Transistors Q lo to Q t t are connected in series to form a NANO type cell block CB, and transistors Q Io to Q I ? are formed by ion implantation. Information l and 0 are stored depending on whether the type is an enhancement type (hereinafter referred to as E type) or a depression type (hereinafter referred to as D type). The illustrated example is Q. , Q Ill QI4 is type D,
The rest are E type.

Block selection decoder BSD decodes address A3, A:1 and selects block selection line BS.

Row decoder WD has addresses A0 to Az. A+s to X8 are decoded and word line WL. ~WL, set one of them to L (low) and the rest to H (high).

In the above configuration, BS is set to H and cell block CB. , and when only the word line WL is set to L and the remaining word lines are set to H (this is the selection of WL.), all transistors except Q + z are turned on. At this time, bit line B
From L to cell block CB. Whether current flows or not depends on the type of transistor Q + z; if it is a D type, current will flow, but if it is an E type, no current will flow. In other words, a current flows or does not flow in accordance with 1 or 0 of the stored information of cell Qlz, and by detecting this, the stored information of cell QIz is successively output. Remaining transistors QIo, Qth, QI3~
Similarly, QI7 stores 1-bit information, and by setting the word line of the transistor to L1 and the remaining word lines to H, the information stored in the transistor is read.

In large-capacity ROM, multiple bits, for example, 8 bits, can be read simultaneously. In this case, eight cell blocks connected to eight bit lines (not shown) are selected by the block selection line BS, and by selecting a certain word line, for example, WL, the WL. The stored information of eight cells belonging to the cell is read out.

Figure 7 is an example of a combiator system that uses a mask ROM as shown in Figure 6 as the database memory l.
Memory 1 is 4M bits (512K bytes). C.P.
When U2 receives data to be searched (comparison data) from the outside, it sequentially gives addresses to memory l and continues searching until the same data is detected by comparison circuit 3.

[Problem to be solved by the invention]

In the system shown in Figure 7, if the access time to read 8 bits (6 bytes) of data from memory 1 is 200 ns, it will take 200 (ns) x 512 (KB) = 1 to search all the information (512 KB).
05 (ms) is required. This time is the maximum value required to search for 1 data, and although it may be possible to find it within this time, in the worst case, it will take about 105 ms to search for a huge amount of information. Therefore, in a system where comparative data changes constantly, even if the maximum value is
If it takes even 0.05 ms, there is a problem in terms of quick information retrieval. An object of the present invention is to shorten search time by providing a memory structure that allows direct access to comparison data and outputs comparison results.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention. In the present invention, two transistors Q. Using Q, one side of Q is set to type D or type E depending on the stored information, and the other side is set to the opposite type. In the illustrated example, one transistor Q. + Q+I+ QI41
Qls is D type (those with diagonal lines), Q r z + Q
Since ls + Q l & I Q + t are E type (no diagonal lines), the other transistors are mutually connected. +
(J+++ Q141 times., is E type, mutual., mutual.. mutual.
6. Mutual. , is of type D. Cell block CB. is a plurality of cells C,. +CI1+... are connected in series, and are selected when the block selection line BS becomes H.

The cells CIO+ Cll+... are not driven by word lines selected by addresses as in the past.
Comparison data Do. Data line DL. whose H and L level can be determined by DI+... , D.L. ．． . . . and the data line DL. whose level is inverted. , D.L. ．．・
It is a pair of...

DB is a data buffer that drives the data line DL to the same level as the comparison data, ■ is an inverter that drives the data line DL to the opposite level to DL, and BSD. is cell block CB. BL is a bit line that conducts current to cell block C B t, and Q1 is a block selection decoder for cell block C B +.
This is a block selection transistor that connects the bit line BL and the bit line BL.

[Effect]

In the configuration of FIG. 1, the comparison data D0-D, H and the transistor Q,. The E types of ~Ql, all match, and the L of comparison data D0~D, and the transistor times.

? Cell block C only when all E types of mutual, , match
A current flows through B t. For example, when data D0 is low, cell CI0 is on (Q., mutual, . are both on), when data D+ is low, cell CI1 is on, and when data D2 is high, cell CI! is on. On the contrary, if data D0 is H, then . is turned off, so cell CI6 is turned off.Similarly, when data D, is H, cell CI1 is turned off.
Off, Data D! When is L, 01■ is off.
The same applies to others. Since the cells are in series, cell block CB. A current flows through.

In a conventional ROM, data 1 and O are stored depending on whether one transistor in the cell is of the depletion (D) type or the enhancement (E) type, but the present invention stores data 1 and 0 by making one transistor of the cell a pair of transistors Q. Make Q into E, D type, or D,
Data 1 and O are stored depending on whether the type is E or not. In this way, the comparison data Do. D+,... and cell C
1. ．． C. A current flows through the cell block only when all stored data of , . In this way, current flows through the bit line/
It is possible to detect the match/mismatch between the comparison data and the cell block storage data without any flow, and output the result from the memory.

FIG. 2 is an explanatory diagram showing the logic of FIG. 1, and is a cell C1.

O R +. ．． OR,. is the transistor Q t o
+ Mutual + 11 equivalent or gate, AND, . is an AND gate meaning that both transistors are connected in series. The same applies to other cells. AND gate A N D of cell CIO''-Cl? AND gate that combines the outputs of Io~AND.? is the AND gate of cell C1.~Cl'l
means series connection. ORGATE OR. . ~OR1,
One input of data line DL. -DL, but the other input is H if the stored information is L, and L if it is H.

This storage information I/O corresponds to D type/E type transistors. OR, which forms a pair of each cell.

~ORI? The human power on one side is the data line DL. ~DLt, and the other input is L if the stored information is L, and H if the stored information is H.

〔Example〕

FIG. 3 shows a storage device capable of outputting search results using the above-mentioned cell block CB. The cell blocks CB are arranged in a matrix as shown, and a sense amplifier SA is provided for each bit line BL. The illustrated example has 2048 bit lines BL, -BL. . 4. and 256 block selection lines BS
,~Blocked into a 2048 x 256 matrix using BSzsi. Comparison data D0 to D are given to all data buffers DB+-DBzsb simultaneously, and when one of them is selected by address A0 to A, it is simultaneously given to 2048 cell blocks CB selected by the same block selection line BS. The same comparison data D0 to D7 are input.

For example, when data buffer DB, is selected, cell block C B t-CB,. 4. -, the same comparison data D0 to D are applied at the same time, this is compared with the stored information of the cell block, and the cell block that matches causes a current to flow through its bit line. For example, when a match occurs in cell block CBt-+, a current flows through bit line BLl, and this is detected by sense amplifier SA.

Therefore, l data (8 if a cell block has 8 cells)
The time required to search for 1 bit data is 1/2 that of conventional methods.
It is shortened to 048.

A.E. -AE. . 48 is each sense amplifier SA. ~SA2
. 4, and has a function of indicating which sense amplifier's output is 1 using 11 bits (2048 bits) of data. For example, sense amplifier SA. When the output of the sense amplifier is 1 and the output of other sense amplifiers is O, all address encoders AE, ~AE
2.48 outputs are all When the output of OSSA2 is 1 and the output of the remaining SAs is O, the output of AEz is 1000000
0000, the outputs of other AEs are all 0, and the same goes for SA. When only the output of 4, is 1, AE. . 4l
It is assumed that the outputs of AE are all 1 and the outputs of other AEs are all 0. When the output of this AE is applied to the output buffer CDOB through the 11-bit data path CDB, it is possible to determine through an external terminal in which cell block the comparison data has failed.

Matches occurring in multiple cell blocks at the same time (use)
However, in this case, for example, the sense amplifier SA. −
S.A. . 48 1.0 outputs may be sequentially applied to the data path.

FIG. 4 shows another embodiment of the invention. In this figure, only the data buffer DB portion in FIG. 3 is shown. The data buffer of this example includes an address decoder AD, and when the control signal φ is H, it outputs the comparison data DO-D7 to the data lines DL o to DL, and performs the comparison described in FIGS. 1 to 3. Enables data search with functions. On the other hand, when the control signal φ^ is set to L, the 8-bit output O~■ of the address decoder AD is transferred to the data line DL o~DL? output to enable normal (1-bit) memory access. G il+ Gi3+ cts is orgate, G
1 is an AND gate, Gi4 is an inverter, and G1 is a NOR gate (i=0 to 7).

FIG. 5 is a diagram showing another memory device capable of outputting search results, and CA is a cell array composed of one transistor per bit as in FIG. 6. This cell array CA is 20
It has 48 bit lines, which are divided into 8 bit lines and input to each of the sense amplifier groups SAo to SA. Then, each sense amplifier group SA. The 8-bit output of ~SAt is simultaneously input to comparison circuits CMP and ~CMPzsb and compared with comparison data D0 to DL. CMS, ~CMSz
sh is the output of each comparison circuit, ■ indicates a match, and 0 indicates a mismatch.

A.E. ~AEzSh is an address encoder that outputs the address of the corresponding comparison circuit CMP when the comparison output CMS is 1, and outputs all 0s (8 bits) when it is 0, and CDB is an 8-bit data path. [Effects of the Invention] As described above, according to the present invention, information stored in the memory and external data are compared within the chip of the memory that constructs the database. Since a function to output the results has been added, it has the advantage of greatly reducing the time required to search the database.

[Brief explanation of the drawings] Figure 1 is a diagram of the principle of the present invention. Fig. 2 is an explanatory diagram showing the logic of Fig. 1, Fig. 3 is a block diagram showing an embodiment of the present invention, Fig. 4 is a main part configuration diagram showing another embodiment of the present invention, and Fig. 5 is a search diagram. FIG. 6 is a block diagram showing an example of a conventional mask ROM; FIG. 7 is a block diagram of a computer system equipped with a database. In Figure 1, CB. is a cell block, C. ．． ,C. ■,...
... is a memory cell, QI0 and times. . ，・・・・・・
is a pair of transistors, DL. , D.L. ．．・・・・・・
is the data line, DL. , DL, . . . are inverted data lines.

Claims (1)

[Claims] 1. In a semiconductor memory in which a plurality of transistors each selected by a word line and constituting a memory cell are connected in series to form a cell block, and this is connected to a bit line via a block selection transistor, the memory cell The transistors forming the circuit are a pair of depletion type and enhancement type transistors (Q, ■), and the word lines are a data line (DL) to which comparison data is applied and an inverted data line (■) to which the inverted level thereof is applied, The correspondence relationship between the depletion type and enhancement type of a pair of series-connected transistors (Q, ■) of memory cells and the data line and inverted data line is determined according to 1 and 0 of the memory information, and the selected cell block (CB) is determined. A semiconductor memory characterized in that comparison data is applied through a data line and an inverted data line, and when a match occurs, a current flows from a bit line (BL) to the cell block (CB). 2. A semiconductor in which comparison data is given to the selected block (CB) through the data line and the inverted data line in the first term, and when a match is found, current flows from the bit line (BL) to the cell block (CB). In a memory, in a plurality of transistors (Q, ■), a signal (data line, inverted data line, The information on the target transistor pair can be obtained by applying an inverted signal to the data line and inverted data line connected to the target transistor pair. A semiconductor memory characterized by allowing current to flow from the bit line.