JPS62120698A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To easily evaluate the speed of a memory by feeding back an output of the memory to an address. CONSTITUTION:The output of the memory is fed back to one address ADD through an AND gate 2. Memory contents '1' and '0' at respective addresses '0', '1' are previously written in the memory M. When a control input terminal CTRL is '0', the output of the memory M is fed back to the address ADD through an AND gate 1, the circuit forms a kind of an oscillation circuit and an oscillation waveform is obtained from the circuit. Since an oscillation cycle 1/2(td) can be evaluated as an access time of the memory, the speed of the memory can be easily evaluated by counting up the oscillation waveforms.

Description

[Detailed Description of the Invention] [Summary] By feeding back the output of the memory to the address, the speed of the memory can be easily evaluated.

[Industrial application field]

The present invention relates to a test circuit for semiconductor memory circuits, and more particularly to a test circuit that is mounted on a chip and facilitates evaluation of memory speed.

[Conventional technology]

Normally, testing of semiconductor memory circuits is performed in the wafer state.
A second test is being conducted after the chips are divided into chips and sealed in containers. The first test was conducted using an IC tester and a wafer blower, but it was difficult to evaluate the memory speed at that time, so the speed test was performed in the second test using a speed evaluation test program. . In addition, in ICs where memory and logic are mixed, especially when the memory peripheral logic has a gate array configuration, the memory speed itself is evaluated because the speed of the input/output logic circuit is added to the evaluation of the memory section. Accurate evaluation is not possible.

Furthermore, in gate arrays, since the logic configuration is free and the user can freely configure it, there is a drawback that evaluation programs corresponding to each configuration are required, and a large number of programs are required, resulting in a loss of versatility.

[Problem that the invention seeks to solve]

The present invention aims to improve the problem that it is difficult to evaluate the speed of the conventional semiconductor memory device.

[Means for solving problems]

In the present invention, a test circuit that feeds back the output of the memory to the address is added to form a type of oscillation circuit, and by counting the frequency, it is possible to evaluate the speed of the memory. .

[For production]

Taking the schematic diagram of the present invention shown in Fig. 1 and explaining it, Fig. 1 (
In al, A is the input logic circuit 2M is the memory, B
is the output logic circuit, ■ is the input terminal.

0 is an output terminal. Further, CT Rt is a control input terminal, ■ is a control input gate, and 2 is an AND gate. In the configuration shown in FIG. 1, the output of the memory is fed back to one of the addresses ADD via an ANDNO gate. Then, the memory contents at the address O are written to 1 in advance in the memory M, and the memory contents at the address 1 are written to 1 as shown in FIG.
When RL is "0", the output of memory M is fed back to address ADD through the ANDNO gate, and the circuit shown in Figure 1 forms a type of oscillation circuit, and an oscillation waveform as shown in Figure 1 (bl) is obtained. 172 (td) of the oscillation cycle can be evaluated as the memory access time.Therefore, by counting the oscillation waveforms, the memory speed can be easily evaluated.

During normal operation of the memory, the feedback system is turned off by inputting "1" to the control input CTRL. In addition,
When inverting the logic of the feedback loop, change the data “1” and “0” to be written in the memory M as shown in Figure 1 (C).
You can do the opposite.

〔Example〕

FIG. 2 shows an outline of the overall layout of an embodiment in which the present invention is applied to a gate array equipped with a RAM. This embodiment is an example in which test writing and memory evaluation can be performed using terminals 21 to 2505 bins provided directly on the memory. In addition, a slightly more detailed configuration diagram equivalently shown in FIG. 3 is shown.

In FIGS. 2 and 3, 20 is a semiconductor substrate, 21 to 2
Reference numeral 5 indicates signals (and terminals) of the test circuit, and these five signals are used to write data for testing the memory and to switch between the test mode and the normal mode. Further, 26 and 27 are gate circuits connected to the memory M, and are constituted by a gate array OA. The following embodiments will be described in the case where the feedback game (FC) is a NOR gate.

First, in order to write data for testing the memory, the following operations are performed in order starting from the terminal provided directly on the memory.

■ Set the control signal 22 (CTRL) to "1" to cut the feedback loop.

■ Set 21 to “0” and specify address O. 24 “
Set Di and WE to write mode by setting 0”25 to “1”.

■ Set 25 to “O” and write the data to address O (A in the diagram).
Write 0”.

■ Set 21 to "1", 24 to "1", and 25 to 1.

■ Set 25 to 0'' and set data “1” to address 1 (B in the diagram)
Write.

■ Set 25 to “1”.

■ 21; fr: Set to “O”.

■ Set 22 to “0” and connect the feedback loop.

■ Measure the oscillation waveform with a frequency counter.

In the above, a feedback loop was formed using memory cells A and B on the same bit line, and the speed in the X direction was evaluated by oscillation. By doing so, the speed in the Y direction can be evaluated. Also, although Figure 2 evaluates the speed of memory cells along one bit line, if necessary, two memory cells along each of two or more bits (or word lines) can be evaluated. can be used to form a feedback loop, each with a separate control system, to switch one line at a time to perform each test.Alternatively, two or more lines along each bit and word line can be By forming feedback loops using memory cells and providing completely different control systems for each,
The test may be performed by switching between and Y.

FIG. 4 shows an embodiment in which the present invention is applied to a 256×4 RAM. In the figure, 31 is a memory array, 32 is an X decoder driver, 33 is a Y decoder driver, 34 is a sense amplifier and write amplifier section, and FG is a feed bank gate. Also, Ao to A4 are X address input terminals, A and ~A7 are Y address input terminals, WE is a write enable terminal, DOI to DO4 are RAM data output terminals, DI and ~Dr4 are data input terminals, and CTRL is This is a control input terminal.

Double nine terminals, namely Ao, Do, , DI, ,
The 5 terminals WE and CTRL are used as external terminals.

With the above configuration, CTRL is set to 1, the feedback loop is cut off, and when the address terminals A-O', the cell is set to "0".
, when address A0 is g1'', cell B is written as 11'', CTRL is set to 0, and a feedback loop is connected. Then, oscillation occurs in the same way as above, so by counting the frequency, you can evaluate the speed of the memory. can be done.

〔Effect of the invention〕

As described above, according to the semiconductor memory circuit equipped with the test circuit of the present invention, by feeding back the memory output to the address input, it can be used in the wafer state even in the case of a single memory or a mixture of logic and memory. This has the advantage that memory speed can be evaluated during the blobbing test. In particular, when logic and memory are mixed, it has the advantage of being able to evaluate the speed of the memory section itself, excluding the influence of the human-generated logic circuit.

Furthermore, since these evaluations are performed by counting frequencies, there is an advantage that they can be performed without the need for a conventional expensive memory tester.

[Brief explanation of drawings]

Figure 1 (al (b)) (C1 is a diagram showing the concept of the present invention, Figures 2 and 3 are an overall diagram and an equivalent partial diagram of an embodiment of the present invention, and Figure 4 is a diagram showing the concept of the present invention. It is a configuration diagram of the embodiment.Main symbols l...Control input gate 2...Feedback gate M...Memory A...Input gate B...Output gate CTRL...Control signal ADD ... Address input Patent applicant Fujitsu Ltd. agent Patent attorney Tama Mushi Kugobe (1 other person) Outline diagram of the present invention Figure 1 Overall diagram of the embodiment Figure 2 (CTRL) Figure 2 (CTRL) of the embodiment of the present invention Detailed drawing of main parts Fig. 6 Circuit diagram of another embodiment of the present invention Fig. 4

Claims (1)

[Claims] It is equipped with a test circuit that has a feedback loop that feeds back the output of the memory to the address, and a gate provided in the feedback loop.During the test, the gate is opened and the feedback loop constitutes an oscillation circuit, and the oscillation frequency is used to control the memory. A semiconductor memory circuit characterized by evaluating speed.