JPS59104779A - Selection control system of memory array card - Google Patents

Abstract

PURPOSE:To realize an access to a memory which packages plural memory array cards having different memory capacities by providing a memory array card selection index table and using the signal and the address to identify the memory array cards. CONSTITUTION:For a memory containing memory array cards of 1M and 4M bytes, a memory array selection index table 21 is selected by means of an address of four bits (e.g. 08, 09, 10 and 11) sent from an address register 20 and the signal which identifies the packing state of the memory array card that informs that the memory array cards of 4M bytes is packaged from slots 0-3. The selection lines of SEL0-SEL7 are connected from the table 21 to the slots 0-7 of a memory 22 which packages eight memory array cards for example. The index table 21 contains a list as shown by a table 1 and selects the memory array card of each slot of the memory 22 to realize an access to the memory 22 with an address code RA given from the register 20 and an address code SA given from a signal line 23.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a storage device used in an information processing device, etc.
In particular, the present invention relates to a memory array card selection control method that enables access to a storage device configured by mounting a plurality of memory array cards with different storage capacities.

(b) Background of the technology In recent years, advances in memory elements have increased the storage capacity of the memory elements themselves, and the storage capacity of memory array cards made up of these elements has also increased significantly, increasing the storage capacity of each memory array card. Something different is emerging. For example 64KR
There are memory array cards equipped with AM and memory array cards equipped with 256KRAM, and the former has a capacity of 1M bytes and the latter has a capacity of 4M bytes with the same size memory array cards. Therefore, increasing the basic storage capacity of a computer or adding memory array cards to expand the storage capacity can be achieved with a small number of memory array cards. But 1
Since the storage capacity of the memory array card F is large, when implementing the necessary storage capacity in the computer system, depending on the case, it may end up having more storage capacity than necessary. Therefore, if it becomes possible to access a storage device equipped with a mix of 1 Mbyte memory array cards and 4 Mbyte memory array cards, it will be possible to construct a reasonably rational computer system, and a countermeasure is desired. .

(C) Object of the Invention Based on the above-mentioned needs, the object of the present invention is to select a memory array card that enables access to a storage device configured by mounting a plurality of memory array cards with different storage capacities. The objective is to provide a control method.

(d) Configuration of the Invention The configuration of the present invention is a storage device configured by mounting a plurality of memory array cards with different storage capacities.

A memory array card selection index table is provided, and the memory array card is identified by a signal and an address.

This allows access to the storage device.

(e) Embodiment of the Invention The embodiment of the present invention is based on a 1M byte memory array card equipped with a 64KRAM chip and 2
Using a storage device mixed with a 4MB memory array card equipped with a 56KRAM chip,
It has the necessary and sufficient storage capacity, and since the storage capacity will naturally differ when mixed, it is not enough to simply select by memory address as in the case of configuring only memory array cards with the same capacity, so it was implemented. This makes it possible to freely control the selection of memory array cards according to the storage capacity of the memory array cards.

The figure is a block diagram of a circuit showing one embodiment of the present invention.

For example, 08 from the address register 20 via the signal line 24.
, 09, 10.11, and the mounting state of the memory array card given through the signal line 23 which notifies that a 4M byte memory array card is mounted in slots 0 to 3. The memory array card selection index table 21 is selected using the signal. Memory array card selection index table 21 to 5ELO.

5ELI, 5EL2.5EL3, 5EL4, 5EL5,
Each selection line 5EL6, 5EL7 corresponds to each slot 0.1 .
2.3, 4, 5, and 6.7, respectively. In this embodiment, the 4M byte memory array card is in the slot 0~
By installing only slots 3 and 3, the total capacity up to 16MB can be covered, so slots 4 to 7 are equipped with 4
We are not considering implementing an M-byte memory array card.

The memory array card selection index table 21 has a list as shown in the table below, and the address code RA from the address register 20 and the address from the signal line 23, :II-FS.
A selects the memory array card in each slot of the storage device 22 and enables access.

SA represents the state in which 4 Mbyte memory array cards are mounted in slots 0 to 3 of the storage device 22, and the address code is determined by the mounting position and number of cards, and is 0 to F. Also, RA represents the state of the address in the address register 20, and since it is formed of 4 bits, the address code is θ.
~F.

This shows a case where an M-byte memory array card is not installed. Since the signal indicating that a 4M byte memory array card is mounted is not given from the signal line 23, the address code USA becomes "O".

Therefore, the address from address register 20.

The address code via the signal line 23 is given to the memory array card selection index table 21, and when the address code is OO, the memory array card selection index table 21 indicates that slot O of the storage device 22 is selected via 5ELO. 0
Next, when the address code is 01, it indicates that slot 1 of the storage device 22 is selected via 5ELI. Next, when the address code is 02, it indicates that slot 2 of the storage device 22 is selected via 5EL2. Similarly, it will be shown that 1 to 8 Mbytes can be accessed in units of 1 Mbyte up to address code 07.

(2) The table shows a case where a 4M byte memory array card is installed in slot number O of the storage device 22, and 1M byte memory array cards are installed in slot numbers 1 to 7. When there is a signal from the signal line 23 indicating that a 4M byte memory array card is installed in slot 0 of the storage device 22, the SA of the address code is 1, and when the address code is 10°11.12.13, the SA of the storage device 22 is Slot 0 is selected and 1 of the 4MB memory array card is selected.
Portions corresponding to M bytes are each selected, and a total of 4 Mbytes can be accessed for slot number O. Address codes 14 to LA are slot 1 of the storage device 22, respectively.
~7 is selected, 7 dress code 10~IA and 1~II
Indicates that M bytes can be accessed in units of 1 M byte.

Table 0 shows a case where a 4M/\byte memory array card is installed in slot number 1 of the storage device 22, and 1M byte memory array cards are installed in slot numbers 0 and 2 to 7. When there is a signal that a 4M byte memory array card is installed in the slot/node 1 of the storage device 22, the address code SA becomes 2 and the address code becomes 2.
When it is 0, slot 0 of the storage device 22 is selected. When the address code is 21, 22, 23, 24, the storage device 22
Slot 1 is selected, and each portion corresponding to 1M byte of the 4M byte memory array card is selected, 1 total 4.
M bytes are accessible for slot number 1. When the address is 25 to 2A, slots 2 to 7 of the storage device 22 are selected respectively, and when the address code is 20 to 2A, 11M is selected.
Bytes are selected and made accessible in IM byte units.

■The table shows that the 4MB memory array card is the storage device 22.
■The front side has a 4MB memory array card in slot 2 of the storage device 22 only, ■The front side has 0 and 2, ■The front side has 1 and 2, ■The front side has a 4MB memory array card in slot 2 of the storage device 22. , 0 table is 3
Only, the [phase] table is for 0 and 3, the ■ table is for 1 and 3, the 0 table is for 0, 1, and 3, the [phase] table is for 2 and 3, and the [phase] table is for 0 and 2.
and 3, the [phase] table shows a case in which 4 Mbyte memory array cards are mounted in 1, 2, and 3, and the [phase] table shows a case in which 4 Mbyte memory array cards are mounted in 0, 1, 2, and 3, respectively.

(f) As described in detail, unlike the conventional method in which the mounting position of the memory array card in the storage device is physically determined, the present invention allows the mounting position to be determined freely. You can also change it.

The storage capacity can be changed by replacing the memory array card.

When memory array cards with different storage capacities are mixed,
It is also possible to use a memory array card with a large capacity with a memory array card with a small capacity, and how to use addresses to select a memory array card is different between a large capacity memory array card and a small capacity memory array card. Although it is different from the above, it has a great effect because it can be accessed freely without being conscious of it.

BRIEF DESCRIPTION OF THE DRAWINGS The figure is a block diagram of a circuit showing an embodiment of the present invention. 20 is an address register, 21 is a memory array card selection index table, 22 is a storage circuit, and 23 is a memory array card of 4 MB installed in any or all of slot numbers 0 to 3 of the storage device 22. Signal line shown, 2
4 is an address signal line from the address register 20.

Claims (1)

[Claims] In a storage device configured by mounting a plurality of memory array cards with different storage capacities, a memory array card selection index table is provided, and the storage device can be accessed by a signal and an address that identify the memory array card. A memory array card selection control method characterized by: