JPS59148963A - Control system of storage device - Google Patents

Abstract

PURPOSE:To use memories with different storage capacity efficiently by allowing an access control part to select a memory unit while referring different storage capacity included in plural memory units to convert an address signal. CONSTITUTION:The memory units 10aa-10nn having different storage capacity use a data bus and an address bus in common and are controlled by a memory access control part (MAC) 30a. Each memory unit 10ii has a memory unit mounting storage capacity specifying circuit 15 in addition to a memory array 11, an address register 12, a write data register 13, and a read data register 14 and transfers and holds the data to/in a memory constitution control circuit 31. The MAC 30 selects each memory unit 10ii and accesses an address register 12 while referring the mounted storage capacity of each memory unit 10ii to convert an input address signal. Thus, the memory units having different storage capacity can be efficiently used.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to improvements in storage device control schemes in data processing systems.

(b) Background of the Technology In recent years, with the development of semiconductor technology, particularly integration technology, high-speed, large-capacity IC memories based on MO8DRAM have come to be provided at low prices as internal main memories in data processing devices. These MO8DRAM memories have a storage capacity of 64 kilobits (Kb) or 2
56 Kb, a plurality of memory chips are mounted on a printed wiring board, etc., and a 1 megabyte (MB) or u4MB memory unit is used as an intermediate mounting unit, and one or more memory units are housed in a housing. It is used as a storage device.

(e) Prior Art and Problems FIG. 1 shows a conceptual block diagram of a conventional storage device control system. 10a, b, e, . . . are memory units, 20a, b, c are memory unit selection signals, and 30 is a memory access control unit (MAC). The memory units 10a, b, c...n have the same storage capacity, and the memory units 10a, b, -c
...n and the MAC 30 write data in the storage device via a common address bus and data bus,
Perform read operation. However, as mentioned above, IC memory is becoming larger in capacity and lower in price over the years, but the mass production effect of manufacturing is a major factor in the market price, so products of the same series that differ only in capacity are Production is limited to relatively large-capacity types that are the mainstay of production, and there are cases where previously developed small-capacity types have been discontinued due to unprofitability and are no longer available.

Since IC memory usually has a 2n-bit configuration, the storage capacity ratio between the old small-capacity type and the new large-capacity type is also 2.
For example, in MOS DRAM, it is 16Kb.
It changes from 64 Kb to 256 Kb, and it is characteristic that the increase in one step is extremely quick, about two years, compared to the useful life of electrical equipment, for example, several years. Therefore, when it is expected that the storage capacity will be increased after the data processing device is shipped, the installed storage capacity of the memory units 10a and 10b at the time of shipment may be, for example, IMB, but at the time of expansion, the address method in the memory array chip will be changed. Although there is no difference in the method since address control is performed to match chip select and multi-address, when using a mixture of memory units with a 1:4 mounting storage capacity like this, the host device, for example, central control, If the address signal associated with the access from the device (CPU) is used as is to select the address of the memory unit, the increased area for a large capacity memory unit will not be selected for 3MB. This has led to problems in control, such as poor usage of memory units, or system failures due to lack of access to small memory units.

(d) Purpose of the Invention In order to eliminate the above-mentioned problems, the present invention is designed to solve the above-mentioned problems in a storage device that is composed of multiple memory units with different installed storage capacities, without being aware of the memory units with different capacities from the outside. It is intended to provide a control method that allows access in the same way as a storage device configured with memory units of the same capacity.

(e) Structure of the Invention The object is to share an address bus and a data bus in a storage device in a data processing system, and a plurality of memory units having different installed storage capacities each record and hold its own installed storage capacity. The means and memory access control section receive the implemented storage capacity data held by each memory unit to create and hold address data for each memory unit, and the memory access control section receives an input address signal accompanying memory data input/output. Control of a storage device characterized by comprising means for selecting each memory unit by referring to the address data and means for converting an input address signal, and continuously addressing memory units having different installed storage capacities. This can be achieved by providing a method.

(f) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings.

4- FIG. 2(a) shows the storage device ff? in one embodiment of the present invention.
A block diagram of the control system; FIG. 2(b) is a functional block diagram showing the configuration of its main parts; FIG. 2(e) is a block diagram of the configuration of the memory access control unit (MAC) 30a;
Figures (a) and (b) are examples of memory unit address assignment correspondence, and Fig. 4 is an example of conversion of memory unit selection addresses.

In the figure, 10aa, bb, cc-nn are memory units, and 30a is a memory access control unit (MAC).
, 11 is a memory array, 12 is an address register, 13
is a write data register, 14 is a read data register, 1
5 is a memory unit mounted storage capacity designation circuit, 20a;
b, c... nu memory unit selection signal, 21a.

b, c-n are address signals, 22a, b, c-・-
・n ld write data, 23a, b, c-n read data, 25a.

b, c-n are memory unit mounting storage capacity signals, 31 is a memory unit configuration control circuit, 32a, b, c...
...n is the memory unit installed storage capacity register, 3
3a, b, c...n are memory unit selection address registers, 34 is an AND circuit, and 40 is a memory unit address signal.

The memory units 10aa, bb, cc-nn have a large number of I-C memory chips mounted on, for example, a printed wiring board, as in the past, and have a storage capacity for intermediate mounting units or control purposes.For example, the memory units 10aa, cc are 4MB, 10b.
b.

nn is a unit of storage means having IMB, for example 1
It is constructed on a single printed wiring board or, in some cases, on multiple boards. The MAC 30a is a memory unit 1 connected to a common address bus and data bus under the control of a central processing unit (CPU) for external access for write or read operations in the storage device of FIG. 2(a).
It has a function to control access to 0aa, bb, and cc-nn. and memory unit 10aa,
bb, cc-nn are memory unit 1 in FIG. 2(b)
As typically shown by 0aa, an address register 12 for accessing the memory array 11 as in the conventional case.
Write data register 13 for inputting and outputting , data, and data.
In addition to the read data register 14, in one embodiment of the present invention, a memory unit mounting storage capacity designating circuit 15 is provided with a fixed storage means to determine the mounting storage capacity of the self-memory unit, for example, as shown in the middle part of FIG. During the initialization operation of the device, the control section 30b of the MAC 30a has an auxiliary storage section 30c composed of a fixed storage element (ROM), for example.
The data held by the designated circuit 15 is accessed and stored in the memory unit mounted storage capacity signals 25a, b, according to the storage control program held in the storage area of the auxiliary storage section 30c.
c... ・n, and the memory unit mounted storage capacity registers 32a, b, c of the memory configuration control circuit 31.
n is transferred and held. In addition, the control unit 30b has registers 32a, b, c...n in order to continuously control the configuration of the entire storage capacity of the memory units 10aa, bb, cc...nn. c... Refer to the data of n\Memory unit selection address data, for example, as shown in the lower part of Fig. 4, sequentially from register 33a to IMB storage capacity fkk.
The unit is 0000.1000.0100, 1001 and the start address of each register is set, and the correspondence is made as shown in the example of memory address allocation of the memory unit shown in FIG. 3(a). If it is convenient to configure it as shown in Fig. 3(b) 7-, register 3 is omitted.
If the start address of each memory unit is set to 0000.0100.0101.1101 in order from 3a, the MAC 30a will respond to external access by setting the start address of each memory unit l0aa, bb, cc, etc.
- It is possible to perform a storage operation by accessing as nn k consecutive addresses in the same way as in the past.

(g) As described in detail, according to the present invention, even when combining memory units with different installed storage capacities, it is possible to keep in mind the structure of memory units with the same installed storage capacity, similar to the conventional storage device with a combination of the same capacity. A storage device control method with high storage capacity efficiency can be obtained.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional storage device control system.
FIG. 2(a) is a block diagram of a storage device control system according to an embodiment of the present invention, FIG. 2(b) is a block diagram of its main part configuration, and FIG.
AC), FIGS. 3(a), 8-(b), and FIG. 4 are diagrams showing an example of address assignment correspondence of the self-memory unit, and FIG. 4 is a diagram showing an example of conversion of a memory unit selection address. In the figure, 10a, b, c-n, 10aa+
bb, ccnn are memory units, 30,30
a is a memory access control unit (MAC), a 15H memory unit mounting storage capacity designation circuit, and 33a, b,
c-n is a memory unit selection address register. Figure 1 Figure 2 Ca-) Figure 2 (i7) Figure 2

Claims (1)

[Claims] In a storage device in a data processing system, a plurality of memory units that share an address bus and a data bus and have different installed storage capacities each have a means for recording and holding their own installed storage capacity and a memory access control unit for each memory unit. The memory access control unit receives the mounted storage capacity data held by the memory unit and creates and holds address data for each memory unit. 1. A control method for a storage device, characterized in that it includes means for selecting a memory address signal and means for converting an input address signal, and allows continuous addressing even in memory units with different installed storage capacities.