JPH11143767A - Memory switching processor and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory switching processor for increasing a memory capacity for a computer circuit having a limited address space without necessitating plural memory chips. SOLUTION: This device is provided with a memory part 21 constituted of one memory chip in which plural memories are incorporated, and a second address is assigned to each memory as a physical address in the memory chip, and a memory switching control circuit 23 for selectively switching the plural memories by generating at least one of a selection signal and one part of the first address generated from an MPU 22 as one part of the second address to be applied to the plural memories in the memory part 21, adding one part of the second address to the first address for generating the second address, and applying it to the memory part 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory switching processing apparatus and method for switching a plurality of memories in a computer circuit having a limited address space in order to increase the memory capacity.

[0002]

2. Description of the Related Art Generally, in a computer circuit,
Since it is often mounted on a small device, it is required to reduce the size and cost of the device itself. Therefore, a small-scale microcomputer is used. In this microcomputer, an increase in memory capacity is required because software becomes more complicated as technology advances. However, in this microcomputer, since the address space is limited, a plurality of memory chips (ICs: Integrated Circuits) are assigned to the same address space, and these memory chips are switched.
The aim is to increase the memory capacity.

FIG. 4 shows an example of the configuration of a conventional memory switching processor for switching a plurality of memory chips allocated to the same address space as described above.

[0004] In FIG. 4, reference numerals 11 to 14 denote, for example, four memory chips. One of them is a common memory 11, the other is a bank 1 memory 12, a bank 2
The memory 13 and the bank 3 memory 14 are used. These common memory 11, bank 1 memory 12, bank 2 memory 1
The third and bank 3 memories 14 have address input terminals corresponding to the respective capacities. Here, the common memory 11
Is 32 kbytes, for example, and thus has 15 address (A14 to A0) input terminals. Bank 1
Memory 12, bank 2 memory 13, and bank 3 memory 1
4 has, for example, 16 kbytes, and thus has 14 address (A13 to A0) input terminals.

A common memory 11, a bank 1 memory 1
2, the bank 2 memory 13 and the bank 3 memory 14 are connected to an MPU (Micro Processing Unit) 15 via an address bus and a data bus, respectively. further,
A chip select signal for selectively reading data from the memories 11 to 14 is given to the common memory 11, the bank 1 memory 12, the bank 2 memory 13, and the bank 3 memory 14 by the memory switching control circuit 16. .

FIG. 5 shows an example of the arrangement of the common memory 11, the bank 1 memory 12, the bank 2 memory 13 and the bank 3 memory 14 in the address space. That is, when the common memory 11 is 32 Kbytes,
７7FFF, bank 1 memory 12, bank 2 memory 13 and bank 3 memory 14
Is 32 kbytes, and if unused blocks are included, each has an address of 0 to 3FFF. Then, the MPU 15 controls the common memory 1
Addresses from 0 to 7FFF are assigned to 1 and addresses from 8000 to BFFF are assigned to the bank 1 memory 12, the bank 2 memory 13, and the bank 3 memory 14.

FIG. 6 shows an example of the memory switching control circuit 16 in detail. In FIG. 6, the memory switching control circuit 16 takes in two higher address signals (A15, A14) out of the 16 address signals (A15 to A0) generated from the MPU 15. These upper address signals (A15, A14) are supplied to AND circuits 16a to 16a.
16c. When the addresses of 0 to 3FFF are generated from the MPU 15, (A15, A
14) = (0,0), and the output of the AND circuit 16a is supplied to the common memory 11 as a chip select signal via the OR circuit 16e. Also, MPU 15 to 400
When addresses of 0 to 7FFF are generated, (A15, A15
14) = (0, 1), and the output of the AND circuit 16b is supplied to the common memory 11 as a chip select signal via the OR circuit 16e.

In the memory switching control circuit 16,
When the addresses of 8000 to BFFF are generated from the MPU 15, (A15, A14) = (1, 0), and AN
The output of the D circuit 16c is supplied to one input terminal of the AND circuits 16f to 16h. The other input terminals of the AND circuits 16f to 16h have bank selection output ports 16i for generating bank selection signals for selecting each bank memory.
Is supplied.

Here, when the bank 1 memory 12 is selected, the bank selection signal from the bank selection output port 16i is supplied to the AND circuit 16f, so that the AND operation is performed.
The output of the circuit 16f is used as a chip select signal in the bank 1
The data is supplied to the memory 12. When the bank 2 memory 13 is selected, the bank selection signal from the bank selection output port 16i is supplied to the AND circuit 16g, so that the output of the AND circuit 16g is output to the bank 2 memory 13 as a chip select signal. Supplied. In addition, Bank 3
When the memory 14 is selected, the bank selection signal from the bank selection output port 16i is supplied to the AND circuit 16h, so that the output of the AND circuit 16h is supplied to the bank 3 memory 14 as a chip select signal.

The common memory 11 uses 15 address signals (A14 to A0). The bank 1 memory 12, the bank 2 memory 13, and the bank 3 memory 14 are installed so that the highest address is fixed to L, and use the address space of the first half of the memory.

In the bank 1 memory 12, the bank 2 memory 13, and the bank 3 memory 14, 8000 to B
When the address of the FFF is selected, the upper address signal (A15, A14) is ANDed with the previously output bank select signal, so that the actual address 0 of the selected one, for example, the bank 1 memory 12 is used. 3FFF is
The MPU 15 operates as if it were 8000 to BFFF.

Next, the operation of the above configuration will be described. (1) The MPU 15 reads a program from the common memory 11. (2) When the program jumps from the common memory 11 to the bank 1 memory 12, the bank 2 memory 13, and the bank 3 memory 14, respectively, the information (D7 to D0) indicating which bank is to be selected by the MPU 15 before the program jumps. Output to the memory switching control circuit 16. (3) In the memory switching control circuit 16, the information (D7 to D7)
0) based on the bank selection signal output from the bank selection output port 16i and the upper address signal (A15,
A14), a chip select signal (CS) for the bank 1 memory 12, the bank 2 memory 13, and the bank 3 memory 14 is generated and supplied to each of the memory chips 11 to 14.

By the way, the method of increasing the memory capacity as described above may be disadvantageous in terms of component mounting and cost by using a plurality of memory chips in the same address space. In recent years, due to rapid technological progress, the price of memory is not proportional to the capacity, and even if the capacity increases, the price and size (component mounting area) slightly increase. In addition, since small-capacity memories tend to disappear due to technological progress, in the above-described method, only a part of the memories is used, and the utilization efficiency gradually decreases.

[0014]

As described above, in the conventional memory switching processing device, when increasing the memory capacity of a computer circuit having a limited address space, a plurality of memory chips are placed in the same address space. There is a problem in that it is disadvantageous in terms of component mounting and price due to use.

An object of the present invention is to provide a memory switching processing apparatus and method capable of increasing a memory capacity of a computer circuit having a limited address space without requiring a plurality of memory chips. .

[0016]

A memory switching processing device according to the present invention focuses on a device applied to a device having a predetermined address space, stores data, and stores an address generated from an address generation source. A part of a plurality of memories from which data can be read at least based on a first address corresponding to the space is arranged in the same address space in the address space, and a plurality of memories are selected according to the first address The present invention is directed to a memory switching processing device that switches memories so as to selectively read data from a plurality of memories by supplying selection signals to the memories.

A memory section is composed of a single memory chip, a plurality of memories are built in the memory chip, and a second address is assigned to each memory as a physical address in the memory chip. At least one of a selection signal and a portion of a first address generated from an address generation source to be provided to a memory is generated as a portion of a second address, and the portion of the second address is converted to a first address. And a memory switching control means for selectively switching a plurality of memories by giving a second address to the memory unit.

According to this configuration, it is noted that one memory chip incorporates a plurality of memories, and each memory is assigned a second address as a physical address in the memory chip. At least one of a selection signal for selecting a memory and a part of a first address generated from an address generation source is generated as a part of a second address, and is provided to the memory chip. In addition, a part of the second address is added to the first address generated from the address generation source to generate a second address, and based on the second address, data can be selectively output from a plurality of memories. Reading is performed.

As a result, by using one memory chip containing a plurality of memories and performing memory switching based on the second addresses corresponding to the plurality of memories in this memory chip, the same address space can be obtained. It is possible to increase the memory capacity of a computer circuit having a limited address space without allocating a plurality of memory chips.

The memory switching processing method according to the present invention, when used in an apparatus having a predetermined address space, stores data and stores the data in a first address corresponding to an address space generated from an address generation source. Selection for selecting a plurality of memories in accordance with a first address in a state where at least some of the plurality of memories from which data can be read based on the first address are arranged in the same address space in the address space The present invention is directed to a memory switching processing method in which a memory is switched so that signals are supplied to memories to selectively read data from a plurality of memories.

When one memory chip is provided, a plurality of memories are built in the memory chip, and each memory is provided with a memory section for assigning a second address as a physical address in the memory chip. A selection signal and a first signal to be supplied to a plurality of memories in the memory unit;
At least one of a part of the second address is generated as a part of the second address, and a part of the second address is generated at the second address in addition to the first address. By giving it, a plurality of memories are selectively switched.

According to this method, a plurality of memories are selected when one memory chip containing a plurality of memories and assigning a second address as a physical address in the memory chip to each memory is used. Signal and a first address generated from an address generation source are generated as a part of a second address and supplied to a memory chip, thereby selectively selecting from a plurality of memories. Data is read out.

Therefore, by using a single memory chip containing a plurality of memories and performing memory switching based on the second address corresponding to the plurality of memories in the memory chip, a limited address can be obtained. It is possible to increase the memory capacity of a computer circuit having space.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a block configuration in an embodiment of a memory switching processing device according to the present invention. Here, the present invention is applied to, for example, an 8-bit microcomputer circuit. This microcomputer circuit usually has 16 bits of an address signal, and therefore has an address space of 64 Kbytes.

In FIG. 1, reference numeral 21 denotes a memory that stores a program, data, and the like, and has a common memory area and a plurality of bank memory areas that can read out the program, data, and the like based on an address by a single memory chip. Department. Since the memory unit 21 requires a memory capacity of a total of 80 kbytes (common memory 32 k + bank memory 16 k × 3), for example, a 128 kbyte memory chip is used. And the memory unit 2
1 assigns a memory address, which is a physical address in the memory, to the common memory area and the plurality of bank memory areas, as shown in FIG. At this time, the memory unit 21 arranges the common memory area and the plurality of bank memory areas in order such that the common memory area is at the head of the memory address. The memory unit 21 is connected to the MPU 22 via a data bus and an address bus.

Here, the memory unit 21 has 17 (A17
To A0). Of these 17 addresses, 15 address signals (A14 to A14)
0) is directly supplied from the MPU 22 to the memory unit 21. Then, the remaining two address signals (A16, A1
5) is given by the memory switching control circuit 23. The memory switching control circuit 23 uses the bank selection signal and the upper address signal (A15, A14) of the MPU 22 to output the highest address signal (A16, A15) of the memory unit 21.
Is generated and given to the memory unit 21.

That is, when addresses 0 to 7FFF are selected, (A16, A15) = (0, 0), and when addresses 8000 to BFFF and bank 1 are selected, (A16, A15) = (0, 0). , 1), address 800
0 to BFFF and bank 2 are selected, (A1
6, A15) = (1, 0), address 8000 to BFF
F, when bank 3 is selected, (A16, A1
5) = (1, 1), the address signal A16,
By generating A15, the bank can be switched in one memory unit 21. It should be noted that the computer circuit supplies address signals of 0 to BFFF to the memory unit 21 so that an access signal does not collide when a signal other than the memory unit 21 is accessed.

FIG. 3 shows an example of the memory switching control circuit 23 in detail. 3, the memory switching control circuit 23 takes in two higher address signals (A15, A14) out of 16 address signals (A15 to A0) generated from the MPU 22. These upper address signals (A15, A14) are supplied to AND circuits 23a to 23a.
23c. When the addresses of 0 to 3FFF are generated from the MPU 22, (A15, A
14) = (0,0), and the output of the AND circuit 23a is supplied to the memory unit 21 as a chip select signal via the OR circuits 23d and 23e. When addresses of 4000 to 7FFF are generated from the MPU 22, (A1
5, A14) = (0, 1), and the output of the AND circuit 23b is supplied to the memory unit 21 as a chip select signal via the OR circuits 23d and 23e. In this case, the common memory area has been selected.

In the memory switching control circuit 23,
When an address of 8000 to BFFF is generated from the MPU 22, (A15, A14) = (1, 0), and AN
The output of the D circuit 23c is supplied to one input terminal of the AND circuits 23f to 23h. The other input terminals of the AND circuits 23f to 23h have a bank selection output port 2 for generating a bank selection signal for selecting each bank memory area.
3i is provided.

Here, the bank selection signal from the bank selection output port 23i is selectively supplied to the AND circuits 23f to 23h in the state where the addresses of 8000 to BFFF are generated, so that the AND circuits 23f to 23h Output from the upper address signal A via OR circuits 23j and 23k.
15 and A16 are supplied to the memory unit 21. The memory unit 21 selects the common memory area and the plurality of bank memory areas by detecting the presence or absence of the output of the OR circuits 23j and 23k.

In the memory switching control circuit 23, an address signal (A15 to A15) generated from the MPU 22 is used.
A0) is also supplied to a RAM (not shown) other than the memory unit 21, and the chip select signal (CS) supplied to the bank selection output port 23i will be described next. (1) The MPU 22 reads a program from the common memory area of the memory unit 21. (2) Before the program jumps from the common memory area to the bank memory area, the MPU 22 outputs information (D7 to D0) indicating which bank memory area to select to the memory switching control circuit 23 by software. (3) In the memory switching control circuit 23, the information (D7 to D7)
0) based on the bank select signal output from the bank select output port 23i and the upper address signal (A15,
A14) and the upper address signals (A16, A15) for the memory unit 21 are generated and supplied to the memory unit 21.

Therefore, according to the above embodiment, 1
The memory section 21 including a plurality of memory chips includes a common memory area and a plurality of bank memory areas, and focuses on a configuration in which memory addresses are assigned to respective memories. An upper memory address signal (A16, A15) is generated by using a bank selection signal for performing the operation and an upper address signal (A15, A14) generated from the MPU 22, and is provided to the memory unit 21. Then, in the memory unit 21, the higher memory address signals (A16, A15) are
A memory address is generated in addition to the address signal (A14 to A0) given from the memory 22, and data is selectively read from the common memory area and the plurality of bank memory areas based on the memory address.

For this reason, the memory section 21 which is a single memory chip having a built-in common memory area and a plurality of bank memory areas is used to correspond to the common memory area and the plurality of bank memory areas in the memory section 21. By performing memory switching based on addresses, it is possible to increase the memory capacity of a computer circuit having a limited address space without allocating a plurality of memory chips to the same address space.

Further, by switching between the common memory area and the plurality of bank memory areas in the memory section 21, it is advantageous in terms of component mounting and cost, and the utilization efficiency for the memory is improved.

In the above embodiment, a ROM is used for the memory unit 21. However, a RAM, an input / output port, or a circuit in which these are mixed are used for a plurality of bank memory areas of the memory unit 21. But it is possible. The memory unit 21 has three unused blocks every 16 kbytes.
By changing the configuration of No. 3, the 16-kbyte bank memory area can be changed to six blocks, and the size of the blocks of the common memory area and the blocks of the bank memory area can be changed.

The memory switching control circuit 23 generally switches the bank by software, but it is also possible to switch the bank by hardware. Further, in the memory unit 21, it is possible to consider that all memory blocks do not have a common memory area and are all bank memory areas. In other words, a method in which a specific bank memory area is always selected when the MPU 22 is reset to start the program, and thereafter, the bank memory area is switched according to the progress of the program. In this case, the transfer is not necessarily to the bank memory area of the same address space, but to a bank memory area of another address.

It should be noted that the present invention is not necessarily limited to the above-described embodiment, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0038]

As described in detail above, according to the present invention,
It is possible to provide a memory switching processing device and method capable of increasing a memory capacity for a computer circuit having a limited address space without requiring a plurality of memory chips.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a memory switching processing device and method according to the present invention.

FIG. 2 is a view for explaining address assignment to a common memory and a plurality of bank memories in the embodiment;

FIG. 3 is a circuit configuration diagram showing an example of a memory switching control circuit in the embodiment.

FIG. 4 is a block diagram showing a conventional memory switching processing device.

FIG. 5 is a view for explaining address assignment to a common memory and a plurality of bank memories in the conventional device.

FIG. 6 is a circuit diagram showing an example of a memory switching control circuit in the conventional device.

[Explanation of symbols]

 11: Common memory, 12: Bank 1 memory, 13: Bank 2 memory, 14: Bank 3 memory, 15, 22, MPU, 16, 23: Memory switching control circuit, 21: Memory unit.

Claims (6)

[Claims] 1. Applicable to an apparatus having a predetermined address space, wherein data is stored and at least the address is generated based on a first address corresponding to the address space generated from an address generation source. A plurality of memories from which data can be read, at least a part of the plurality of memories is arranged in the same address space in the address space, and the plurality of memories are stored in accordance with the first address. A memory switching processing device for switching between memories so as to selectively read data from the plurality of memories by applying a selection signal for selection to each of the memories, comprising: a memory chip; And a second address as a physical address in the memory chip. And a memory for allocating at least one of the selection signal and a part of the first address to a part of the second address to be provided to the plurality of memories in the memory. Memory switching control means for selectively switching the plurality of memories by giving a part of the address to the memory unit so as to generate the second address in addition to the first address. A memory switching processing device, comprising: 2. When the first address generated from the address generation source has a predetermined number of bits, the memory switching control means includes a part of upper bits of the first address, or Using a part of upper bits of the first address and information for selecting the plurality of memories, a part of upper bits of the second address is generated, and an upper bit of the second address is generated. Part of the first
2. The memory switching processing device according to claim 1, further comprising: means for adding the address to a plurality of bits forming the address to the memory unit. 3. The memory unit according to claim 1, wherein one of the plurality of memories is a common memory and the other is a plurality of bank memories, such that the common memory is at the head of the second address. 2. The memory switching processing device according to claim 1, wherein a common memory and the plurality of bank memories are sequentially arranged. 4. An apparatus having a predetermined address space, wherein a plurality of data can be stored and at least the data can be read out based on a first address corresponding to the address space generated from an address generation source. When a memory is used, at least a part of the plurality of memories is arranged in the same address space in the address space, and according to the first address,
A memory switching processing method for switching between memories so as to selectively read data from the plurality of memories by providing a selection signal for selecting the plurality of memories to each of the memories. In a case where the memory chip includes the plurality of memories and each of the memories includes a memory unit that allocates a second address as a physical address in the memory chip, the memory unit is provided with the plurality of memories. At least one of the selection signal and a part of the first address is generated as a part of the second address, and a part of the second address is added to the first address to generate the second address. By providing an address to the memory unit so as to generate an address, the plurality of memories are selectively switched. Memory switching processing method and butterflies. 5. When the first address has a predetermined number of bits, a part of upper bits of the first address or a part of upper bits of the first address and the plurality of memories And generating a part of upper bits of the second address using the information for selecting the first address and adding a part of upper bits of the second address to a plurality of bits forming the first address. 5. The memory switching processing method according to claim 4, wherein said memory switching processing is provided to said memory unit. 6. The memory unit according to claim 1, wherein when one of the plurality of memories is a common memory and the other is a plurality of bank memories, the common memory is located at the head of the second address. 5. The method according to claim 4, wherein a common memory and the plurality of bank memories are sequentially arranged.