JP2004334256A - Data processing system and controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide data processing system and a controller allowing sharing of a storage device with a different bit width by a CPU. <P>SOLUTION: This controller constituting the system creates a selection signal for selecting a predetermined storage device from a plurality of storage devices, and predetermined data stored in a storage device, to which the CPU makes access on the basis of the selection signal, are converted into a data format processible by the CPU. The CPU constituting the system is provided with a function for accessing the storage device matching the selection signal and transferring the predetermine data stored in the storage device to the controller and a function for reading the converted data to execute them. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data processing system in which a CPU can share storage devices having different bit widths, and more particularly to a data processing system for processing data stored in a storage device having a bit width smaller than the bit width of the CPU with the bit width of the CPU. It is about.
[0002]
[Prior art]
In recent years, in order to realize high-speed data processing in multimedia products appearing on the market, CPUs have been increased in number of bits in addition to higher frequencies. At present, the shift to multi-bit CPUs is at the stage when the transition from a 16-bit CPU to a 32-bit CPU has been almost completed, and it is considered that the transition to a 64-bit CPU and a 128-bit CPU will be successively made.
[0003]
In a system equipped with such a multi-bit CPU, a storage device capable of accessing and processing data by the CPU is naturally required. It is most desirable to use a storage device having the same bit width as that of the CPU for such a storage device. However, for example, a 32-bit memory is still more expensive than an 8-bit or 16-bit memory, and a system configured with such a memory is undesirably high in cost as a whole. Furthermore, 64-bit memories are not practical because they are few on the market and difficult to obtain.
Therefore, for example, for a 32-bit CPU, it is conceivable to arrange two 16-bit memories in parallel to make the total bit width 32 bits.
[0004]
[Patent Document 1] Japanese Patent Application Laid-Open No. 11-134246
[Problems to be solved by the invention]
However, in the above method, even when the required storage capacity is extremely small, it is necessary to provide two storage devices, and there is a problem that a useless memory area is formed. Such a problem is solved by the data processing system described in Patent Document 1. Specifically, when it is determined based on predetermined memory information that the CPU has a memory having the same bit width as its own bit width, the CPU selects a processing mode in which processing is performed with the bit width of the CPU. If it is determined that a memory having a bit width smaller than the bit width of the memory is mounted, a system capable of coping with memories having different bit widths is selected by selecting a processing mode in which processing is performed using the bit width of the memory. It is configured. However, in the data processing system described in Patent Literature 1, for a memory having a bit width smaller than that of a CPU, for example, the CPU processes data with the bit width of the memory. Can not be demonstrated. That is, in this case, there is a problem that the speed of data processing cannot be increased.
Further, in the above-mentioned conventional system, it is necessary to secure an area for storing predetermined memory information in advance only to detect the specification of the mounted memory.
Further, since the above-described conventional system switches the access method to the memory according to the judgment of the CPU, it cannot be applied to a storage area storing a boot program executed at the time of starting the system. was there.
[0006]
Therefore, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data processing system and a control device that allow a CPU to share storage devices having different bit widths.
[0007]
[Means for Solving the Problems]
SUMMARY OF THE INVENTION The present invention for solving the above-mentioned object has a plurality of storage devices having different bit widths, a CPU for accessing the storage device and executing predetermined processing, and a configuration in which the CPU can share the plurality of storage devices. In a data processing system including a control device for controlling, the control device is configured to generate a selection signal for selecting a predetermined storage device from the plurality of storage devices, and to generate a selection signal by the selection signal generation device. And data conversion means for converting predetermined data stored in the storage device accessed by the CPU into a data format that can be processed by the CPU based on the selection signal. The storage device corresponding to the generated selection signal is accessed, and the predetermined data stored in the storage device is transferred to the control device. And transfer means, and is configured as a data processing system characterized by comprising a data read processing means reading and executing the data converted by said data converting means.
Thus, even when a memory having the same bit width as that of the CPU is mounted or a memory having a smaller bit width than the CPU is mounted, the CPU stores data having the bit width of the CPU. It can be processed. Further, by directly reading out the selection signal generated by the control device, it is not necessary to provide a storage area for storing predetermined memory information which has been required conventionally, and as a result, the memory area can be used effectively. It became.
[0008]
In this case, it is conceivable that the selection signal generation means generates the selection signal according to predetermined switching means. As a result, for example, a storage device having a bit width smaller than the bit width of the CPU can be applied to a storage area in which an initialization program to be executed when the system is started is stored. Further, by providing a plurality of switching patterns of the switching means, it is possible to configure a system corresponding to a plurality of types of memories.
[0009]
It is also conceivable that the data conversion means converts the startup program data stored in the storage device accessed by the CPU based on the selection signal into a data format that can be processed by the CPU.
[0010]
Further, the above problem can be solved by the following control device.
That is, in a control device for controlling the CPU so that a plurality of storage devices having different bit widths can be shared, a selection signal generating means for generating a selection signal for selecting a predetermined storage device from the plurality of storage devices; Data conversion means for converting predetermined data stored in a storage device accessed by the CPU based on the selection signal generated by the generation means into a data format that can be processed by the CPU. The above problem can also be solved by a control device that performs the above.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings to facilitate understanding of the present invention. The following embodiments are examples embodying the present invention, and do not limit the technical scope of the present invention.
Here, FIG. 1 is a block diagram showing a schematic configuration of a data processing system according to the embodiment of the present invention, and FIG. 2 is a flowchart showing an example of a data processing procedure of the data processing device according to the embodiment of the present invention. .
[0012]
First, a schematic configuration of a data processing system according to an embodiment of the present invention will be described using the system block diagram of FIG.
This data processing system includes a 32-bit CPU (hereinafter abbreviated as “CPU”) 10, a control circuit 20 as an example of a control device, and a 16-bit memory 30 and a 32-bit memory 40 as an example of a storage device. The CPU 10, the control circuit 20, and the memory 30 are connected to each other by a data bus 50 (a bus having a bus width of 16 bits (0 to 15 bits)) so that data stored in the memory 30 can be transmitted. The data bus 50 and the data bus 51 (the bus width is 16 bits (16 to 31 bits)) so that the CPU 10, the control circuit 20, and the memory 40 can mutually transmit the data stored in the memory 40. ) To form a system.
[0013]
Here, each of the above-described units constituting the data processing system will be described in detail.
The control unit 20 includes at least a selection signal generation circuit 21 as an example of selection signal generation means, a data conversion circuit 22 as an example of data conversion means, a changeover switch 23 as an example of switching means, and a buffer area 24. It is configured. More specifically, as an example of the control circuit 20, for example, a circuit board on which electronic devices are arranged to configure the circuits, an ASIC (Application Specific Integrated Circuit) in which the circuits and the like are integrated into an IC, and the like are given. Can be
[0014]
The selection signal generation circuit 21 is a circuit that generates a selection signal for selecting a predetermined storage device from a plurality of storage devices. For example, one of the 16-bit memory 30 and the 32-bit memory 40 is selectively extracted. This is a circuit that generates a signal for performing the operation. Specifically, the selection signal generation method includes an ON / OFF signal generated by switching ON / OFF of a dip switch (an example of a changeover switch 23) provided in the control circuit 20, or a plurality of jumper pins (switches). There is a general method in which the control circuit 20 performs a logical operation on a short-circuit signal generated by switching the short-circuit position of the switch 23) to generate a predetermined bit string signal. The selection signal (bit string signal) generated in this case is preferably a signal that can be recognized by the CPU 10 described later. In this embodiment, since one memory is selected from the two memories of the memory 30 and the memory 40, the changeover switch 23 may be a 1-bit dip switch or the like. It is preferable to generate a signal recognizable by the CPU 10 by bit-converting a 1-bit ON / OFF signal or a short-circuit signal generated by the switching into a bit string signal having the same bit width (32 bits) of the CPU 10. Further, since the CPU 10 described later accesses the memory 30 or the memory 40 corresponding to the selection signal, the selection signal has a role of an address signal indicating a position of the memory 30 or the memory 40. In this case, the selection signal may be a jump code for jumping to an area of the address map where the address of the memory 30 or the address of the memory 40 is stored.
[0015]
As described above, the changeover switch 23 provided in the control circuit 20 is a changeover switch using hardware such as a dip switch and a jumper pin. Such switching is performed by the CPU automatically determining the specification (memory information) such as the bit width and capacity of the mounted memory from the mounting position of the memory and the like, so that the CPU accesses the memory in accordance with the above specification. Switching by software is also possible. However, this causes a problem when, for example, accessing a memory that stores an initialization program (boot program, IPL program) that is executed first when the system is started. That is, since the system has not been started, the CPU cannot switch the method of accessing the memory by the software described above, so that there is a problem that the CPU cannot execute the initialization program. Therefore, as described above, it is desirable that the changeover switch 23 be configured by hardware such as a dip switch and a jumper pin.
[0016]
As described above, in the present embodiment, two memories, the memory 30 and the memory 40, are mentioned, but it is not particularly limited to these. For example, there is no problem even if the selection signal generation circuit 21 is a circuit that generates a signal for selecting one memory from three or more memories.
[0017]
The data conversion circuit 22 is a circuit that converts predetermined data stored in a storage device accessed by the CPU into a data format that can be processed by the CPU based on the selection signal generated by the selection signal generation circuit 21. is there.
The CPU 10 accesses the memory located at the address indicated by the selection signal. However, when accessing the memory 30 (16 bits) having a width smaller than the bit width (32 bits) of the CPU 10, the CPU bit width and the access Therefore, the data stored in the memory 30 cannot be directly handled because the bit width of the memory to be used is different. Therefore, in this case, the data conversion circuit 22 converts the data stored in the memory 30 into 32-bit data. Specifically, the data conversion circuit 22 sends the 16-bit data, which has been transmitted to the buffer area 24 of the control device 20 via the data bus 50 by the data transfer function 11 of the CPU 10 described later, to the data bus 51. Execute Further, the 16-bit data transmitted through the data bus 50 by the data transfer function 11 is not returned to the data bus 51 but transmitted to the transmitted data bus 50. By performing such processing, it becomes possible to convert two 16-bit data obtained by reading twice into one 32-bit data. When the 32-bit CPU 10 processes the data stored in the 8-bit memory, it can be converted into 32-bit data by adding four 8-bit data obtained by reading the data four times. In the case of processing data stored in a 4-bit memory, it is possible to cope with this by converting eight 4-bit data obtained by reading eight times into 32-bit data.
[0018]
The CPU 10 is a central device in configuring the present data processing system, and exhibits a data transfer function 11 as an example of data transfer means and a data read function 12 as an example of data read processing means. is there.
Here, the data transfer function 11 accesses a storage device corresponding to the selection signal generated by the selection signal generation circuit 21 and transmits predetermined data stored in the storage device to the control circuit 20. The transfer function is, for example, a transfer function to the buffer area 24 of the control circuit 20. As described above, when accessing the memory 30 having a width smaller than the bit width of the CPU 10, the data stored in the memory 30 cannot be directly processed. Therefore, the data read from the memory 30 is transferred to the buffer area 24 in order to convert the data read by the CPU 10 into 32-bit data. In this case, at the time of transfer, it is preferable that a predetermined bit is made valid to indicate whether the read data is data to be sent to the data bus 51 or not.
The data reading function 12 is a function of directly reading data in, for example, a 32-bit memory, and is a function of reading data converted from 16 bits to 32 bits by the data conversion circuit 22.
[0019]
Next, an example of a data processing procedure of the data processing device according to the embodiment of the present invention will be described with reference to the flowchart of FIG. S10, S20... In the figure indicate processing procedure (step) numbers. The processing is started from step S10.
[0020]
When the system is started, the CPU 10 first needs to access a memory storing the initialization program in order to execute the initialization program. Therefore, the CPU executes a process of accessing the control circuit 20 to read a selection signal for selecting a memory to be accessed (S10). This processing is realized by, for example, designing the system so that the program counter is set to the address of the control circuit 20 when the system is started.
[0021]
Subsequently, the CPU 10 executes a process of reading out the selection signal generated by the control circuit 20 (S20). This processing is performed by detecting the ON / OFF state of the changeover switch 23. Here, in step S30, when it is determined that the changeover switch 23 is OFF, that is, when the selection signal (signal for selecting the 32-bit memory) generated when the changeover switch 23 is OFF is read, the CPU 10 The 32-bit memory 40 is accessed (S40), the initialization program stored in the memory 40 is read, and the system startup processing is executed (S41 → S60). If it is determined in step S30 that the changeover switch 23 is ON, that is, if a selection signal (a signal for selecting a 16-bit memory) generated when the changeover switch 23 is ON is read, the CPU 10 30 is accessed (S50). Thereafter, the CPU transfers the 16-bit data read from the memory 30 to the buffer area 24 of the control device 20 (S51). The 16-bit data transferred to the buffer area 24 is converted into 32-bit data by a data conversion circuit provided in the control device 20. Thereafter, the CPU reads out the 32-bit data converted by the control device 20 (S52) and executes the read-out data to execute a system activation process (S60).
[0022]
【The invention's effect】
As described above, according to the present invention, the selection signal generation means for generating a selection signal for selecting a predetermined storage device from a plurality of storage devices, and the CPU based on the selection signal generated by the selection signal generation device. A control device having data conversion means for converting predetermined data stored in a storage device accessed by the CPU into a data format that can be processed by the CPU, and a storage device corresponding to the selection signal generated by the selection signal generation means A data transfer unit that accesses the control unit and transfers the predetermined data stored in the storage device to the control device; and a data read processing unit that reads and executes the data converted by the data conversion unit. Since the system configuration is made by the CPU, even if a memory having the same bit width as the CPU is installed, Even if the memory of PU smaller bit width is mounted, the CPU can process the data bit width of said CPU. Further, by directly reading out the selection signal generated by the control device, it is not necessary to provide a storage area for storing predetermined memory information, which has been required conventionally, and as a result, the memory area can be used effectively. It becomes.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a data processing system according to an embodiment of the present invention.
FIG. 2 is a flowchart showing an example of a data processing procedure of the data processing device according to the embodiment of the present invention.
[Explanation of symbols]
10 ... 32 bit CPU
11 Data transfer function 12 Data read function 20 Control circuit 21 Selection signal generation circuit 22 Data conversion circuit 23 Changeover switch 24 Buffer area 30 16-bit memory 40 32-bit memory 50 Data bus (0 to 0) 15 bits)
51: Data bus (16 to 31 bits)

Claims (4)

A plurality of storage devices having different bit widths;
A CPU that accesses the storage device and executes a predetermined process;
A control device for controlling the CPU to share the plurality of storage devices;
In a data processing system comprising
The control device is
Selection signal generation means for generating a selection signal for selecting a predetermined storage device from the plurality of storage devices;
Data conversion means for converting predetermined data stored in a storage device accessed by the CPU into a data format that can be processed by the CPU, based on the selection signal generated by the selection signal generation means;
The CPU is
Data transfer means for accessing a storage device corresponding to the selection signal generated by the selection signal generation means and transferring the predetermined data stored in the storage device to the control device;
Data read processing means for reading and executing the data converted by the data conversion means;
A data processing system comprising: 2. The data processing system according to claim 1, wherein said selection signal generation means generates said selection signal according to predetermined switching means. 3. The data according to claim 1, wherein said data conversion means converts start program data stored in a storage device accessed by said CPU based on said selection signal into a data format that can be processed by said CPU. Processing system. In a control device for controlling a CPU to share a plurality of storage devices having different bit widths,
Selection signal generation means for generating a selection signal for selecting a predetermined storage device from the plurality of storage devices;
Data conversion means for converting predetermined data stored in a storage device accessed by the CPU into a data format that can be processed by the CPU, based on the selection signal generated by the selection signal generation means;
A control device characterized by comprising:

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