JP3820707B2 - Interrupt vector address generator and microcomputer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an interrupt vector address generation device that generates a predetermined interrupt vector address in response to an interrupt process by a CPU, and a microcomputer including the interrupt vector address generation device.
[0002]
[Prior art]
If a problem occurs when a microcomputer (hereinafter referred to as a microcomputer) is mounted on an electronic board, the microcomputer is removed from the electronic board and analyzed by itself, or serial communication built into the microcomputer is performed. The analysis program is transferred to the RAM by using it, and is executed by the analysis program on the RAM so as to identify the defective portion.
[0003]
[Problems to be solved by the invention]
However, when analyzing with a microcomputer alone, if the system becomes complicated, it becomes difficult to reproduce the problem, and the analysis takes a long time. In addition, when a failure location is specified by the analysis program on the RAM, the analysis can be performed along the system, but since it is executed by the limited analysis program on the RAM, it is already mounted on the ROM. In order to make it independent of the existing user program, analysis must be performed except for interrupt processing. In other words, if an interrupt factor occurs during the execution of the analysis program, the microcomputer CPU branches to the interrupt processing routine by accessing the interrupt vector address of the user program on the ROM, and the analysis program on the RAM Since it is impossible to continue the analysis away from the problem, there is a disadvantage that the failure analysis cannot be performed in consideration of the interruption.
[0004]
The present invention has been made in view of the above circumstances, and an object thereof is to provide an interrupt vector generation device and a microcomputer capable of performing a failure analysis taking into account an interrupt when performing a failure analysis according to an analysis program. It is in.
[0005]
[Means for Solving the Problems]
According to the first aspect of the present invention, the CPU accesses a predetermined interrupt vector address set in the user program storage address space when executing the interrupt process according to the interrupt factor. At this time, the interrupt vector detection circuit outputs an interrupt detection command because the address from the CPU is a predetermined interrupt vector address.
[0006]
Here, since the interrupt vector address conversion circuit normally enables the CPU to access the interrupt vector address, the interrupt vector set in the user program storage address space as described above. When accessing the address, the CPU shifts to the user program.
[0007]
When the CPU executes interrupt processing on the analysis program instead of the user program, an interrupt vector address generation switching command is given to the interrupt vector address conversion circuit. Then, the interrupt vector address conversion circuit, when the interrupt vector generation circuit receives the interrupt detection command from the interrupt vector generation switching command, gives a predetermined higher order of the interrupt vector address from the CPU. By inverting the bit pattern of the address, it is set in the analysis program storage address space and converted into a predetermined interrupt vector address.
[0008]
As a result, the CPU accesses a predetermined interrupt vector address set in the analysis program storage address space, so that the interrupt processing can be shifted from the user program to the analysis program.
[0009]
In this case , since the interrupt vector address conversion circuit only needs to have a function of inverting the bit pattern, the circuit configuration can be simplified.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment in which the present invention is applied to a single chip microcomputer will be described with reference to the drawings.
FIG. 1 schematically shows a configuration related to the present invention among the configurations of a one-chip microcomputer. In FIG. 1, a microcomputer 1 is mainly composed of a 16-bit CPU 2. Data terminals D15 to D0 and address terminals A11 to A0 are connected to a RAM 3 and a ROM 4 via an internal data bus (address bus and data bus). The peripheral circuit 5 and the serial communication circuit 6 are connected.
[0011]
The serial communication circuit 6 has a serial transmission terminal 6a and a serial reception terminal 6b, and an analysis program can be transferred onto the RAM 3 through these terminals 6a and 6b.
[0012]
The address terminals A15 to A0 of the CPU 2 are connected to the vector address generation circuit 7. The vector address generation circuit 7 generates a predetermined vector address based on the vector address from the CPU 2 and outputs it to the address bus.
[0013]
In other words, in the vector address generation circuit 7, the address terminals A15 to A0 of the CPU 2 are connected to the interrupt vector ROM area decoder circuit 8 as an interrupt vector detection circuit . The interrupt vector ROM area decoder circuit 8 issues a high-level interrupt detection command to one of the NAND circuits 9 when the address terminals A15 to A10 are [FF00] h, "FF02] h, and [FF04] h. Output to the input terminal.
[0014]
The other input terminal of the NAND circuit 9 is connected to an external terminal, and an interrupt vector generation switching signal is given through this external terminal.
One input terminal of each of the four AND circuits 10 is connected to the address terminals A15 to A12 of the CPU 2, and the other input terminal is connected to the output terminal of the NAND circuit 9. The output terminal of the AND circuit 10 is connected to each circuit via an address bus. In this embodiment, the NAND vector 9 and the AND circuit 10 constitute an interrupt vector address conversion circuit.
[0015]
FIG. 2 shows an address space accessible by the CPU 2. In FIG. 2, addresses [0000] h to [07FF] h are set in the IO area, addresses [0800] h to [3FFF] h are set in the RAM area, and [4000] h to [FFFF] address h is set in the ROM area.
[0016]
The ROM 4 stores a user program, and [FF00] h address in the user program is set as a start vector during normal operation, and [FF02] h address is set as a timer interrupt vector during normal operation. FF04] address h is set as an NMI (Non Maskable Interrupt) interrupt vector during normal operation.
[0017]
The RAM 3 stores working data as the user program is executed by the CPU 2. In the RAM 3, an analysis program is stored by communication during operation analysis, and [0F00] h address in the analysis program is set as a start vector during analysis operation, and [0F02] h address is analyzed. The timer interrupt vector during operation is set, and [0F04] h address is set as the NMI interrupt vector during analysis operation.
[0018]
Here, the start vector is a vector that is set first after reset release, and executes a process of jumping to the start address of the program. The timer interrupt vector is a vector generated when the count value of the timer overflows, for example. When the timer overflows, the operation content is determined depending on what processing is necessary in the system next. An NMI interrupt is a vector that is generated when a signal is input from the NMI terminal of the CPU 2, and is an interrupt with a very high priority because the interrupt mask is invalidated. Is to be done.
The vector mentioned above is an address to which the interrupt program jumps, and the CPU 2 jumps to the address indicated by the vector.
[0019]
Next, the operation of the above configuration will be described.
When analyzing the malfunction operation of the CPU 2, the analysis program is transferred to the RAM 3 through the serial communication circuit 6 and stored, and then the analysis program is operated.
[0020]
When an interrupt is requested from the peripheral circuit 5 or the serial communication circuit 6 during the execution of the analysis program, the CPU 2 generates an interrupt vector corresponding to the interrupt factor.
[0021]
That is, the CPU 2 has a start vector, a timer interrupt vector, and an NMI interrupt vector set as interrupt vectors. When generating a start vector, [FF00] h is output as an address to generate a timer interrupt vector. [FF02] h is output as an address when generating, and [FF04] h is output as an address when generating an NMI interrupt vector.
[0022]
Here, the operation when the CPU 2 executes the timer interrupt process will be described. When the timer count factor overflows and the timer interrupt factor signal is input, the CPU 2 outputs [FF02] h as an address (see FIG. 3).
Then, the interrupt vector ROM area decoder circuit 8 outputs a high-level interrupt detection command to the NAND circuit 9 when the address becomes [FF02] h.
[0023]
At this time, although one input terminal of the NAND circuit 9 is at a high level, the interrupt vector generation switching signal input to the other input terminal remains at a low level. Is output. Therefore, when [FF02] h is output from the CPU 2 as an address, the input terminals of all the AND circuits 10 are at a high level, so that a high level signal is output from the AND circuit 10.
[0024]
In short, when [FF02] h is output as an address from the CPU 2, [FF02] h is output to the address bus regardless of the presence of the vector address generation circuit 7.
[0025]
With the above operation, the CPU 2 shifts to the timer interrupt process based on the normal operation timer interrupt vector stored in the [FF02] h address in the ROM area. As a result, the process proceeds to the next process when the timer overflows.
[0026]
By the way, as described above, when an interrupt factor occurs during the execution of the analysis program, the routine shifts to a normal interrupt process, and the analysis operation becomes impossible.
[0027]
Therefore, in this embodiment, when an interrupt factor is generated as follows, the CPU 2 executes an interrupt process for analysis.
That is, when it is desired to execute the interrupt processing for analysis, the interrupt vector generation switching signal given to the external terminal connected to the NAND circuit 9 is switched to the high level (see FIG. 4).
[0028]
Then, since the signal level of the output terminal of the NAND circuit 9 becomes a low level, even if [FF02] h is output as an address from the CPU 2 due to the timer overflow as described above, the output of the AND circuit 10 is Become low level.
[0029]
With the above operation, since the low level is output from the vector address generation circuit 7 as the addresses A15 to A12, the address is converted to [0F02] h.
[0030]
Here, as shown in FIG. 2, address [0F02] h in the address space is a RAM area, and is set as a timer interrupt vector at the time of analysis operation in the analysis program, so the CPU 2 interrupts at the time of analysis operation. By moving to the address set by the vector, processing for timer operation analysis is executed.
[0031]
Similarly, when executing a start interrupt or NMI interrupt process due to the generation of an interrupt factor, the CPU 2 performs an interrupt for normal operation and an interrupt for analysis based on the signal level of the interrupt vector generation switching signal. Can be selectively executed.
[0032]
According to the above configuration, when the interrupt address is output from the CPU 2, the vector address generation circuit 7 performs interrupt processing or analysis in the user program according to the signal level of the interrupt vector generation switching signal. Since the interrupt process in the program is selectively executed, the interrupt process by the CPU 2 can be arbitrarily switched. Therefore, when the CPU executes the interrupt process according to the interrupt factor, unlike the configuration in which only the interrupt process at the normal operation can be executed, the analysis according to the interrupt process can be performed, and the operation analysis of the CPU 2 can be performed. Accuracy can be increased.
[0033]
Since the vector address generation circuit 7 is composed of simple digital circuits such as the interrupt vector ROM area decoder circuit 8, the NAND circuit 9, and the AND circuit 10, the circuit configuration can be simplified.
[0034]
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
Instead of providing an external terminal for interrupt vector ROM generation switching signal input, a vector generation switching control register is provided in the microcomputer, and a level signal is sent to the vector address generation circuit 7 by writing data (1 or 0) from the CPU 2. You may comprise so that.
As the address space, the RAM area may be set to a higher address than the ROM area.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing an overall configuration of an embodiment of the present invention. FIG. 2 is a schematic diagram showing an address space of a CPU. FIG. 3 is a signal waveform diagram when an interrupt vector generation switching signal is at a low level. 4] Signal waveform diagram when interrupt vector generation switching signal is high level [Explanation of symbols]
1 is a single chip computer, 2 is a CPU, 3 is a RAM, 4 is a ROM, 5 is a peripheral circuit, 6 is a serial communication circuit, 7 is a vector address generation circuit, 8 is an interrupt vector ROM area decoder circuit (interrupt vector detection) Circuit), 9 is a NAND circuit (interrupt vector address conversion circuit), and 10 is an AND circuit (interrupt vector address conversion circuit).

Claims (2)

An interrupt vector detection circuit that outputs an interrupt detection command when the address accessed by the CPU is a predetermined interrupt vector address set in the user program storage address space;
Normally, when the CPU enables access to an interrupt vector address, and an interrupt detection command is given from the interrupt vector detection circuit while an interrupt vector generation switching command is given from the outside Comprises an interrupt vector address conversion circuit that converts a predetermined high-order bit pattern of an interrupt vector address from the CPU into a predetermined interrupt vector address set in an analysis program storage address space. An interrupt vector address generator characterized by the above. A microcomputer comprising the interrupt vector address generation device according to claim 1.

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