DE10017934A1 - Method for handling interrupts for a computer system with a CPU and a system bus in which a multiplexor is used to redirect address to an interrupt base address register to optimize system speed for soft or hard boot-ups - Google Patents

Abstract

A system address (4) is sent from the processor (1)to a comparator (10), that controls a multiplexor (5) via its control input (13). The multiplexor now sends the system address directly, or an address that is stored in an interrupt base address register (8), to the system bus. Changing addresses stored in the interrupt base address register allows a chosen memory range to be inserted into the memory range addressed by the processor. An independent claim is made for a method for operating a processor circuit in which an address from the processor in sent to the input of a multiplexor and a second address is transferred from the multiplexor output to the system bus. The second address is the start address for an interrupt handling routine.

Description

The present invention relates to a circuit arrangement with a processor and a system bus interface for ver reduction of the processing time of an interrupt and reprogramming Interruptibility of an interrupt vector.

Data processing equipment is used to process Data, as well as for the control, regulation and analysis of A gear and output signals used. During operation a data processing device, which is usually a Has processor and a system bus, so-called In terrupts on. These are signals that the Pro processor and a CPU (central processing unit) an event Show. The events are, for example to states, results, or events that are both within as well as be generated outside of the CPU and execution a special routine in response to the event other. The special routine is the In terrroutine, whose start address as a so-called interrupt Vector ge at a predetermined memory cell of the memory stores. In addition, so-called interrupt handlers used, which are short program sequences delt, which are executed after an interrupt is triggered, at z. B. to determine the source of the interrupt.

Since interrupt vectors also during cold start or warm starts of a data processing device must be valid sen, they are in a non-volatile memory such. B. a ROM (read only memory). However, a ROM has the disadvantage that the access time to it is very long, what leads to significant interrupt latency.  

One solution is to store a jump instruction in the ROM to a fixed address in RAM (random access memory), so that another jump instruction in the RAM be programmed to the actual interrupt routine can. The disadvantage of this approach lies in the fact that at least one actually unnecessary jump instruction is issued must be led. Another problem that arises in that some operating systems of the software by prepro programmed routines reprogramming the interrupt Force vectors.

A second known solution is from "ARM Training Ma material: Technical Training 1999, Chapter 16, Chapter 19 "be knows and provides that so-called base address register are the start address of the ROM and the start address se of the RAM included, so that by reprogramming the respective address areas shifted or ver can be exchanged. This approach requires one additional complex address coding mechanism in the Memory modules for RAM and ROM. With complex modules with Numerous memory expansions can be added Complexity comes in that the address coding is no longer can take place within a clock period. this leads to an unwanted limitation of the maximum clock frequency. Wei furthermore, this procedure is problematic if an additional one Cache memory is provided as by reprogramming of the start addresses of memory areas with an inconsistency the data stored in the cache can arise.

It is the object of the invention, a circuit and a ver drive to their farm to indicate the shorter machining time of an interrupt and the reprogrammability of a Interrupt vector enables.

According to the invention the object is achieved by a circuit arrangement with:

• - a processor and  
• - solved a system bus interface,
• - The processor having an address line with a first Input of a multiplexer is connected, and an output of the multiplexer connected to the system bus interface is.

The multiplexer according to the invention is used by the Pro to select address lines leading to the system bus. The multiplexer can either be the one generated by the processor Address or by its multiplex function another address pass it on to the system bus. With this arrangement it is possible that the processor was originally in the processor specified address accesses, but this by the multiplexer is converted into another address at which the bear interrupt routine is stored.

Another embodiment of the arrangement according to the invention provides that the output of an interrupt vector Base address register with a second input of the multiple xers is connected. The interrupt vector base address register is used, for example, to save the address, where the interrupt routine is actually located. Usual For this purpose, an address arranged in the RAM is selected chosen. At the output of the interrupt vector Base address register is then the address that the Multi plexer is fed at its second input, and given if necessary, is passed on to the address bus.

Another embodiment of the invention provides that Interrupt vector base address register outside the processor is arranged. This arrangement is also suitable for Pro cessors without integrated interrupt vector Base address register with the functionality of an interrupt Vector base address register. This is special advantageous, since inexpensive processors with this Functionality can be retrofitted. The interrupt  Vector base address register can be, for example, in a Integrate chipset.

It is also provided that a comparator input of a Comparator is connected to the address line and a Kompa rator output of the comparator with a control input of the Mul tiplexers is connected. The comparator has the task be, the address transmitted by the processor to the system bus check so as to access the interrupt vector or the interrupt handler area of the memory and to control the multiplexer accordingly.

With regard to the method, the task is solved by a method for operating a circuit with the following steps:

• - Provision of a processor and a system bus Interfaces;
• - Transferring a first address from the processor an address line to a first input of a multiple xers;
• - Transfer a second address from an output of the Mul tiplexers to the system bus interface.

The advantage of the method according to the invention is that the address is not directly from the processor to the system bus Interface is transmitted, but a multiplexer in between is switched between the one transferred by the processor gen address and another address.

Another process step of the inventive method rens provides that a third address from an exit interrupt vector base address register to a second Input of the multiplexer is transmitted. The interrupt In this case, vector base address register is used to create a To store the address instead of the one sent by the processor th address is transferred to the system bus. To select between the address sent by the processor and that in the  Interrupt vector base address register stored address the multiplexer is used.

Another embodiment of the method according to the invention provides that the first address to a comparator input a comparator is transmitted. The comparator has that Task to analyze the first address sent by the processor and a memory access to the interrupt vector Detect area.

The method according to the invention also provides the step of that the comparator has the first address with a reference address se compares and a comparator output signal on a Kom generated parator output that to a control input of the Multi plexers is transmitted. The comparison with the reference address This is used to access the interrupt vector area of memory. The comparator now also controls its output signal the multiplexer, which accordingly between the address transmitted by the processor and by the Interrupt vector base address register transferred address dials, and this selected address to the system bus Interface transmits. By controlling the multiplexer it is ensured that either that of the processor or the one originating from the interrupt vector base address register Address is passed on to the system bus interface.

Further refinements of the invention are in the corresponding corresponding dependent claims.

Exemplary embodiments of the invention are described below of the drawings shown and explained.

The figures show:

Figure 1 shows an inventive circuit arrangement with a processor and system bus interface.

Figure 2 is a memory having a first and a second memory area.

FIG. 3a shows a memory having an interrupt vector storage area;

FIG. 3b shows a further memory with an interrupt vector storage area;

Fig. 4 is a memory that is disposed in the first and second interrupt vector memory area associated with a first and a second CPU.

In Fig. 1, a circuit arrangement according to the invention is provided, which comprises a processor 1 and a system bus interface 2 , wherein the system bus interface 2 is connected to a system bus 3 . Furthermore, the processor 1 is connected to the system bus interface 2 by control lines 15 , which, for. B. Control lines such as a data read and a data write signal. Furthermore, a reset control 14 is arranged, which is connected to the processor 1 . An address line 4 connects the processor 1 to a first input 6 of a multiplexer 5 . The second input 9 of the Mul tiplexers 5 is connected to an interrupt vector base address register 8 . The multiplexer 5 has an output 7 which is connected to the system bus interface 2 . In addition, a comparator 10 is connected to the address line 4 via a comparator input 11, a comparator output 12 being connected to a control input 13 of the multiplexer 5 .

Conventionally, the multiplexer 5 and the comparator 10 are not connected between the processor 1 and the system bus interface 2 . In this case, the address generated by the processor is transferred directly to the system bus interface 2 .

For the present invention, the multiplexer 5 and the comparator 10 is an extremely simple and fast address decoder which decodes the upper part of the address transmitted by the processor.

The decoding function is taken by the comparator 10 , which is connected to the address line 4 . Is z. B. the entire upper address part is identical to zero, this is a sign that the processor is accessing the interrupt vector area of the memory. In this case, the multiplexer is switched so that the upper address bits of the processor are replaced by predetermined address bits which are stored in the interrupt vector base address register 8 . For all other addresses, the comparator 10 supplies an output signal to the comparator output 12 which controls the control input 13 of the multiplexer 5 so that the address generated by the processor 1 via the multiplexer 5 and the output 7 of the multiplexer 5 to the system bus -Interface 2 is transferred. The number of address bits evaluated in the comparator 10 is variable.

When the data processing device is cold started, the processor accesses a start routine, the address of which is stored in a ROM memory. For this purpose, the corresponding address is located in the interrupt vector base address register 8 during the cold start. In the case of a warm start, the interrupt vector base address register 8 does not necessarily have to be reset, so that another start code can also be executed. During the runtime of the Datenververarbeitungein direction, the address stored in the interrupt vector base address register is changed so that another area of the memory can be used to store the interrupt vectors and interrupt handlers.

FIG. 2 shows an example of a memory 16 for a data processing device. The memory 16 has a first memory area 17 , which in this embodiment is designed as RAM, and a second memory area 18 , which is designed as a ROM. In the second memory area 18 there is an interrupt vector ROM memory area 19 which begins, for example, from the address Oxff00_0000. The RAM ends at this memory location and starts at memory address 0x0000_0000. When the system starts, it is stored in the processor that the interrupt vectors are stored in the ROM of the second memory area 18 . The interrupt vector base address register 8 is programmed at a restart or a reset signal to a corresponding address value, which points to the beginning of the interrupt vector ROM memory area 19 .

During the runtime of the data processing device the interrupt vector base address register is reprogrammed so that it points to a different memory address.

With reference to Fig. 3a, 3b, the change of the interrupt vector base address register 8 and the associated Verle is described supply of the interrupt vector memory area. With reference to Fig. 3a is first rich created a copy of the interrupt vector ROM storage area 19 at the address 0x0000_0000 17 in the first Speicherbe. The content of the interrupt vector base address register 8 is then changed to the new address 0x0000_0000. As a result, the interrupt routines and interrupt handlers stored in the interrupt vector RAM memory area 20 are called from the next interrupt call. In addition, it is now possible to change the interrupt vectors and routines stored in the interrupt vector RAM memory area 20 so as to change the functionality of an interrupt process.

With reference to FIG. 3b, it is also possible to relocate the interrupt vector RAM memory area 20 to a memory address other than 0x0000_0000.

With this arrangement, it is possible to perform quickly interrupt calls, since these are now in the RAM are running. In addition, it is possible to use the Processing of an interrupt called routine to modifi and adhere to the conditions of data processing to adjust direction.

An exemplary embodiment of a multiprocessor system is explained with reference to FIG. 4. The multiprocessor system is designed to work on a memory 16 . The memory 16 has a first memory area 17 , which is designed as RAM, and a second memory area 18 , which is formed as ROM. An interrupt vector ROM memory area 19 is arranged in the second memory area 18 . Both the first processor CPU1 and the second processor CPU2 work with the first memory area 17 and the second memory area 18 and both first use the interrupt vector ROM memory area 19 . The inventive arrangement of a multiplexer 5 and a comparator 10 and an interrupt vector base address register 8 for each of the processors CPU1, CPU2 enables a first interrupt vector RAM area 21 for the first processor CPU1 and a second separate interrupt vector RAM area 22 for the second processor CPU2 in the first memory area 17 . This arrangement makes it possible to assign each of the two processors their own interrupt vector table and interrupt vector handler, which is independent of other processors. This arrangement is not limited to two processors, but can be carried out for any number of processors.

Reference list

1

processor

2

System bus interface

3rd

System bus

4

Address line

5

multiplexer

6

First entrance

7

output

8th

Interrupt vector base address register

9

Second entrance

10th

Comparator

11

Comparator input

12th

Comparator output

13

Control input

14

Reset control

15

Control lines

16

Storage

17th

First storage area

18th

Second storage area

19th

Interrupt vector ROM memory area

20th

Interrupt vector RAM memory area

21

First interrupt vector RAM area

22

Second interrupt vector RAM area
CPU 1 First processor
CPU 2 Second processor

Claims (9)

1. Circuit arrangement with:

• - a processor ( 1 );
• - a system bus interface ( 2 );

characterized in that the processor ( 1 ) is connected to an address line ( 4 ) with a first input ( 6 ) of a multiplexer ( 5 ) and an output ( 7 ) of the multiplexer ( 5 ) with the system bus interface ( 2nd ) connected is. 2. Arrangement according to claim 1, characterized in that the output of an interrupt vector base address register ( 8 ) is connected to a second input ( 9 ) of the multiplexer ( 5 ). 3. Arrangement according to one of claims 1 or 2, characterized in that the interrupt vector base address register ( 8 ) is arranged outside the processor ( 1 ). 4. Arrangement according to one of claims 1 to 3, characterized in that a comparator input ( 11 ) of a comparator ( 10 ) is connected to the address line ( 4 ) and a comparator output ( 12 ) of the comparator ( 10 ) with a control input ( 13 ) the multi plexer ( 5 ) is connected. 5. Method for operating a circuit with the steps:

• - Providing a processor ( 1 ) and a system bus interface ( 2 );
• - Transferring a first address from the processor ( 1 ) by means of an address line ( 4 ) to a first input ( 6 ) of a multiplexer ( 5 );
• - Transfer a second address from an output ( 7 ) of the multiplexer ( 5 ) to the system bus interface ( 2 ).

6. The method according to claim 5, characterized in that a third address is transmitted from an output of an interrupt vector base address register ( 8 ) to a second input ( 9 ) of the multiplexer ( 5 ). 7. The method according to any one of claims 5 or 6, characterized in that the first address is transmitted to a comparator input ( 11 ) of a comparator ( 10 ). 8. The method according to any one of claims 5 to 7, characterized in that the comparator compares the first address with a reference address and generates a comparator output signal at a comparator gate output ( 12 ) which is transmitted to a control input ( 13 ) of the multiplexer ( 5 ) . 9. The method according to any one of claims 5 to 8, characterized in that the multiplexer ( 5 ) at its control input ( 13 ) is controlled so that the second address transmitted by the output ( 7 ) of the multiplexer ( 5 ) either the first Address or the third address is.