JPH0997176A - Interrupt handling device for microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To immediately cope with even the occurrence of an interrupt request of urgency by accessing a second nonvolatile memory by a control circuit even in the case that some interrupt request occurs during data write to a first non- volatile memory. SOLUTION: An interrupt vector generation circuit 21 accepts the set output of an RS flip flop to fix the most significant bit of a program counter 3 to '1'. Consequently, address data corresponding to a prescribed interrupt request is set to the counter 3 by the vector generation circuit 21 but its most significant bit is fixed to '1' as it is when this interrupt request occurs during data write to an EEPROM (first non-volatile memory) 1. Thus, a mask ROM (second nonvolatile memory) 2 is accessed instead of the EEPROM 1, and interrupt handling is performed in parallel with data write to the EEPROM 1.

Description

Detailed Description of the Invention

[0001]

The present invention uses a predetermined storage area of a non-volatile memory such as an EEPROM capable of writing and reading data as a program data storage area for controlling the operation of a one-chip microcomputer.
The present invention relates to an interrupt processing device of a microcomputer.

[0002]

2. Description of the Related Art Generally, as a program memory for storing program data for controlling the operation of the one-chip microcomputer, which is built in the one-chip microcomputer, a read-only mask ROM, and writing and reading are possible. There are EPROM and EEPROM.

The latter non-volatile memory has an advantage that part of the data can be rewritten as compared with the former mask ROM. Specifically, the storage area of the non-volatile memory can be rewritten in units of a plurality of bytes (one page). A RAM having a storage capacity of the plurality of bytes for storing rewrite data is provided. The data write operation to the RAM is performed based on the decoding result of the program data read from the non-volatile memory, but the program operation is stopped during the data write operation from the RAM to the non-volatile memory. And is performed by hardware using a logic circuit or the like. In other words, the program operation is not restarted until the data writing from the RAM to the nonvolatile memory is completed.

[0004]

Therefore, when an interrupt request occurs at the time of writing data from the RAM to the non-volatile memory, the interrupt processing based on the interrupt request cannot be executed until the above-mentioned data writing is completed. was there. For example, one of the nonvolatile memory
If the page is 128 bytes, it takes about 5 msec to write 128 bytes of data, which is extremely inconvenient for urgent interrupt processing.

Therefore, an object of the present invention is to provide an interrupt processing device of a microcomputer capable of executing interrupt processing in parallel with data writing in the nonvolatile memory.

[0006]

The present invention has been made to solve the above-mentioned problems, and is characterized in that a first nonvolatile memory capable of writing and reading data is built-in. Then, in the one-chip microcomputer that performs the normal operation or the interrupt processing operation corresponding to the interrupt request based on the program data stored in the predetermined area of the first nonvolatile memory, the interrupt written in the first nonvolatile memory. A second non-volatile memory in which the same program data as the program data for executing the interrupt process based on the request is stored, a program counter for accessing the first and second non-volatile memories, and various interrupt requests An interrupt vector generating circuit for changing the value of the program counter to an address value, and the first nonvolatile memory. A control circuit for controlling the interrupt vector generation circuit to specify the address value of the program counter to the second non-volatile memory when an interrupt request is generated while writing data to a predetermined area of the non-volatile memory. , And that interrupt processing can be executed in parallel with the data writing operation of the first nonvolatile memory.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a diagram showing a microcomputer interrupt processing device of the present invention, showing an internal configuration of a one-chip microcomputer. In FIG.
(1) is an EEPROM (first non-volatile memory),
The program data for controlling the operation of the one-chip microcomputer and other various data are written therein. The EEPROM (1) has addresses from "0000H" to [7FFFH].
However, H is hexadecimal. In addition, the EEPRO
It is assumed that the broken line demarcation inside M (1) represents one page (for example, 128 bytes). The EEPROM
In (1), data can be rewritten for each page.

(2) is a mask ROM (second non-volatile memory) having addresses from "8000H" to "FFFFH". That is, the addresses of the EEPROM (1) and the mask ROM (2) are consecutive addresses in the same address space. From another perspective, EEPR
The addresses of the OM (1) and the mask ROM (2) are different in the most significant bits from "0" and "1", respectively. Then, the mask ROM (2) is written with the same program data as the program data for the interrupt process already written in the EEPROM (1). In addition, EEPR
The write address of the program data for interrupt processing with respect to the OM (1) and the mask ROM (2) is written at the same address except the most significant bit. The types of interrupt requests include timer interrupts and external interrupts. For example, if the program data for the timer interrupt request is written in "001BH" of the EEPROM (1), this program data is mask ROM.
It is written in "801BH" of (2), and only the most significant bit is different.

(3) is a program counter PC,
The address of either one of the EEPROM (1) and the mask ROM (2) is accessed. Reference numeral (4) is a page address latch, which is used to specify a page when rewriting data in the EEPROM (1), and which is an address required for specifying a page output from the program counter (3) in synchronization with the clock CLK. Top 9 data
It is to latch bits. Where clock CL
AND to apply K to the page address latch (4)
A gate (5) is provided. The AND gate (5)
Is applied with a signal MODE which becomes "1" when the EEPROM (1) is set to the data write mode, a signal AREA which becomes "1" when writing to the RAM (2) is designated, and a clock CLK0. Therefore, the signal MODE
When both AREA and AREA are "1", the clock CLK equal to the clock CLK0 from the AND gate (5)
Is output and applied to the page address latch (4).

The AND gates (6) and (7) and the OR gate (8) form a multiplexer, and the EEPROM (1)
16 are provided in accordance with the total number of addresses. 16
The 16-bit address data output from the program counter (3) is applied to one input of each AND gate (6). The page address latch (4) is connected to one input of the upper 9 AND gates (7).
The upper 9 bits of the address data latched at are applied. Further, the signal MODE is inverted and applied to the other inputs of the 16 AND gates (6) and 16 ANs are input.
The signal MODE is directly applied to the other input of the D gate (7). That is, when the data of the EEPROM (1) is rewritten, since the signal MODE is "1", the address value of the page address latch (4) is EEP.
The voltage is applied to the ROM (1), and the page of the EEPROM (1) is designated. On the other hand, when the EEPROM (1) is used as a normal data read state, the signal MOD
Since E is "0", the EEPROM (1) is directly accessed by the value of the program counter (3). EE
The write enable signal * WE1 is "0" during the period in which data is written in PROM (1).

(9) is a RAM, which is an EEPROM
It has a storage capacity for one page (128 bytes) of (1). The RAM (9) stores 128 bytes of data to be written in the EEPROM (1).
(10) is an in-page address latch, RAM
In order to access 128 bytes of (9), the lower 7 bits of the address data output from the program counter (3) are latched in synchronization with the clock CLK. The latch operation of the in-page address latch (10) is performed simultaneously with the latch operation of the page address latch (4). The RAM (9) is accessed by the value of the in-page address latch (10) and writes data of 128 bytes. The write enable signal * WE2 is "0" during this writing period. The write data stored in the RAM (9) is applied to the input port (11) byte by byte, and then temporarily stored in the accumulator ACC (13) via the internal bus (12).
It is again written to the designated address of the RAM (9) via the internal bus (12). This operation is repeated 128 times.

(14) is an oscillator for generating an oscillation clock of a predetermined frequency. (15) is a frequency divider that divides the oscillation clock by a predetermined frequency. Reference numeral (16) is a timer which counts with the divided clock of the frequency divider (15) and is reset with the clock CLK output from the AND gate (5). The state in which the clock CLK is applied to the timer (16) means that the RAM (2) is in a writing state, and the clock CLK is periodically applied during the data writing in the RAM (9). Since it is applied to the timer (16), the overflow signal OVF1 is not generated from the timer (16). However, when the data writing to the RAM (2) is completed, the signal AREA becomes “0”.
Therefore, the clock CLK is not generated. Then, the timer (16) counts up to a predetermined value, and the overflow signal OVF1 (=
"1") occurs. (17) is a frequency divider for dividing the oscillation clock by a predetermined frequency. The AND gate (18) has
The overflow signal OVF1 and the divided clock of the frequency divider (17) are applied. That is, the AND gate (18) outputs the frequency-divided clock of the frequency divider (17) after writing one page of data to the RAM (2) is completed. The in-page address latch (10) is reset by receiving the overflow signal OVF1.

When the writing of data for one page to the RAM (2) is completed, the clock CLK is interrupted, and the program counter (3), the EEPROM (1) and the RAM.
Access is blocked from (2). Therefore, the incrementer (19) is required. The incrementer (19) receives the divided clock output from the AND gate (18) and increments the in-page address latch (10) by hardware. For example, EEPROM
If one page in the shaded area of (1) is finally designated by the page address latch (4), the RAM
The 128-byte data written in (9) is
One byte of the hatched portion of the EEPROM (1) is accessed via the internal bus (12) by being sequentially accessed by the value of the in-page address latch (10) incremented by the incrementer (19) and read by one byte. Written in.

Therefore, from RAM (2) to EEPROM
Since the EEPROM (1) cannot be accessed by the program counter (3) while data is being written to (1), in the past, even if a predetermined interrupt request was generated during this period, the interrupt processing could not be executed. Is. In the present invention,
This problem can be solved. (20) is a timer, AN
The divided clock output from the D gate (18) is counted. Since the RAM (2) reads data in synchronization with this frequency-divided clock, if this frequency-divided clock is counted 128 times, 128 bytes of data are read from the RAM (2), that is, to the EEPROM (1). Data write can be detected. The timer (20) counts the output of the AND gate (18) 128 times to generate an overflow signal O.
Generate VF2.

An interrupt vector generation circuit (21) sets address data corresponding to various interrupt requests in the program counter (3). (2
Reference numeral 2) is an interrupt setting circuit, which sets which interrupt request has priority when multiple interrupts occur, and whether to enable or disable acceptance of interrupt requests. It controls (21).

The NOR gates (23) and (24) are control circuits which form an RS flip-flop,
One input of the NOR gate (23) has an inverter (2
5), the write enable signal * WE1 is applied, and the NOR gate (24) receives the overflow signal OV.
F2 (= “1”) and an initial clear signal INT generated when the one-chip microcomputer is reset
(= “1”) is applied. Therefore, the EEPROM
While the data is being written to (1), since the write enable signal * WE1 is "0" and the overflow signal OVF2 and the initial clear signal INT are "0", the RS flip-flop is set. "1" is output from the NOR gate (24). The interrupt vector generating circuit (21) fixes the most significant bit of the program counter (3) to "1" by receiving the set output of the RS flip-flop. Therefore,
When a predetermined interrupt request is generated while writing data to the EEPROM (1), the interrupt vector generation circuit (2
According to 1), the address data corresponding to the interrupt request is set in the program counter (3), but its most significant bit is fixed at "1". Therefore, EEPR
The mask ROM (2) is accessed instead of the OM (1), and the interrupt processing is executed in parallel with the data writing operation to the EEPROM (1).

On the other hand, when the one-chip microcomputer is reset, the initial clear signal IN
Since only T becomes "1", the RS flip-flop is reset and the output of the NOR gate (24) becomes "0". Then, the most significant bit of the address data set in the program counter (3) from the interrupt vector generation circuit (21) becomes "0". That is, the program counter (3) accesses the EEPROM (1). The same applies when the overflow signal OVF2 is generated. Therefore, when data is not written in the EEPROM (1), when the interrupt request is generated, the EEPROM is
The address where the program data for the interrupt request written in (1) is stored is the program counter (3).
Is accessed, and interrupt processing is executed based on the decoding result of this program data.

Reference numeral (26) is an instruction register IR for holding the program data read from the EEPROM (1) and the mask ROM (2) via the internal bus (12). Further, (27) is an instruction decoder IDEC which decodes the program data set in the instruction register IR (26) and generates a control signal for controlling the operation of the one-chip microcomputer. Of course, the control signal for the interrupt request is also obtained from the instruction decoder (27).

As described above, since the mask ROM (2) is configured to be accessed even if any interrupt request occurs during the data writing to the EEPROM (1), the data writing to the EEPROM (1) is performed. Interrupt processing can be executed in parallel. Therefore, even if an urgent interrupt request occurs, it can be immediately dealt with, and the data processing in the one-chip microcomputer will not be hindered.

In the embodiment of the present invention, EE
PROM (1) and mask ROM (2) in the same space,
Although only the most significant bit is set to be different, the setting is not limited to this, and for example, the entire address space is set to 00.
00H to FFFFH, mask RO in the middle
An M (2) address space may be provided. In this case, the interrupt vector generation circuit (21) may switch the address assigned to the mask ROM (2) to the program counter (3).

[0021]

According to the present invention, the second non-volatile memory is configured to be accessed by the control circuit even when an interrupt request occurs during data writing to the first non-volatile memory. As a result, the interrupt process can be executed in parallel with the data writing operation to the first nonvolatile memory. Therefore, even if an urgent interrupt request occurs, it can be immediately dealt with, and there is an advantage that it does not hinder the data processing inside the one-chip microcomputer.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an interrupt processing device of a microcomputer of the present invention.

[Explanation of symbols]

 (1) EEPROM (2) Mask ROM (3) Program counter (21) Interrupt vector generation circuit (23) (24) NOR gate

Claims (4)

[Claims] 1. An interrupt process which incorporates a first non-volatile memory capable of writing and reading data and responds to a normal operation or an interrupt request based on program data stored in a predetermined area of the first non-volatile memory. In a one-chip microcomputer that operates, a second non-volatile memory that stores the same or different program data as the program data for executing interrupt processing based on the interrupt request written in the first non-volatile memory, A program counter for accessing the first and second non-volatile memories, an interrupt vector generation circuit for changing the value of the program counter to an address value corresponding to various interrupt requests, and data for a predetermined area of the first non-volatile memory When an interrupt request is generated during writing, the interrupt A control circuit for controlling an address generation circuit to specify the address value of the program counter to the second non-volatile memory, and interrupt processing in parallel with the data writing operation of the first non-volatile memory. An interrupt processing device for a microcomputer, which is capable of executing. 2. The interrupt processing device for a microcomputer according to claim 1, wherein the first and second non-volatile memories are assigned consecutive addresses in the same address space. 3. The interrupt processing device for a microcomputer according to claim 2, wherein some bits of addresses of the first and second nonvolatile memories are different. 4. The control circuit receives the write enable signal for the first non-volatile memory during data writing to the first non-volatile memory to access the program counter to the second non-volatile memory. The interrupt vector generation circuit is controlled so that the value becomes possible, and when the writing of the data to the first nonvolatile memory is completed, the most significant bit of the program counter is set to the first nonvolatile by receiving a write end signal. 4. The interrupt processing device for a microcomputer according to claim 3, wherein the interrupt vector generating circuit is controlled so as to change the address memory to an accessible value.