JPS5952483A - Main storage device - Google Patents

Abstract

PURPOSE:To cope easily with the support of a new memory element and the memory extension, by controlling an address to a memory array card having different type without changing the circuit of the control card. CONSTITUTION:The memory array card 2 is provided respectively with a capacity identification signal generating circuit 3, the circuit 3 generates a capacity identification signal 102 being an information signal relating to the number of memory elements and capacity mounted on the said card 2 and transmits the signal to an address control circuit 4 of the control card 1. The control circuit 4 converts an address signal from an external device based on the capacity identification signal 102 and produces the memory address matched to the card 2 in response to the type of the memory element and transmits it. For example, the memory array card 2 having different type as TYPE 1, 2, 3 are controlled with the same control card 1.

Description

[Detailed Description of the Invention] (1) Technical field of the invention □ The present invention makes it possible to easily cope with the 1.1 increase in the capacity of memory elements mounted on main storage devices, especially memory array cards. It relates to main storage.

(2) Technical Background and ProblemsC) 1M storage devices used in data processing systems are generally memory array cards equipped with several memory elements such as so-called memory chips, and controls for controlling them.・It is composed of cards. Conventionally, the memory elements mounted on memory array cards are
Its capacity IB was fixedly determined in advance, and the main memory device could only be composed of memory elements of a specific capacity.However, with the recent rapid development of LSI technology, the capacity of memory elements has increased. It is rapidly increasing. However, as mentioned above, the conventional main memory device f"t has a specific capacity f"t.
.

(3) Object and structure of the invention The present invention aims to solve the problems mentioned in (1) and (2) above, and provides a memory element Furukawa, which is mounted on each control card of the same type.
Controls multiple types of memory array cards with different types υ11
The purpose is to make it possible to cope with the increase in memory element capacity by simply replacing the memory array card. Therefore, the main memory device of the present invention is composed of a plurality of memory devices each equipped with a memory element group.
In a main storage device consisting of an array card and a plurality of control cards that control the memory array card, the memory array card is mounted on the memory play card. Totomo is provided with a circuit for generating a capacity recognition signal that notifies the control card of the type of memory element, and the control card is provided with an address signal supplied from an external device and an address signal supplied from the memory array card. The present invention is characterized by providing an address control circuit that generates a memory address suitable for the memory element mounted on the memory array card based on the capacity recognition signal. A one-length embodiment will be described below with reference to the drawings.

(4) Embodiment of the invention Figure J-1 shows a schematic configuration of an embodiment of the invention, and Figure A-2 shows an example of address assignment for explaining the invention in detail.January 13
The figure is an example of the configuration of a memory element corresponding to figure 'A12, E-4.
The figure shows an example of an addressing system 611 circuit; ;)i'5 shows an example of a capacitance recognition signal generating circuit.

In the figure, 1 is a control card, 2 is a memory array card, and 3 is a capacity recognition signal generation circuit.

4 represents an address control circuit.

The main storage device is composed of a plurality of controller cards 1 and a plurality of memory array cards 2. Control card 1 is a central processing unit (CP).
External devices such as u) and channel control equipment (CIIC)
An interface signal 100 from the memory array card 2 controls input signals 101 such as control signals, addresses, and write data to the memory array card 2.
Control Ml+ is performed to send read data 103 from array card 2 to an external device. Addresses supplied to the control card 1 from an external device are assigned address bits with a margin in advance in anticipation of an increase in memory element capacity.

Memory play card 2 has 1 for example 16KW or 6
It is possible to mount a memory element with an arbitrary capacity of 1 ton, such as 4KW, and one type of memory element can be mounted on any memory array card 2 equipped with memory elements of different capacities, as explained below. It can be controlled by control card 1. A capacity recognition signal generation circuit 3 is added to each memory array card 2, and the capacity recognition signal generation circuit 3 generates information signals regarding the number and capacity of memory elements mounted on the memory array card 2. A certain capacity recognition signal 102 is generated and sent to the address control circuit 4 of the control card 1.

The address control circuit 4 has an address 1 supplied from an external device.
Converts the /S signal based on the 1) acknowledgment Af (t! signal) 02, and generates a memory address suitable for the memory array card 2 according to the type of memory element. , send.

Next, the following three types of memory configurations will be specifically explained.

Type 'A11 is a case where the capacity of one memory element mounted on the memory card 2 is 16KW. Hereinafter, the type i-2, referred to as TYPEI, is a case in which 16KW memory elements are connected by dot-OR to obtain 64KW. below.

'I' Y I) E 2, the N-3 type, is
This is a case of 64KW with one element. Below, 'rYl'E
It's called 3.

According to the present invention, memory array cards 2 of different types can be controlled by the same control card 1 in this way.

From TYPEI to TY l) E 3 memory
Addresses on array card 2 are assigned and used as shown in FIG. T Y )) E
In the case of 1, of the address given by 16 bits, 14 bits of address bits 02 to 15 are used as 16x(
The address of w is shown, and address bits 00, 01 are considered unused and ignored. For TYPF2, 14 bits of address bits 02-15 indicate the 16KW address within each memory element, and address bit 00°01 is decoded to select one of the four memory elements. made to respond to signals. '
l'Y For PE3, address bits OO~
A total of 15 16 bits indicates an address of 64KW.

Diagram NF3 shows an example of the configuration of memory elements in the memory array card 2 of each type. In the figure, numeral 5 represents a 16KW memory element, and 6 represents a 64KW memory element. DIN is write data, DOUT is read data, ADDRESS is address signal, CSO~C3
3 represents a selection signal. Especially T Y l) E
In case 2, 1) IN.

ADDRES is commonly supplied to each memory element by a dot OR, and DOUT is also connected by a dot OR. 9 selection signal C when accessing
Only one of 3O-C83 is made to be 1P', and one memory element r. is selected.

'A' 4 Figure C shows an example of the address control circuit 4 in the control card 1.

The address control circuit includes the address and
Signal 110 of bit OO, signal 111 of address bit 01, and capacity recognition signal A 112 supplied from the memory array card. 1ifll (f+
No. #3 122 and a memory activation signal 124 which is a timing signal are input. In this embodiment, in order to recognize and distinguish three types of memory array cards, two
The bit capacity recognition signal A·[t is used, and the signal A-112 is II Q11. Signal 13/122
is made to be "l", and for 'l'YPE2, both signal A 112 and signal I3 122 are 1.
For 'I'Y I' E 3, both signal A.112 and signal 13.122 are made to be 10''.

'l'' Y P E In case of 1, signal A・] 12 =
'0', signal 11/122='1'' is the corresponding controller)
・Is the roll card the rule? 11i1 memory play
Since the input is from the card, the outputs □114 and 116 of gates 11 and 13 become T,
Output 117 of gate □14 always becomes "1°1. On the other hand, outputs 118-120 of gates 1.15-17 always become 101°, and outputs 132-13 of gates 29-31
4 is always "0". Therefore, 'A-
Mail 4 input as one of the i-illustration signals 100
- The 4-motion signal 124 is always output only to the output terminal 131 and is supplied to the memory array card 2 as the 1 selection signal C8O.

TYI' E 2(7) case Niha, (IA -112
= 'l'.

Signal 13A = '1' is input from the memory array card, address bit 00 signal 11
0 and address bit O] by the signal ill.

Output 117 of game) 14 to 17 forming the decoding circuit
Only one of ~120 will be 1111. Since the output 121 of the gate 18 is 11'', the output 1
19 and output] 20 are connected to gates 20, 22, 2
4.25 and are input to gates 30 and 31, respectively. , therefore.

The memory 1[ij3 signal 124 is outputted to outputs 11.7, 118, 119.120 of the decoding circuit, and only to one of the output terminals 131 to 134.

A=3 shown in figure-t-TYPF, 2t7) IGKW memo!
One of the j elements 5 is selected.

i' Y P I! : In case of 3, signal A・1]
2 = 'O'.

fN issue [3・122 = '0'To'j!=
;') + T Y P As in the case of El, the chip select selection signal C8O is output only to the output terminal 131. On the other hand, since output 12'3 becomes gin, signal 110 of address bit ()0 and signal 111 of address bit 01 pass through gates 20 to 25 forming a multiplex circuit to gate 30 and gate 3.
1 and output to output terminals 133 and 134, respectively. This output is used as the upper two bits of the address for the 64i<w memory element 6 shown in FIG.

Figure 'A15 shows an example of the ht recognition signal generation circuit 3 for each of the above types. Depending on the type of memory element mounted on the memory array card 2, the
) or via the ζ'' resistor R to the power supply Vcc, it is possible to easily generate the capacitor 4 recognition signals 112 and 122 at the ``0'' level or the ``1'' level, respectively.

Although the case where the memory configuration type is three types has been described above, the present invention is not limited to this, and by increasing the number of bits of the capacity recognition signal, it is possible to support many more types. Needless to say, it is.

(5) As described in the detailed description of the invention, according to the present invention, the internal circuitry of the control card is not changed.

It becomes possible to control memory addresses for different types of memory cards.

It becomes possible to easily handle new support for new memory elements and memory expansion using memory elements with increased capacity. ′

[Brief explanation of drawings]

Figure 4-1 is a schematic configuration of one embodiment of the present invention, Figures ``A and 2 are examples of address assignment for detailed explanation of the present invention, A1
3 shows an example of the configuration of a memory element corresponding to FIG. 2, FIG. 4 shows an example of an address control circuit, and FIG. 315 shows an example of a volume recognition signal generation circuit. In the figure, 1 is a control card, 2 is a memory array card, and 3 is a damage recognition signal generation circuit. 4 is an address control circuit, and 5 and 6 are memory elements. 102.112.122 represents a capacity recognition signal. Patent applicant Fujitsu Ltd. Representative patent attorney Mori Ro1 Hiroshi (1 other person) Shin 1 figure □ Sai 2 figure,, Sai 3 figure (TYPE?) (TYPE 2) Kenki =

Claims (1)

[Claims] A plurality of memory devices comprising a group of memory elements (1/1)
In a main storage device consisting of a memory card and a plurality of control cards that control the memory array card, A circuit for generating a capacitance recognition signal for notifying the control card of the type of memory element is provided, and the control card is provided with a circuit for generating a capacitance recognition signal. A memory address suitable for the memory element mounted on the memory array card is determined based on an address signal supplied from an external device and a sewing recognition signal supplied from the memory array card. 1. A main memory device comprising an address control circuit that generates an address.