KR910000589B1 - Memory system providing a continuous address space - Google Patents

Abstract

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Description

Memory system providing contiguous address space

1 is a block diagram of an individual memory card.

2 is a block diagram of memory module slots arranged in series.

3 is a block diagram of a memory control circuit connected to memory card slots arranged in series.

4 is a block diagram of another embodiment including a memory controller connected to a memory card slot arranged in series.

* Explanation of symbols for main parts of the drawings

10: memory card 16: adder

30, 40, 50, 60, 70: Next address 100, 20: Memory controller

TECHNICAL FIELD The present invention relates to a computer memory system, and more particularly, to a computer memory system that allocates an address space between several individual memory modules to form a contiguous address space in the memory.

By convention, computer systems always include a memory system composed of several individual memory modules. This memory module is connected to the central processor by an information bus including address lines, data lines and control signal lines. Each individual memory module is accessed by a specific address signal on an address line that designates a memory location within the memory module.

Several techniques have been used to place memory addresses in memory modules. One commonly used technique is to use jumper wires or dual line package switches to specify the address space for a memory module. At that time, when the memory module is connected to the information bus, the memory module responds to an address in the designated address space. One disadvantage of this technique is that it must first determine the memory address placed first for the connected memory module to determine the appropriate address space for the newly added module. Another disadvantage is that it is not possible to increase the size of the memory module by changing the capacity of the memory chip because of the limited number of switches used to specify jumper wires or address space. Another disadvantage is that increasing the memory capacity of the memory module itself requires a complete relocation of memory addresses for other memory modules. If multiple memory modules are involved, this can be a very tiresome task.

Another technique is disclosed in US Pat. No. 4,414,627, entitled "Main Memory Control System." The system includes an address translation table, which includes a module indicating whether the unit is operating and a word register addressable by a logical address to store each predetermined physical unit memory address for a corresponding flag signal. As with the jumper technology, this technology needs to select a module for the address space.

U.S. Patent No. 3,469,241, entitled "Contact Addressing Supply Data Processing Device for Non-Contact Storage," describes a technique in which when a data processing unit communicates with a memory, it symbolically supplies a signal group representing the address of a memory cell. To announce. The symbolic address is applied to a translation device that generates the actual address of the cell being accessed. Again, this technique requires the selection of an address space.

According to the present invention, a memory system for providing a contiguous address space, each circuit having a circuit for supplying a memory module capacity, comprising several memory modules, has been disclosed. The memory module capacity is indicated by numerical information representing the capacity of the memory module or the memory card, and this is also called the memory card capacity or the memory capacity. A control circuit is provided for allocating one start address to the first module and all other start addresses to each remaining module according to the first allocated start address and the first allocated memory module capacity.

In one embodiment of the invention, several memory cards are connected to an information bus. The processor supplies the start address to the first memory cards arranged in series. Each memory card includes a circuit for supplying a memory capacity of each memory card and a control circuit for receiving a start address, and each of its cards for supplying a next card address supplied to a serially arranged next memory card. Add memory capacity. After receiving the start address, each memory card supplies the start address to a daisy chained serially arranged next card. In this way, adjacent address spaces are provided.

In the second embodiment, a main memory control circuit is provided which includes several adders, each connected to a separate memory module. The memory module provides an adder having a memory capacity of each module. Each adder combines memory capacity with a start address to provide a next address to the next adder placed in series. In addition, the memory controller includes an address comparison circuit for each memory module to determine when a particular memory module is being addressed.

In the third embodiment, the memory controller described in the second embodiment is provided. However, the line extending from the memory module to the adder is bidirectional. In the first direction, the memory capacity is supplied to each adder of the memory modules. In the second direction, a lower address is supplied to access individual memory locations in each memory module. The direction control of these bidirectional lines is provided by control signals to each memory module. High order address decoding is performed on the memory controller as in the second embodiment. That is, the memory comparison circuit on the memory controller selects each memory module when addressed.

It is an object of the present invention to assign addresses to individual memory modules in order to provide the entire contiguous address space in accordance with the initial power load. 1 and 2 illustrate one embodiment of the present invention. 1 is a block diagram of an individual memory card 10 including a memory array 11 connected to a data bus 8 and a memory array address bus 25. The start address for the memory module is supplied to adder 16 at line 18. The adder 16 combines the memory card capacity from the block 12 on the line 14 to the start address to calculate the next start address for the next memory card arranged in series. The next start address is the output on the line 20 arranged in series and going to the next card (not shown). The memory card capacity is also supplied to the address comparison logic 24 by the line 21. The address comparison logic also receives the start address on line 18 and adds the received start address to a memory card capacity such as adder 16 to calculate the next start address. Thus, the address comparison logic can determine the address space (ie address range) for the federated memory array 11. This address space is limited to include all addresses up to the start address and the next start address. This address space is compared with a useful address on the address bus 27 to determine when the card select signal 26 is supplied, and on line 25 the memory array address is accessed to access a memory location within the memory array 11. Is provided. Control lines, such as leads / lights, are also installed which are not shown. Memory card capacity block 12 may be a read-only memory, a set of jumpers, a double-in-line switch, or any circuit element providing a number representing memory card capacity. As is known in the art, dual-in-line switches comprise a plurality of switch elements, each of which can be manually set in the on and off positions. This switch is associated with an electrical circuit having a function of generating a signal according to the setting of the switch element. In this case, therefore, the switch elements are set so that the signal represents the memory capacity. Electrical devices using jumpers (ie short wires) are also well known in the art. The device has a plurality of jumper positions each having a pair of terminals. These jumpers are used to make electrical connections between selected terminal pairs so that the device generates a signal according to the electrical connections. By properly selecting the terminal pairs, this signal represents the memory capacity. If a double-in-line switch or jumper is provided, the number of switch elements or jumper positions must be sufficient so that the memory card capacity is simply refreshed when the size of the memory array 11 is increased.

2 shows the location and interconnection of memory card slots 30, 40, 50, 60, and 70. FIG. Each of these slots 30, 40, 50, 60, and 70 is connected to an address bus 34, a data bus 36 and a command bus 38. In addition, slot 1 30 is connected to receive a start address on line 32. In this embodiment, the start address is supplied by a processor card (not shown). Once the memory is located on the processor card, the start address can be a useful next address after the address is assigned to the processor memory. This start address information is processed by the memory card in slot 30 to supply the next address on line 42 to the sequentially placed next card in slot 2 (connector 40) discussed. Memory card 40 in slot 2 supplies the next address on line 52 to memory card 50 in slot 3 and the other for the object slot. In this way, the start address for a memory card is assigned in the form of a daisy wreath that supplies the address space adjacent to this card. This address space is contiguous even though the card itself in this slot is of varying memory capacity.

It is clear from Figure 2 that many slots are being implemented. As shown in FIG. 2, when the next address lines are daisy-chained, each slot is connected to a common address bus 34, a data bus 36 and a command bus 38. As shown in FIG. Those skilled in the art, along with address bus 34, data bus 36, and command bus 38, start addresses on lines 32, 42, 52, 62, and 72 It can be clarified that it includes serial or parallel lines.

3 illustrates a second embodiment of the present invention that includes a memory controller 100 situated on a processor card or some other central location. The memory controller 100 includes adders 103 to 106 and address comparison circuits 107 to 111. Memory card slots (1) through (N), including connectors 150, 152, 154, 156, and 158, include data bus 116, address bus 118, and command bus 119. Each bus is common to all connectors 150, 152, 154, 156 and 158. In addition, each of the connectors 150, 152, 154, 156, and 158 is individually connected to an adder and an address comparison circuit of the memory controller 100. Each memory card (not shown) in slot 1 includes means for providing memory capacity to one of lines 122, 126, 130, 134, and 138 via an associated connector of connectors 150, 152, 154, 156, and 158.

Referring now to the memory controller 100, the initial start address is supplied to the adder 106 on line 112. As before, the initial start address is generated from the processing substrate. This start address on line 112 is combined with the memory capacity on line 122 resulting from connector 150 connected to the memory card in slot 1. The memory capacity on line 122 and the start address on line 112 are added together in adder 106 to supply the next address on line 140 to adder 105. The memory capacity on the line 122 and the start address on the line 122 are the address comparison circuit 111 to enable the address comparison circuit 111 to determine the address space for each memory module located in the slot 1. Supplied to. The high address line on line 114 is supplied to address comparison logic 111 to enable address comparison logic that determines whether a memory module is being accessed. If a memory module is being accessed, a module select signal on line 120 is supplied to connector 150 to signal the memory module in slot 1, where the memory module in slot 1 accesses the memory location on the memory module. To receive the lower address on line 118.

The next address on line 140, which is supplied to adder 105, is converted using memory capacity data on line 126 to supply the next address on line 142 in a similar manner. In this way, each adder 103-106 receives each start address and memory capacity, respectively. The adder 103 outputs the next start address to the address comparison circuit 107 for the slot N located last including the connector 158.

The address comparison circuits 107 to 111 are individually connected to the address bus 114 to receive the start address and the memory capacity for each memory module. For example, the address comparison circuit 111 receives the start address on line 112 and the memory capacity on line 122 to limit the address space for the memory module in slot 1. When a suitable address is received on line 114, the address comparison circuit 111 decodes the address and the address on line 118 along with the data on the data bus 116 and the command signal on the command signal bus 119. The card select signal on line 120 is supplied to activate the card in slot 1 receiving. Each address comparison circuit 107-111 receives a memory capacity from each slot connector to provide a memory address space for each memory module. As one of ordinary skill in the art will appreciate, placing the high address line on 114 into the memory controller 100 allows each slot connector 150, 152, 154, 156 and 158 to be placed. The number of address lines going to) is reduced. Each of these slot connectors 150, 152, 154, 156 and 158 memory individual memory capacity lines 122, 126, 130, 134 and 138. Required to supply controller 100. Additionally, connectors 150, 152, 154, 156 and 158 are individually on respective lines 120, 124, 128, 132 and 136. Receive the module selection signal.

Figure 3 shows that the memory control circuitry includes the entirety of the daisy wreath sequence, which supplies the start address to the address comparison circuit for each memory module in the slot, is performed on a common circuit board or a single integrated circuit, and is required to access information within a separate memory module. There is an advantage of reducing the address line.

4 illustrates a third embodiment of the present invention for reducing address bus lines going to memory modules in slots 1 through N as shown. Each memory module (not shown) has means for providing memory capacity through an associated connector of connectors 250,252,254,256 and 258. As already explained, the memory controller 200 has adders 203 to 206 and address comparison circuits 207 to 211, each acting in a manner similar to the counterpart of FIG. The initial start address is supplied on line 212 and the next address is supplied in a daisy wreath on lines 240, 242, 244 and 248. Furthermore, the higher address line is supplied to address comparison circuits 207 through 211 on line 214. The individual address comparison circuits 207 to 211 combine the start address with the memory capacity to determine the address space for each memory module, respectively. The outputs of the individual address comparison circuits 207 through 211 are modules on lines 220, 224, 228, 232 and 236 that go to each memory module in slots 1 through N. It is a selection signal.

The difference in this embodiment is that the data flows on lines 260, 262, 264, 266 and 268 are bidirectional. In this embodiment, these lines are connected to an address bus 218 that contains the low order bits for the memory location within the memory module. By adding a control line on the command bus 219, the directions of lines 260, 262, 264, 266, and 268 become clear. In this embodiment, the initial direction is from memory module connectors 250, 252, 254, 256 and 258 toward adders 203 through 206 and each line 222, 226. ) And address comparison circuits 207 to 211 for supplying memory information on (230), (234), and (238). In the second state, the command signals on the command bus 219 are lines 260, 262, 264 such that the memory in the slots 1-N can receive the lower address of the address bus 218. Reverses the direction of the data flow on (2), (266) and (268). Since memory capacity data is required only when initializing the address space, multiplexing the address bus 218 with memory capacity information on lines 222, 226, 230, 234, and 238 is a slot. It does not affect the memory module access timing in (1) to (N).

Although the invention has been shown in detail and described with reference to preferred embodiments, many other changes in form and detail can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims (4)

A memory system that provides a contiguous memory address to a processor connected to a memory system by an information bus (e.g., 114,116,118, or 214,216,218) for the transfer of address and data information, includes a plurality of removable memories serially connected to the information bus. A module (modules in slots 1 to N), each module having means 12 for providing memory capacity; Control means (e.g., 100 or 200) for receiving a start address from the processor and being connected to the information bus to receive address information from the processor and a memory module capacity from a memory module; Assigning an address range to each memory module based on memory module capacity and sending a module selection signal to each of the memory modules when the received address information is within the address range allocated for each of the memory modules; Memory system. 2. The apparatus according to claim 1, wherein said control means adds the memory capacity of each memory module to a start address from said processor or to a next start address from a preceding adder means for generating a next start address for a next serially connected memory module. Determine an address range for each memory module based on a plurality of serially connected adder means (e.g., 103 to 106, or 203 to 206) and a start address from the processor or a next start address from a preceding adder means. And a plurality of address comparison means (e.g., 107 to 111, or 207 to 211) for providing a module selection signal for the memory module when the address information is within the determined address range. 3. The information bus of claim 2 wherein the information bus has a plurality of parallel address lines that are high to low in grade, and wherein the plurality of low grade address lines (e.g., 118 or 218) are connected to the memory module while being high. And a number of remaining address lines of class (e. G. 114 or 214) are connected to said address comparing means. 4. The method of claim 3, wherein the row grade plurality of address lines (e.g., 218) are connected to delivery lines (e.g., 260, 262, 264, 266, 268) used to convey the memory capacity of an associated memory module to the control means. And a control line (e.g., 219) for providing a control signal from said processor to control the direction of signal flow across said delivery line.

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