WO1993004430A1

WO1993004430A1 - Self-configuration of memory addresses for computer memory having multiple memory module types

Info

Publication number: WO1993004430A1
Application number: PCT/US1992/006899
Authority: WO
Inventors: Angela Gracita Hopkins
Original assignee: Digital Equipment Corporation
Priority date: 1991-08-15
Filing date: 1992-08-14
Publication date: 1993-03-04

Abstract

A computer system employs a memory board having a number of slots to receive memory modules, so the memory may be of variable size. The modules provide 'present' and 'type' signals to indicate whether a module is present, and if so, what size it is. These present and type bits are used along with high-order address bits to generate memory activating signals. The modules are preferably single-in-line-modules or SIMMs of standard pin-out and the memory devices in the SIMMs are DRAMs, in which case the memory activating signals are row and column address strobes. The memory addressing signals are generated by logic circuitry in the memory itself, and so the address configuration is transparent to the CPU or to software executing on the CPU.

Description

SELF-CONFIGURATION OF MEMORY ADDRESSES

FOR COMPUTER MEMORY HAVING

MULTIPLE MEMORY MODULE TYPES

* * * * *

BACKGROUND OF THE INVENTION

This invention relates to computer systems, and more particularly to a memory subsystem for a computer system and a method for self-configuration of memory arrays to support memory modules of different sizes.

Computer systems are usually constructed with main memory subsystems which may be configured with widely variable sizes. For example, a desktop computer system might be delivered by a vendor with main memory anywhere in the range of 1-Mbyte to 32-Mbyte, or a workstation or file server type of computer might be delivered with main memory of from 8-Mbyte to 128-Mbyte. In addition, it is usually possible for the end-user to upgrade main memory by adding memory modules. As the DRAM devices ordinarily used for main memory become available economically in increasing densities, progressing from 1-Mbit to 4-Mit, 16-Mbit, and above, it is preferable to be able to upgrade using the higher-density devices without modifying the memory boards.

One of the preferred forms of DRAM memory packaging for systems requiring high density and large capacity is the so-called SIMM or Single Inline Memory Module. This is an industry-standard package format, and a memory configuration should employ pin assignments that are in conformance with the standards for DRAM SIMM modules. In U.S. Patent 5,012,408, issued to D.G. Conroy and assigned to Digital Equipment Corporation, assignee of this invention, a memory addressing system is illustrated having a set of memory module slots, where each slot may be empty or may contain a memory module. The slots may accept at least two different sizes of modules, and each module produces a memory type signal denoting the amount of memory in the module. Upon power-up of the system, initialization software analyzes the memory type signals from the slots, and assigns physical address ranges for the modules accordingly. It is preferred, however, for the present purposes, to avoid requiring a software routine to assign memory address ranges. Instead, a hardware (i.e., circuit) implementation is preferred, where the memory configuration is transparent to the operating system or other software executing on the CPU.

U.S. Patent 4,281,392 shows a memory arrangement having a number of slots adapted to receive memory modules varying in size and type; for example 1- Kbit or 4-Kbit. A decoder circuit receives size feedback signals from each memory module, enabling it to automatically assign to each module the address space it requires. Additional feedback signals from the modules specify what type of memory it is, e.g., ROM or RAM, so the proper activating signals may be used by the memory controller. The circuitry of patent 4,281,392, however, does not permit the situation of having some of the low-order slots empty, i.e., if there are empty slots, they must be the higher-order slots.

SUMMARY OF THE INVENTION

In accordance with one embodiment of the invention, a computer system employs a memory board having a number of slots to receive memory modules, so the memory may be of variable size. The modules provide "present" and "type" signals to indicate whether a module is present, and if so, what size it is. These present and type bits are used along with high-order address bits to generate memory activating signals. The modules are preferably single-in-line-modules or SIMMs of standard pin-out and the memory devices in the SIMMs are DRAMs, in which case the memory activating signals are row and column address strobes. The memory addressing signals are generated by logic circuitry within the memory board itself, and so the address configuration is transparent to the CPU or to software executing on the CPU. The slots may be populated by the memory modules in any order of size, with slots being left empty in any order.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as other features and advantages thereof, will be best understood by reference to the detailed description of specific embodiments which follows, when read in conjunction with the accompanying drawings, wherein:

Figure 1 is an electrical diagram in block form of a computer system which may employ the features of one embodiment of the invention; Figure 2 is an electrical diagram in block form of a module control circuit used in the computer system of Figure 1 employing features of one embodiment of the invention;

Figures 3 and 4 are diagrams of SIMM modules used in the system of Figures 1 and 2; and

Figures 5-9 are diagrams of memory maps for various configurations of memory sizes using the modules of Figures 3 and 4 in the circuit of Figure 2, according to the invention, illustrating the generation of RAS signals.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Referring to Figure 1, a computer system is illustrated which may employ the address self-configuration method for memory modules according to the invention. A CPU board 10 includes a processor 11 coupled to a system bus 12, where the system bus includes an address bus 12a, a data bus 12b and a control bus 12c. A main memory board 15 is connected to and accessed by the system bus 12. The CPU .10 usually would be implementing a virtual memory management system such as that provided by the UNIX™ or VAX/VMS™ operating systems, and so a virtual-to-physical address translation is made when memory references are executed, and pages of data are swapped between physical memory provided by the main memory 15 and secondary storage in the form of a disk 16. The VAX architecture is described by Levy and Eckhouse in "Computer Programming and Architecture: The VAX", 2nd Ed., Digital Press, 1989, which is incorporated herein by reference. The CPU 10 may be of the VAX™ type as disclosed by in the Levy et al text or in U.S. Patent 5,006,980, issued to Sander, Uhler & Brown, assigned to Digital Equipment Corporation, the assignee of this invention, or, alternatively, may be of an advanced 64-bit RISC type as disclosed in copending application Serial No.547,630, filed June 29, 1990, also assigned to Digital Equipment Corporation. Of course the CPU 10 may be of any one of a number of other types of construction, such as the 386 type, or using the MIPS R3000 RISC processor, for example. Also, it should be noted that the method to be described may also operate in a multiprocessor environment, in which a number of processors 11 connected to a common system interconnect 12 would each access the main memory 15.

The main memory board 15 is accessed through a memory controller 20 on the CPU board, functioning to convert the non-multiplexed address on the address bus 12a of the system bus 12 to a multiplexed address (ordinarily used for DRAMs), and to convert the memory address strobe on the control bus 12c of the system bus 12 to RAS and CAS strobes. The multiplexed address and RAS and CAS strobes are applied to a module controller 21 by a bus 22.

Referring to Figure 2, the module controller 21 includes a circuit 23 receiving the multiplexed address, bits <9:0> in this case, on address lines 22a from the CPU board and applying it to the memory board 15 by lines 24 so that this part of the address is reaches all of the slots. The multiplexed ten-bit address provided by these bits <9:0> addresses a 1-Mbyte range (actually 2¹⁰ or 1,048,576 in decimal or FFFFF in hex). Output enable OE and the read/write R/W command are also applied to the memory board 15 via the module controller 21, where circuit 26 receives these signals by lines 27. These signals are derived from similar signals originating in the processor chip 11. A logic circuit 30 receives the four high-order address bits <23:20> on lines 31 and uses these to select which one of the 1-Mbyte memory sections to activate for a given memory operation. According to the invention, the present and type signals on lines 32 from the SIMM modules is also used by the logic circuit 30 to make this selection. The logic circuit 30 also receives a memory-enable command on line 33, and a refresh command on line 34. When a refresh operation is signalled by the memory controller 20, all DRAM modules are driven by CAS before RAS, and there need be no selection of modules because there is no data input or output.

The memory board 15 in this example contains three slots 37, 38 and 39 as seen in Figure 2 to receive SIMM modules of either 2-Mbyte or 4-Mbyte size. Referring to Figures 3 and 4, the SIMM modules for slots 37, 38 and 39 may be of two sizes in this embodiment. One is a 2-Mbyte module 40 of Figure 3 having eight 1-Mbit DRAM chips 41 on each side of a double-sided board 42, for a total of sixteen DRAM chips. An edge connector 43 plugs into the mating connector of the slots 37, 38 or 39. Each DRAM chip 41 is of the 256Kx4 configuration. The data I/O bus is 32-bits wide, so eight DRAMs 41 are in parallel at each address location. The DRAMs 41 receive one of four CAS lines CASO-CAS3, and one of two RAS lines RAS0-RAS1. The other size is a 4-Mbyte module 44 of Figure 4 having four 4-Mbit DRAM chips 45 on each side of a double-sided board 46, for a total of eight DRAM chips. The edge connector 43 for plugging into the mating connector of the slots 37, 38 or 39 is the same as in Figure 3. Each DRAM chip 45 is of the 1-Mx4 configuration. All eight of the DRAMs 45 are in parallel to provide the 32-bit wide data I/O bus. The sockets for slots 37, 38 and 39 and the edge connectors 43 each contain a 32-bit data bus connecting to bus xx, a 10-bit address bus receiving the multiplexed address bits <9:0> from lines 24, R/W and OE lines, Vdd and Vss lines, and, according to the invention, pins for present and type signals. The slots 37, 38 and 39 are referred to a slot-1, slot-2 and slot-3, and produce present and type bits referred to as psntl and type1, psnt2 and type2, and psnt3 and type3, respectively. The status of SIMM modules in the slots 37, 38 and 39 is represented by the present and type bits as follows:

Present Type SIMM Memory

0 1 2-Mbyte

0 0 4-Mbyte

1 1 Not Present

The memory board 15 in the example embodiment has 2-Mbyte of memory permanently in place, in the form of sixteen 256Kx4 DRAM chips 48 arranged in two rows of eight each. These two permanent rows are driven by RAS0 and RAS1, and CAS0<3:0>, which are always present if the address, in this range. The RAS and CAS strobes to slots 37, 38 and 39 are dependent upon whether and in what sizes SIMMs are in the slots. Slot-1 is driven by RAS2 and RAS3 and CAS2<3:0>. Slot-2 is driven by RAS4 and RAS5 and CAS4<3:0>. Slot-3 is driven by RAS6 and RAS7 and CAS6<3:0>.

Referring to Table A, the additional memory in the board 15 (above the 2-Mbyte permanent memory) may be from 0-Mbyte to 12-Mbyte, as listed in the left column, corresponding a minimum of no SIMMs present in the slots 37, 38 and 39, up to a maximum of three 4-Mbyte SIMMs present. In the case of 6- Mbyte added memory, this can be configured seven different ways, with a 2-Mbyte and a 4-Mbyte SIMM positioned in the three slots in various order. The present and type bits for the various configurations is shown in the table. These are the status bit combinations connected to the logic circuit 30 by the lines 32. The present and type status of each slot location on lines 32 is combined with the corresponding address select lines 31 in the logic circuit 30 to perform the appropriate bank select by generating the appropriate RAS strobes. In Table B, the logic equations implemented in the logic circuit 30 for generating the RAS signals in lines xx are given. The RAS signals are active-low, while the address signals A20-A23 are active high. In the equations of Table B, the notation ! means the signal is not asserted, so ! A20 means the A20 address line is low, while ITYPE1 means the typel line is high (since typel is active-low). The # notation means logical OR, and & means logical AND. Thus, RAS3 is asserted (low) when A22 and A21 are high, A23 and A20 are low, and presentl and typel are low. The diagrams of Figures 5-9 provide a graphical representation of the functional interdependencies among product terms of Table B. These diagrams of Figures 5-9 are formatted for 2-Mbyte and 4-Mbyte SIMMs in a contiguous memory map, for several examples. The concept is adaptable to other configurations by changing the variables. The memory address space is separated into 1-Mbyte increments. The BANKO through BANK13 notation represents the A23-A20 address decode of each 1-Mbyte increment. Decodes are generated for the type of SIMM installed in a location, and is dependent on the status of a SIMM in a previous location (if any). RAS4 and RAS6 are illustrated. Figures 5 and 6 are for the SIMM1 slot being populated or empty, respectively. For example, from Figure 5, with SIMM1 populated with a 2-Mbyte SIMM as indicated by block 47, then RAS4 is generated to address bank4 and bank5 if a 2-Mbyte SIMM is in slot2 as indicated by a block 48, or RAS4 is generated to address banks 4-to-7 if slot2 is populated by a 4-Mbyte SIMM. However, if slot1 is populated by a 4- Mbyte SIMM as indicated by a block 49, RAS4 is generated for bankό and bank7 if a 2-Mbyte SIMM is in slot2, indicated by block 50, or generated for banks 6-to-9 if slot2 is populated by a 4-Mbyte SIMM. On the other hand, if slot1 is empty. the case for Figure 6, RAS4 is generated for bank2 and bank3 for a 2-Mbyte SIMM in slot2, or generated for banks 2-to-5 for a 4-Mbyte SIMM in slot2. Figure 7 illustrates the generation of RAS6 for situations where slot1 and slot2 have either 2- or 4-Mbyte SIMMs, and slot3 has either 2- or 4-Mbyte SIMMs; the fully-populated situation shows 4-Mbyte SIMMs in all three slots as illustrated by blocks 51, 52 and 53. Figure 8 shows the generation of RAS6 for slot3 when one of slot1 or slot2 is empty, and Figure 9 shows generation of RAS6 when both slot1 and slot2 are empty. Each graph of Figures 5-9 represents a set of minterms for each bank select. The bank selects are then gated with RAS and CAS to enable the DRAMs. These minterms are directly translated into logic equations by combining the address decode with the corresponding present and type bits for each location.

In summary, this invention allocates address space which is determined per slot location based on the size of an installed SIMM. The decode is performed by determining the presence and types of individual SIMMs installed in a slot location. The decoder 30 then configures based on the known status of the memory module in a slot location to determine the bank select over a valid address range. The full implementation allows any slot location to become mapped into the starting memory address if the previous slots are empty.

This method provides the advantage of a contiguous memory map to software where the boundary addresses and configuration of the memory modules are transparent to software. The autoconfiguration is implemented in the logic design of the circuits, not requiring any intervention by the operating system software. This method provides maximum versatility of memory module configurations where the correct mapping will occur independent of memory module type and location. The format of the method provides a straightforward procedure for mapping all possible configurations of the memory array. This format identifies the interdependencies of the memory map on the physical array by graphical representation of a number of variables. The flexibility of the method allows cost savings where a memory controller can be designed to support multiple SIMMs. As the price per bit of memory devices decreases, a single hardware platform can support multiple configurations for extended memory expansion.

While this invention has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.

Claims

WHAT IS CLAIMED IS:

1. A computer system including a memory and a CPU producing memory addresses to the memory, the memory comprising:

a memory board having a plurality of slots, where each slot may be empty, or may contain a memory module containing one of two different memory capacities, the memory board providing an indication of the presence and capacity of memory modules in each of said slots;

memory addressing means receiving a part of each of said memory addresses from said CPU and receiving said indication for each of said slots, and producing memory-activating signals to said memory board to access said memory in a contiguous addressing range regardless of the content of said slots.

2. A device according to claim 1 wherein said memory modules contain dynamic RAMs, said addresses are multiplexed, and said memory-activating signals are row-address-strobe and column-address-strobe signals.

3. A device according to claim 1 wherein said indication of presence and capacity is a two-bit value, where one bit indicates present or absent and the other bit indicates one of said two capacities:

4. A device according to claim 2 wherein said addresses include a multiplexed portion applied to all of said slots, and said part is not multiplexed.

5. A method of operating a computer system which includes a memory and a CPU producing memory addresses to the memory, said method comprising the steps of: providing an indication of the presence and capacity of memory modules in each of a plurality of slots in a memory board, where each slot may be empty or may contain a memory module containing one of two different memory capacities;

addressing said memory in response to a part of each of said memory addresses from said CPU and said indication for each of said slots, using memory-activating signals to said memory board to access said memory in a contiguous addressing range regardless of the content of said slots.

6. A method according to claim 5 wherein said memory modules contain dynamic RAMs, said addresses are multiplexed, and said memory-activating signals are row-address-strobe and column-address-strobe signals.

7. A method according to claim 5 wherein said indication of presence and capacity is a two-bit value, where one bit indicates present or absent and the other bit indicates one of said two capacities.

8. A memory device for use with a CPU producing memory addresses to the memory device, comprising:

a memory board having a plurality of slots, where each slot may be empty, or may contain a memory module containing one of a number of different memory capacities, the memory board providing an indication of the presence and capacity of memory modules in each of said slots;

memory addressing means receiving a part of said memory addresses from said CPU and receiving said indication for each of said slots, and producing memory-activating signals to said memory board.

9. A device according to claim 8 wherein said memory-activating signals are row-address-strobe and column-address-strobe signals.

10. A device according to claim 9 wherein said addresses are multiplexed, and said memory modules contain dynamic RAMs.

11. A device according to claim 10 wherein there are at least three of said slots.

12. A device according to claim 11 wherein said memory modules in said slots are single-inline-memory-modules.

13. A device according to claim 8 wherein said memory modules may be of two different capacities, and said indication of presence and capacity is a two- bits value, where one bit indicates present or absent and the other bit indicates one of said two capacities.

14. A device according to claim 13 wherein one of said two capacities is double that of the other of said two capacities.

15. A device according to claim 14 wherein said memory modules contain dynamic RAMs, said addresses are multiplexed, and said memory-activating signals are row-address-strobe and column-address-strobe signals.

16. A method of operating a memory device for a CPU producing memory addresses to the memory device, comprising:

generating in a memory board having a plurality of slots, an indication of the presence and capacity of memory modules in each of said slots, where each slot may be empty, or may contain a memory module containing one of a number of different memory capacities;

generating memory-activating signals for applying to said memory board in response to a part of said memory addresses from said CPU and to said indication for each of said slots.

17. A method according to claim 16 wherein said memory-activating signals are row-address-strobe and column-address-strobe signals.

18. A method according to claim 17 wherein said addresses are multiplexed, and said memory modules contain dynamic RAMs.

19. A method according to claim 18 wherein there are at least three of said slots.

20. A method according to claim 19 wherein said memory modules in said slots are single-inline-memory-modules.

21. A method according to claim 16 wherein said memory modules may be of two different capacities, and said indication of presence and capacity is a two-bits value, where one bit indicates present or absent and the other bit indicates one of said two capacities.

22. A method according to claim 21 wherein one of said two capacities is double that of the other of said two capacities.

23. A method according to claim 22 wherein said memory modules contain dynamic RAMs, said addresses are multiplexed, and said memory-activating signals are row-address-strobe and column-address-strobe signals.