GB2255843A - Optional memory. - Google Patents

Optional memory. Download PDF

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Publication number
GB2255843A
GB2255843A GB9210225A GB9210225A GB2255843A GB 2255843 A GB2255843 A GB 2255843A GB 9210225 A GB9210225 A GB 9210225A GB 9210225 A GB9210225 A GB 9210225A GB 2255843 A GB2255843 A GB 2255843A
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GB
United Kingdom
Prior art keywords
memory device
means
optional
memory means
set
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9210225A
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GB9210225D0 (en
Inventor
Yoshihiko Ide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
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Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP13534191A priority Critical patent/JPH04336347A/en
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Publication of GB9210225D0 publication Critical patent/GB9210225D0/en
Publication of GB2255843A publication Critical patent/GB2255843A/en
Application status is Withdrawn legal-status Critical

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646Configuration or reconfiguration
    • G06F12/0653Configuration or reconfiguration with centralised address assignment
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646Configuration or reconfiguration
    • G06F12/0684Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection

Description

1) 1 - " e- ' 5 5;.> i 1 "OPTIONAL MEMORY DEVICE" The present invention

relates to a memory device, and more particularly to a memory device of laser printer controller boards, microcomputers, and the like, which memory device is provided as expansion memory and used as optional memory for these apparatuses, and the like.

Memory devices are provided with slots having connectors or sockets for setting the storage medium, such as RAM elements and the like, inside the device, and are used as optional memories. When the capacity of the main memory inside the microcomputer has become insufficient, a CPU of the microcomputer accesses the optional memory, and thereby makes up for the insufficiency in the memory capacity.

The memory capacity of optional memories of such computer related apparatuses is predetermined as either 1M bytes or 4M bytes. The memory capacity can therefore be increased, as per the above accessing performed by the CPU, when a new application is installed. However, the memory capacity of option boards is predetermined, and so the memory capacity will still be insufficient when 21 1 a new application exceeds the expanded memory capacity. In cases such as these, the CPU of the microcomputer may either not be able to use the newly installed application, or may need to rebuild the memory of the main board internal to the computer.

Accordingly, a general object of the present invention is to eliminate the problems associated with the conventional technology, and to provide a novel and effective memory device.

A more specific object of the present invention is to provide a memory device which can use an application by means of only optional memory expansion, even in cases when much memory capacity is needed to do so.

The above-stated objectives can be attained by an optional memory device additionally provided to a main memory, which optional memory device comprises at least one of a plural number of memory mediums in a state such that the one memory medium is mountable and demountable, comprises an identification signal output portion, which outputs identification signals on the basis of types and capacities of the plurality of the memory mediums set in the optional memory device, and comprises 3 also a detector portion that uses the identification signals output from the identification signal output portion to detect types and capacities of the memory mediums.

Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the FIG.1 is a composition of a memory according to the present invention; FIG.2 is a block diagram showing a composition of a slot of a memory device of an embodiment according to the present invention; FIG.3 is a block diagram showing a a DRAM control of a memory device of an embodiment according to the present invention; FIG.4 is a table showing the contents of set status signals of an embodiment according to the present invention; FIG.5 is a table showing a case when the optional memory is set in a slot; FIG.6 is a memory mapping results table; is accompanying drawings. block diagram showing a device of an embodiment composition of and FIG.7 is a table of mapping results of another embodiment according to the present invention.

In this embodiment, the present invention is applied to a optional memory device.

A detailed description of the preferred embodiments of the present invention is given below, with reference to the appended drawings.

FIG.1 is a block diagram showing a composition of a main board of an optional memory device of an embodiment according to the present invention. The optional memory device of the present invention comprises a portion of a housing of a microcomputer, for example, provided with a portion that provides an optional memory. FIG.1 shows the case when a dynamic RAM (DRAM) is used as an optional memory in the above that portion. Accordingly a description of the CPU of the microcomputer itself will be omitted here.

The main board of the optional memory device of the present embodiment comprises a multiplexer 1, a DRAM controller 2, a resident RAM 3, and slots 4 - 7 for setting optional boards.

The multiplexer 1 selects the address information input from the CPU signal, and supplies one of the row address signal and the column b is address signal to the DRAM availabel in the slots 4 - 7; it also supplies to the multiplexer 1 the address switching signal (MUX) output from the DRAM controller 2. The DRAM controller 2 generates control signals using the signals output from the slots 4 - 7 and the CPU (not shown in the figure) so as to control the DRAM in the slots 4 - 7. The resident RAM 3 has two blocks of 0.5M bytes each and has a total capacity of 1M byte. The resident RAM 3 is always-provided in the device, so as to when there is no DRAM provided in the slots 4 - 7.

The address switching signal MUX from the DRAM controller 2, and the address information A1 A20 from the CPU are input to the multiplexer 1. The multiplexer 1 outputs either the row address signal or column address signal based on the signal MUX received. Furthermore, the signals DRAM 0 9 are output from the multiplexer 1 to the resident RAM 3 and the DRAM, which DRAM is provided in the slots 4 - 7.

The DRAM controller 2 generates the control signals RAS 0 - 9, CAS, OE, WR, and the address switching signal MUX, for controlling the DRAM using the control signal R/W (read/write), the AS (Address strove) signal, and DS output, which 6 signals are output from the CPU of the microcomputer.

FIG.2 shows a slot. As shown in FIG.2, the slots 4 - 7 for the optional RAM (DRAM) can each store an optional RAM, each having the pairs of blocks 21 and 22. The blocks 21 and 22 respectively comprise from four DRAM elements. The capacity of the optional memory is 0.5M byte when 1M byte DRAM is stored in one of the slots 4 - 7 and only one block is used; the capacity of the optional memory is IM byte when two blocks are used. The situation is similar in the case when 4M byte DRAM are used, with the capacity of the optional memory being 2M byte when one block is used, and 4M byte when two blocks are used.

The identification signals supplied from the slots 4 - 7 to the DRAM controller 2 are the SLOT signal, the 1M/4M signal, and the BLOCK signal. The optional RAM not shown in FIG.2. The signals DRAM 0 - 9 from the multiplexer 1, and the DRAM control signals from the DRAM controller 2 are input to the slots.

The SLOT signal indicates whether or not DRAM is set in at least one of the slots 4 -7. In the case of this embodiment, when the SLOT signal 1 7 is high level, it indicates that there is no DRAM provided in any slot. When the SLOT signal is low level, it indicates that there is DRAM provided in at least one slot because, as shown in FIG.2, the line of the SLOT is connected to ground and is pulled up on the side of the main board so that it becomes high level when there is no optional RAM board is not provided in any slot. For example, the SLOT signal outputs a low- level signal from the slot 5, when there is DRAM set in the slot 5.

The IM/4M signal indicates whether the capacity of the DRAM is 1M byte or 4M byte. The 1M/4M signal is high level when the capacity of a DRAM set in at least one of the slots 4 - 7 is 1M byte, and is low level when the capacity of a DRAM set in any of the slots 4 - 7 is 4M byte. For example, the IM/4M signal is a low-level signal from the slot 6, when the 4M byte DRAM is set in the slot 6.

The BLOCK signal 1/2 indicates the number of blocks used to provide DRAM in each slot. When the number of blocks of DRAM set in a slot is one, the BLOCK signal 1/2 is high level. When the number of blocks of DRAM set in the slot is two, the BLOCK signal 1/2 is low level. For example, the 1 2 BLOCK signal 1/2 outputs a low-level signal from slot 7, when the DRAM provided in slot 7 uses 2 blocks.

More specifically, when a DRAM has a 4M byte capacity and both of the blocks 21 and 22 are used, a jumper pin is ON and the BLOCK signal 1/2 and the 1M/4M signal become low level. In addition, when a IM byte DRAM capacity is provided, and only one of the blocks 21 and 22 is used, the jumper pin is OFF and the BLOCK 1/2 signal and the 1M/4M signal become high level. In this manner, the capacity of DRAM set in each slot is a maximum of 4M byte when the 4M byte DRAM uses two blocks. Therefore, the maximum capacity of the entire system becomes 17M byte when four DRAMs each 4M byte use 2 blocks in each of the slots 4 - 7.

The slots 4 - 7 directly output the SLOT signal A - D, the 1M/4M signal A - D, and the BLOCK signal 1/2 A - D to the DRAM controller 2.

As shown in FIG.3, the DRAM controller 2 has a decoder 31, a timing controller 32, and an RSA decoder 33. The decoder 31 is input address signals from the CPU. The decoder 31 decodes the address signals A19 - A24 input from the CPU of the microcomputer, and generates 64 areas of 0. 5M byte 1 q each. In the present embodiment, there is a maximum of 17M byte and so there are only 34 areas; they are signal areas 0 - 33. That is, the decoder 31 allocates the decoded address signals to the option memory of the slots 4 - 7. The decoder 31 outputs the signal-AREA 0 - 33 to the RAS decoder 33.

The signals AS, DS, R/W and REF from the CPU of the microcomputer are input to the timing controller 32, and the timing the signals CAS, OE and WR to the RAS in order to access the DRAM in accordance with a predetermined timing. In addition, signals AS, DS and R/W which comprise DRAM control signals, are output from the CPU of the microcomputer. Signals RAS, CAS, OE, and WR, which comprise DRAM control signals, are output from the timing control 32 of DRAM controller 2.

The RAS decoder 33 refers to the SLOT signals A - D, BLOCK signals 1/2 A D, and the 1M/4M signals A - D output from the slot side, and judges the capacity of DRAM being used in the slots 4 - 7.

The RAS decoder 33 receives slot data obtained by the SLOT signals A - D, the 1M/4M signals A - D and the BLOCK signals 1/2 A - D. The slot data is information concerning DRAM provided controller 32 outputs is in the slots. Then the RAS decoder 33 allocates the slot data on the signal-area made by the decoder 31. This process is called "mapping". Accordingly, the RAS decoder 33 makes a table, in this embodiment, as shown below.

The AREA signals 0 - 33 output from the decoder 31 and the RAS signals output from the timing controller 32 are input to the RAS decoder 33, which then generates the signals RAS 0 - RAS 9, which are DRAM control signals, and outputs them to the slot.

TABLE

SIGNAL-RAS SIGNAL-AREA RAS 4 AREA 0 3 RAS 5 AREA 4 7 RAS 6 AREA 8 11 RAS 8 AREA 12 18 RAS 9 AREA 14 15 RAS 0 AREA 16 17 RAS 1 AREA 18 19 FIG.4 is a table showing the contents of identification signals of an embodiment according to the present invention.

I i When the SLOT signal is high level, there is no DRAM set in the respective slot. When the SLOT signal is low level, a DRAM is set in the respective slot. Accordingly, in FIGA there is no DRAM set in the slot 3; the slot 3 is then set to resident RAM, the slots 4 - 7 are provided with DRAM.

When the 1M-4M signal is high level, i indicates that a 1M byte DRAM is set in the respective slot. When the 1M/4M signal is low level, it indicates that a 4M byte DRAM is set in the respective slot. Accordingly, FIG.4 shows that 1M byte DRAMs are set in slots 4, and 5, and that 4M byte DRAMs are set in the slots 6, and 7.

When the BLOCK signal 1/2 is high level, it indicates that a DRAM set in a slot uses one block.

When the BLOCK signal 1/2 is low level, it indicates that a DRAM set in the slot uses two blocks. Accordingly, in FIGA, there is one block of DRAM (i block= 0.5M byte) set in each of the slots 4 and 6.

The following is a description of the operation of a memory device having the composition described above.

The description is for the case of a first is 1 12- embodiment using the composition described above, and in which the SLOT signal, the 1M/4M signal and the BLOCK signal 1/2 are output from each of the slots.

In this case, DRAMs each using two blocks are set in slots 5 and 7, and a DRAM using one block is set in slot 6. Accordingly, in slot 5 is set 4M byte of DRAM, in slot 6 is set a 4M byte DRAM (using one block), and in slot 7 is set a 1M byte DRAM, and the resident RAM 3 which is set RAM of 1M byte. In this case, the total DRAM capacity is 8M byte.

FIG.5 shows the levels of each of the SLOT signals, the 1M/4M signal and the BLOCK signal 1/2 output from each slot. At this time, the slot 4 has no DRAM set in it, and so the level of all of the signals is high. Each SLOT signal, 1M/4M signal and BLOCK 1/2 signal is directly output from the slot side to the DRAM controller 2. The DRAM controller 2 uses each of these output signals as basis for the mapping.

FIG.6 is a table showing the mapping results. The mapping is performed by the RAS decoder of the DRAM controller 2. The left side addresses in the table of FIG.6 indicate addresses 13 allocated by the decoder 31. The right side blocks in the table of FIG-6 indicate the result of the mapping done by the RAS decoder 33. The "OUTPUT RAS" column in the table is the DRAM control signal output by the RAS decoder 33. This information of the table in FIG.6 is allocated as shown in the mapping of the RAS decoder 33 of DRAM controller 2.

Thus, DRAM controller 2 has continuously available 8M byte of continuous RAM in an area with addresses "0" to "7FFFFF". Thus, the DRAM controller 2 has access to 8M byte of continuous RAM in a region with address from 0 to 7FFFFF.

The following is a description of a second embodiment, for the case where, after a mapping has been made from the identification signals, there is a DRAM status change to an other status. Confirmation of the above signal then makes the DRAM status current and a new mapping is made.

The SLOT signal, the 1M/4M signal and the BLOCK 1/2 signal output from each of the slots is managed by a software. The signals are thus indirectly output to the DRAM controller 2.

First, the DRAM controller 2 sets the SLOT signals A - D, the 1M/4M signals A - D, and the BLOCK 1/2 signals A - D from the DRAM to the low is 1 is 14 level. Accordingly, the DRAM controller 2 selectS 17M byte as the maximum capacity available to the system.

FIG.7 shows the initial mapping results when the maximum capacity is selected. That is, the slot data corresponding to the identification signals output from the slot side at the initial state, is mapped.

After the initial mapping, the slot data from the DRAM that has been mapped by the DRAM controller 2 is confirmed by means of the software.

Thus the DRAM controller 2 can confirm the capacity of DRAM set in any of the slots 4 - 7.

Specifically, the contents of the SLOT signals, the 1M14M signal, and the BLOCK signals are verified by the software. The software then adjusts the values of the identification signals from the DRAM based on the results of the above confirmation.

For example, in the initial status, a 1M byte DRAM is set in slot 5, in the next status, a 4M byte DRAM is set in slot 5 instead of the 1M byte DRAM. The SLOT signal indicates that there is a DRAM board mounted in the slot, and the 1M/4M signal indicates that a 4M byte DRAM is set in the slot.

is Is The identification signals as adjusted by the software are sent to DRAM controller 2. The DRAM controller 2 uses the adjusted identification signals to perform a mapping once again, and to determine the continuous RAM area available as DRAM.

In addition, in this case, if there occurs a failure of the RAM there will be an error when confirmation is performed on these areas, thus skipping this area, during confirmation, and performing mapping enables a continuous RAM area to be obtained.

The methods of the first embodiment of the present invention enable a continuous storage area to be obtained without requiring operator awareness of capacities, positions or order of the setting of option memory such as DRAM or the like arbitrarily set in set slots.

In addition, according to a second embodiment, a DRAM controller can confirm all regions to which DRAM is able to be mounted, and by means of a software, adjust the identification signals (SLOT signals A - D, the 1M/4M signals A D, and the BLOCK 1/2 signals A - D and the like) so that the DRAM controller 2 does not select a block when there is no DRAM set and the DRAM controller 2 1 is 16 can therefore determine the continuous available storage area by means of mapping.

Further, the present invention is not limited to these embodiments and various variations and modifications may be made without departing from the scope of the present invention.

1 17

Claims (19)

WHAT WE CLAIM IS
1. An optional memory device additionally set to a main memory device, which a optional memory device has at least one of a plural number of memory means in a state such that said one memory means is mountable and demountable, the optional memory device comprising: an identification signal output portion, for outputting identification signals on the basis of types and capacities of at least one of a plural number of said memory means set in corresponding portions of said optional memory device, and a detection portion for detecting types and capacities of one or a plurality of said memory means, said detecting being made on the basis of said identification signals output from said identification signal output portion.
comprises continuous
2. The optional in claim 1, wherein said memory device as claimed detection portion allocation means for allocating a area of said memory means, and a first mapping means, for mapping an area allocated by said allocation means according to said Is identification signals supplied to the mapping means from said identification signal output portion, and for outputting to said identification signal output portion, access information for accessing said memory means according to results of said mapping.
3. The optional memory device as claimed in claim 2, wherein said allocation means decodes address signals input from said main memory device and generates, from said memory means settable in said identification signal output portion, an area comprising a required number of byte as a maximum capacity.
4. The optional memory device as claimed in claim 2, wherein said mapping means performs a mapping assignment of an area allocated by said allocation means in accordance with a level of said identification signals.
5. The optional memory device as claimed in claim 1, wherein said detection portion includes a second mapping means which refers to said mapped area and adjusts said identification signals input lq from said identification signal output portion if a memory means is a usable area, and uses said adjusted identification signal to output access information for accessing said memory means to said identification signal output portion.
6. The optional memory device as claimed in claim 5, wherein said second mapping means performs mapping of an area in accordance with a maximum capacity of said optional memory means as determined from said identification signals, writes contents of said identification signals corresponding to said area, reads said written data and refers to said data to adjust said is identification signals.
7. The optional memory device as claimed in claim 5, wherein said second mapping means assigns, in the mapping, adjusted values obtained from said identification signals by means of software.
8. The optional memory device as claimed in claim 1, wherein said identification signal includes a set confirmation signal which indicates 2-0 whether or not said memory means is set to said identification signal output portion.
9. The optional memory device as claimed in claim 8, wherein said set confirmation signal becomes low-level when said memory means is set to the said identification signal output portion, and becomes high-level when said memory means is not set to said identification signal output portion.
is
10. The optional memory device as claimed in claim 1, wherein said identification signal includes a capacity confirmation signal which indicates a capacity of said memory means set to said identification signal output portion.
11. The optional memory device as claimed in claim 10, wherein said capacity confirmation signal becomes high-level when a capacity of said memory means is 1M byte, and becomes low-level when a capacity of said memory means is 4M byte.
12. The optional memory device as claimed in claim 1, wherein said identification signal includes a block confirmation signal which 1 21 indicates a number of blocks comprised by said memory means set to said identification signal output portion.
13. The optional memory device as claimed in claim 12, wherein said block confirmation signal becomes high-level when said memory means uses one block, and becomes low-level when said memory means uses two blocks.
14. The optional memory device as claimed in claim 1, wherein said memory means includes a plurality of RAM elements.
15. The optional memory device as claimed in claim 1, wherein said memory means includes a plurality of RAM modules.
16. The optional memory device as claimed in claim 1, wherein said memory means includes a plurality of RAM boards.
17. The optional memory device as claimed in claim 1, wherein said memory means includes a combination of said RAM elements, said RAM modules 22and said RAM boards.
18. The optional memory device as claimed in claim 1, wherein said identification signal output portion includes slots which have some connecting means for setting said memory means.
19. The optional memory device substantially as hereinbefore described with reference to.the accompanying drawings.
is
GB9210225A 1991-05-13 1992-05-13 Optional memory. Withdrawn GB2255843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13534191A JPH04336347A (en) 1991-05-13 1991-05-13 Memory device

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GB2255843A true GB2255843A (en) 1992-11-18

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GB2271003A (en) * 1992-09-23 1994-03-30 Intel Corp High integration DRAM controller
GB2279781A (en) * 1993-07-10 1995-01-11 Ibm Defining topology of a data processing system
GB2295037A (en) * 1994-11-10 1996-05-15 Raymond Engineering Redundant array of solid state memory devices
EP0782076A1 (en) * 1995-12-29 1997-07-02 Siemens Aktiengesellschaft Arrangement for detecting the configuration of a memory
US6567904B1 (en) 1995-12-29 2003-05-20 Intel Corporation Method and apparatus for automatically detecting whether a memory unit location is unpopulated or populated with synchronous or asynchronous memory devices

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Cited By (10)

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Publication number Priority date Publication date Assignee Title
GB2271003A (en) * 1992-09-23 1994-03-30 Intel Corp High integration DRAM controller
US5307320A (en) * 1992-09-23 1994-04-26 Intel Corporation High integration DRAM controller
GB2271003B (en) * 1992-09-23 1996-02-14 Intel Corp High integration dram controller
GB2279781A (en) * 1993-07-10 1995-01-11 Ibm Defining topology of a data processing system
GB2295037A (en) * 1994-11-10 1996-05-15 Raymond Engineering Redundant array of solid state memory devices
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EP0782076A1 (en) * 1995-12-29 1997-07-02 Siemens Aktiengesellschaft Arrangement for detecting the configuration of a memory
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US6567904B1 (en) 1995-12-29 2003-05-20 Intel Corporation Method and apparatus for automatically detecting whether a memory unit location is unpopulated or populated with synchronous or asynchronous memory devices

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Publication number Publication date
DE4215486A1 (en) 1992-12-24
JPH04336347A (en) 1992-11-24
GB9210225D0 (en) 1992-07-01

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