KR100717273B1 - Processor device including backup cache memory and method for backup cache memory access thereof - Google Patents

Abstract

The present invention relates to a processor device having a backup cache memory and a method of accessing the backup cache memory thereof. The processor device disclosed herein is suitable for a computer system using a main memory device. The processor device has a processor core and a secondary cache memory and a backup cache memory. And between the processor core and the secondary cache memory and the backup cache memory to determine whether there is an abnormality in the secondary cache memory, and if the secondary cache memory has an abnormality in at least one specific area, the processor core is located in the specific area. And upon access, means for accessing a memory area corresponding to the specific area. This means stores mapping information for mutually allocating a specific area having an abnormality of the secondary cache memory and a memory area of the backup cache memory. Accordingly, when the processor core accesses a specific region having an abnormality of the secondary cache memory, the processor may access the allocated backup cache memory region by using the mapping information, thereby preventing a processor malfunction due to a failure of a portion of the secondary cache memory. .

Description

A processor device having a backup cache memory and a method of accessing the backup cache memory thereof, and a method for accessing the backup cache memory thereof.

1 and 2 are block diagrams showing a schematic configuration of a processor device having a secondary cache memory device;

3 and 4 are block diagrams showing a schematic configuration of a processor device according to the present invention;

5 is a block diagram showing a configuration of a processor device according to an embodiment of the present invention; And

6 is a flowchart illustrating an access procedure for using the backup cache memory of the processor device shown in FIG. 5.

Explanation of symbols on the main parts of the drawings

30, 40: processor unit

32, 42: processor core

34, 44: secondary cache memory

36, 46: backup cache memory

38: cache memory interface unit                 

50: main memory

The present invention relates to a processor device for a computer, and more particularly, to a processor device having a backup cache memory and a method of accessing the backup cache memory thereof.

In general, a processor device for a computer includes a primary (L1) cache memory provided in a processor core and a secondary (L2) cache memory provided in a processor device.

For example, an Intel Pentium 2 or 3 processor is manufactured in two types, a slot type and a socket type, both of which have secondary cache memory inside the processor device.

1 and 2, a slot type processor device 10 includes a processor core 12 and a secondary cache memory 14 on a PCB substrate 16. The socket type processor device 20 includes a secondary cache memory 24 inside the processor core 22.

These processor devices 10 and 20 are processor devices for computers, which are connected to main memory (not shown) to perform frequent memory accesses according to processor operation. The processor device 10, 20 therefore includes a cache memory between the processor cores 12, 22 and the main memory having an access speed faster than the main memory. In other words, since the processor apparatus 10 or 20 takes a long time for an interface for data access with the main memory, the processor apparatuses 10 and 20 have secondary cache memories 14 and 24 between the processor cores 12 and 22 and the main memory. When access is required, data is read from main memory and loaded into cache memory. Whenever necessary, data is accessed from the cache memory to handle data access in a short time. This is because cache memory access time is generally shorter than that of main memory.

However, in a general processor device, if a failure occurs in a portion of the cache memory, it may cause a malfunction of the processor device. To solve this problem, the performance of the processor device may be limited by limiting access to the cache memory and directly accessing the main memory. Lowers.

Disclosure of Invention An object of the present invention is to solve the above-described problem, and to implement a processor device having a backup cache memory used in response to an abnormality in a specific region of the cache memory in the processor device having a cache memory.

In addition, another object of the present invention is to solve the above-described problem, and to implement a method for using a backup cache memory corresponding to a specific region of the abnormal cache memory in the processor device having a backup cache memory.

According to one aspect of the present invention for achieving the above object, a processor device comprising: a processor core; Cache memory; A backup cache memory having a memory area that is mapped to a specific memory area of the cache memory; The processor core is disposed between the cache memory and the backup cache memory, and the processor core determines whether there is an error in at least one of the memory areas of the cache memory, so that the cache memory is located in at least one memory area. If there is a problem, the processor core includes means for accessing a memory area of the backup cache memory corresponding to the abnormal memory area when the processor core accesses the abnormal memory area.

In a preferred embodiment of this aspect, the cache memory is a secondary cache memory.

In a preferred embodiment of this aspect, the means stores the mutual mapping information for the memory area of the abnormality and the memory area of the backup cache memory.

According to another aspect of the present invention for achieving the above object, in the processor device having a backup cache memory having a processor core and a cache memory and a memory area that is mapped to a specific memory area of the cache memory, the backup cache memory A method of accessing a computer, the method comprising: initializing the processor device; Determining whether the cache memory has an abnormality in at least one specific area in the initializing step; Allocating a memory area corresponding to the specific area to the backup cache memory when the at least one specific area is abnormal as a result of the determination; Storing mutually allocated mapping information between the specific area and the memory area; Allowing the processor core to access the allocated memory region using the mapping information when the processor core accesses the specific region.

(Action)

Therefore, according to the present invention, the processor device determines whether there is an abnormal area among the memory areas of the cache memory through an initialization process. As a result of the determination, if there is at least one abnormal area, a specific area address of the backup cache memory is allocated corresponding to this area. A table containing these allocated mapping information is created and stored. Therefore, when the processor device accesses the cache memory and the region to be accessed and the region to be accessed is in the table, the processor device accesses the corresponding region of the backup cache memory according to the mapping information.

(Example)

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 and 4 illustrate processor devices according to the present invention.

Referring to FIG. 3, the processor device 30 is a slot type processor device for a computer. The processor device 30 includes a processor core 32, a secondary cache memory 34, and a new backup cache memory 36. In addition, the processor device 30 is electrically connected to the main memory 50 to perform data access according to the operation of the processor core 32.

The processor core 32 and the secondary and backup cache memories 34 and 36 are interconnected via a cache bus.

4, the processor device 40 is a socket type processor device for a computer, and includes a processor core 42, a secondary cache memory 44, and a new backup cache memory 44. The secondary and backup cache memories 44 and 46 are provided inside the processor core 42.

Thus, the processor devices 30, 40 allocate a memory area of the backup cache memory 36, 46 corresponding to the memory area in which at least one or more of the secondary cache memories 34, 44 are located.

Specifically, referring to FIG. 5, the processor device 30 (or 40) includes a new cache memory interface unit between the processor core 32, the secondary cache memory 34, and the backup cache memory 36. 38 is provided.

The cache memory interface 38 is connected to the processor core 32, the secondary cache memory 34, and the backup cache memory 36 through a cache bus. The cache memory interface 38 controls the processor core 32 to access the memory area of the backup cache memory 36 corresponding to the abnormal area of the secondary cache memory 34. The cache memory interface 38 may be configured to allocate at least one abnormal area of the secondary cache memory 34 and a memory area of the backup cache memory 36 under the control of the processor core 32. It includes a mapping information storage unit for storing the.

Therefore, when the power is supplied and reset, the processor device 30 is initialized through a self test. At this time, it is determined whether there is a failure among the memory areas of the secondary cache memory 34. As a result of the determination, if there is at least one abnormal region, an address is allocated to the specific region of the backup cache memory 36 corresponding to this region. A marking table including these allocated mapping information is created and stored in the mapping information storage unit. Therefore, when the processor device 30 accesses the secondary cache memory 34, if the marking table includes an area to be accessed by referring to the marking table, the corresponding area of the backup cache memory 36 according to mapping information. Access.

6 illustrates a procedure for accessing the backup cache memory of the processor device shown in FIG. 5. This procedure is a program processed by the processor core 32 or 42 or the cache memory interface 38.

Referring to the drawing, when the power of the processor device is initially reset in step S60, the processor device is initialized by performing a self test process in step S62. In step S64, it is determined whether there is an abnormality in the secondary cache memory during the self test process. If an abnormality occurs in a specific area of the secondary cache memory, the procedure proceeds to step S66 to allocate a memory area corresponding to the specific area having the abnormality in the backup cache memory. Subsequently, in step S68, a marking table including information in which the abnormal region and the allocated memory region are mapped is created and stored. If there is no specific region with abnormality in step S64, the procedure goes to step S70.                     

If the processor core accesses the secondary cache memory in step S70, the procedure goes to step S72 to determine whether it is an area included in the table. That is, it is determined whether the region of the secondary cache memory to be accessed is an abnormal region by using the marking table. As a result of the determination, if the specific area to be accessed is stored in the marking table, the procedure proceeds to step S74 to access the corresponding memory area of the backup cache memory corresponding to the specific area. If the result of the determination is not stored in the table, the procedure goes to step S76 to access the corresponding area of the secondary cache memory.

As described above, the present invention includes a secondary backup cache memory to be accessible in a processor device having a cache memory in response to a region in which there is an abnormality of the cache memory, and thus, even if a problem occurs in a portion of the cache memory of the processor device. Malfunction of the device can be prevented.

In addition, by accessing the cache memory for backup when the cache memory of the processor device mounted in the computer system is abnormal, the access speed can be improved and the system performance can be prevented from being lowered than using the main memory.

Therefore, it is possible to improve the reliability of the processor device due to the cache memory failure, thereby reducing consumer complaints and service costs due to the replacement of the processor device.

Claims (4)

In the processor unit: A processor core; Cache memory; A backup cache memory having a memory area that is mapped to a specific memory area of the cache memory; The processor core is disposed between the cache memory and the backup cache memory, and the processor core determines whether there is an error in at least one of the memory areas of the cache memory, so that the cache memory is located in at least one memory area. Means for accessing a memory region of the backup cache memory corresponding to the abnormal memory region when the processor core accesses the abnormal memory region. The method of claim 1, And the cache memory is a secondary cache memory. The method of claim 1, And the means stores the mutual mapping information for the abnormal memory area and the memory area of the backup cache memory. A processor device having a backup cache memory having a processor core and a cache memory and a memory area mapped to a specific memory area of the cache memory, the method comprising: accessing the backup cache memory: Initializing the processor device; Determining whether the cache memory has an abnormality in at least one specific area in the initializing step; Allocating a memory area corresponding to the specific area to the backup cache memory when the at least one specific area is abnormal as a result of the determination; Storing mutually allocated mapping information between the specific area and the memory area; And allowing the processor core to access the allocated memory area by using the mapping information when the processor core accesses the specific area.

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