WO2002056183A1

WO2002056183A1 - Semiconductor memory device and method for accessing the same

Info

Publication number: WO2002056183A1
Application number: PCT/KR2002/000045
Authority: WO
Inventors: Kyeong Man Ra
Original assignee: Flasys Corporation
Priority date: 2001-01-11
Filing date: 2002-01-11
Publication date: 2002-07-18
Also published as: KR20020060419A

Abstract

A semiconductor memory device and a method for accessing the same are disclosed, in which access to a memory is implemented through an information area, which contains a real address of the memory corresponding to an address to be accessed and its attribute, without directly inputting the address to the memory. The semiconductor memory device includes a memory area allowing access to corresponding information in accordance with input real memory address information, and an information area storing the real memory address information and outputting a real memory address corresponding to an input address to the memory area.

Description

SEMICONDUCTOR MEMORY DEVICE AND
METHOD FOR ACCESSING THE SAME
TECHNICAL FIELD
The present invention relates to a semiconductor memory device and a method for accessing the same, and more particularly to a semiconductor memory device and a method for accessing the same, in which access to a memory is implemented through an information area, which contains a real address of the memory corresponding to an address to be accessed and its attribute, without directly inputting the address to the memory.

BACKGROUND ART
If a memory block has a physical defect or a particular block needs a function such as a write protect function to safely keep data, the status of a corresponding physical (real) memory should be stored to access a corresponding address referring to the stored status.

A related art, US Patent No. 5,471,478 discloses a real memory divided into a plurality of blocks and an overhead area having no defect in each block. According to this related art, information of each block, such as data as to whether the block has a defect and electrical data required for operation, is written in the overhead area.

Another related arts, US Patents Nos. 5,987,563 and 5,966,720 disclose a real memory divided into a plurality of memory blocks, each block being divided into a plurality of sectors. Each sector is divided into a storage area and a data area so that a logical address of the sector is stored in the storage area and user information is stored in the data area. In this case, a method for accessing a semiconductor memory is as follows.

If a logical address of a desired sector is externally specified, the specified logical address is compared with a logical address stored in the storage area of each sector to search a consistent sector, thereby accessing the memory. However, a problem arises in that because the specified logical address should be compared with the stored logical address several times until the consistent sector is searched, the memory access time is not fixed.

Another related art, US Patent No. 5,200,959 discloses a memory divided into a user area and an information area so that an address of the user area having a defect and defect information are stored in the information area in a predetermined address order to skip the defective locations referring to the information area when a controller accesses the memory. This technique is useful only if addresses successively access the memory because defective areas are only written in the information area in the order of addresses. Also, when a defect occurs in another location during operation, a second information area should newly be generated to store the defective location and a type of the defect in the order of addresses.

Another related art, US Patent No. 5,353,256 discloses a technique in which one status register is assigned to each block so that access control data, defect data, and electrical data are written in the status register. A host system updates information of the status register whenever it accesses a memory. This technique individually manages the status of each block. Since an address is directly input to the block, the host system reads the status register to determine whether there is any defect block. If the defect block is not available, a problem arises in that the host system should assign a new address which will be substituted for the defect block.

Another related art, US Patent No. 5,974,500 discloses a method for storing access control data to each memory location in an information storage area. Another related art, US Patent No. 6,044,445 also discloses a method for controlling access to a particular block in accordance with access control data corresponding to each block in a memory. Another related arts, US Patents Nos.

4,796,235 and 5,083,293 disclose a write protect method for safely keeping stored data, the method being implemented in a circuit' (hardware) unlike the related arts,
US Patents Nos. 5,974,500 and 6,044,445. Since the technique according to the US Patents Nos. 4,796,235 and 5,083,293 is limited to adding an access control function or a write protect function to a particular memory block, it is applicable only if the memory is complete without any defect.

As described above, the related art memory device and the method for accessing the same have the following problems.

When a memory block is not available due to a physical defect or when an access control function or a data protect function is added to each memory block, a method for storing corresponding information in each block is used or an information area is separately provided to allow a controller or a host system to refer to the information area when it accesses a memory. In this case, if the accessed address has a physical defect, after the defect is detected by reading out information stored in the block, a new address of the accessed current address should be assigned from the system or another information area is required to store an address of another block which will substitute for the unavailable block. If the control data of each block is only written in the information area, it is difficult to solve the physical defect of the memory.

DISCLOSURE OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor memory device and a method accessing the same that substantially obviates one or more problems due to limitations and disadvantages of the related art.

An object of the present invention is to provide a semiconductor memory device and a method for accessing the same in which an address is not directly input to a memory but input to the memory through an information area, which respectively contains a real address (physical address) of the memory corresponding to an address to be accessed (logical address) and various information.

Another object of the present invention is to provide a semiconductor memory device and a method for accessing the same in which a particular function is not limited to a limited memory area but can be used in the whole memory area under the same conditions, so that a host system or a controller can access the memory area using a linear address space having individual attributes per logical address regardless of the status of a physical memory.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.

The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described'herein, a semiconductor memory device includes: a memory area allowing access to corresponding information in accordance with input real memory address information ; and an information area storing the real memory address information outputting a real memory address corresponding to an input address to the memory area.

In another aspect of the present invention, a semiconductor memory device includes: a memory area provided with a plurality of blocks allowing access to corresponding information in accordance with real block address information; an information area storing the real block address information and outputting a real block address corresponding to an input address; and a block address decoder selecting a corresponding block from the memory area in accordance with the real block address output from the information area.

In another aspect of the present invention, a semiconductor memory device includes: a memory area provided with a plurality of blocks allowing access to corresponding information in accordance with real sector address information, each block having a plurality of sectors; an information area storing the real sector address information and outputting a real sector address corresponding to an input address; and a sector address decoder selecting a corresponding sector from the memory area in accordance with the real sector address output from the information area.

In another aspect of the present invention, a semiconductor memory device includes: a memory area allowing access to corresponding information in accordance with input real memory address information; an information area storing the real memory address information and outputting a real memory address corresponding to an input address to the memory area, the information area being arranged in the same array as the memory area; an information decoder controlling the information area; and an address decoder controlling the memory area, wherein the real memory address information stored in the information area is input to the address decoder if the information decoder controls the information area, thereby allowing the address decoder to access the real memory address.

In another aspect of the present invention, a semiconductor memory device includes: a memory area allowing access to corresponding information in accordance with input real memory address information; an information area storing the real memory address information and outputting a real memory address corresponding to an input address to the memory area, the information area being arranged in the same array as the memory area; an address decoder controlling the memory area and the information area; and an address controller controlling the address decoder in accordance with an externally input address, wherein the address controller allows the real address information of the information area corresponding to the input address to be input to the address decoder, and the address decoder selects the memory area corresponding to the real address.

In another aspect of the present invention, a method for accessing a semiconductor memory device including a memory area allowing access to corresponding information in accordance with input real memory address information, and an information area storing the real memory address information and outputting a real memory address corresponding to an input address to the memory area, includes the steps of: storing a corresponding address in the information area if a test signal is input thereto; collecting information of each address of the memory area using the address stored in the information area; preparing real address information or composite information in the information area in accordance with the collected information; and writing the prepared information in a real address information area of the information area.

In another aspect of the present invention, a method for accessing a semiconductor memory device including a memory area allowing access to corresponding information in accordance with input real memory address information, an information area storing the real memory address information and outputting a real memory address corresponding to an input address to the memory area, an information address counter generating an address of the information area when collecting, preparing, and writing information of the memory area, a real address counter generating an available real memory address, a selection register outputting any one of output signals from the information address counter and the real address counter to the real memory address information, and an operational controller controlling the information address counter, the real address counter,

and the selection register so that the information area has a linear address space regardless of the status of the memory area, includes the steps of: a) writing an address for checking the status of the real memory address if a test signal is input; b) collecting information by testing each address of the memory area using the address stored in the information area; c) writing a currently selected real memory address in a real memory address area of the information area if an available address is collected while not writing the currently selected real memory address in the real memory address area of the information area if an unavailable address is collected.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

In the drawings:
FIG. 1 is a block diagram illustrating a basic structure of a semiconductor memory device according to the present invention;
FIG. 2 is a block diagram illustrating the basic structure of the present invention to which various flags and access password are added;
FIG. 3 is a block diagram illustrating a basic structure of an information area of FIG. 1;
FIG. 4 is a block diagram illustrating the information area having a real memory address only;
FIG. 5 is a block diagram illustrating the information area having a real memory address and various flag information;
FIG. 6 is a block diagram illustrating the information area having a real memory address, various flag information, and access password information;
FIG. 7 is a block diagram illustrating the memory area of FIG. 1 having a memory.

FIG. 8 is a block diagram illustrating the memory area of FIG. 1 having a set of same memories;
FIG. 9 is a block diagram illustrating the memory area of FIG. 1 having a set of different memories;
FIG. 10 is a block diagram illustrating the memory area of FIG. 1 having two or more sets of memories, each set including same memories;
FIG. 11 is a block diagram illustrating address information written in an information area of a tester or host system;
FIG. 12 is a block diagram illustrating address information and composite information such as various flag information and access password written in an information area of a tester or host system;
FIG. 13 is a flow chart illustrating a step of writing the information of FIGS. 11 and 12;

FIG. 14 is a block diagram illustrating address information written in an information area through a controller which controls the information area and the memory area;
FIG. 15 is a block diagram illustrating address information and composite information such as various flag information and access password written in an information area through a controller which controls the information area and the memory area;
FIG. 16 is a block diagram illustrating a controller which controls the written address information of FIG. 14;
FIG. 17 is a block diagram illustrating a controller which controls the address information, and composite information such as various flag information and access password of FIG. 15;
FIG. 18 is a flow chart illustrating a step of writing the information of FIGS. 14,15,16, and 17;

FIG. 19 is a block diagram illustrating a memory array having a plurality of memory blocks and an information area having a block address only;
FIG. 20 is a block diagram illustrating a memory array having a plurality of memory blocks and an information area having composite information;
FIG. 21 is a block diagram illustrating a memory array having a plurality of sectors and an information area having a sector address only;
FIG. 22 is a block diagram illustrating a memory array having a plurality of sectors and an information area having composite information;
FIG. 23 is a block diagram illustrating an information area and a memory in a memory array, an information decoder, and an address decoder;

FIG. 24 is a block diagram illustrating an information area and a memory in a memory array, a decoder which controls access to each area, and an address decoder which controls address information only, the information area having real address information only; and
FIG. 25 is a block diagram illustrating an information area and a memory in a memory array, a decoder which controls access to each area, and an address decoder which controls composite information such as address information and access password, the information area having composite information.

FIG. 26 is a drawing illustrating an information area and a real memory according to the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

A semiconductor memory device and a method for accessing the same according to the first embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a basic structure of a semiconductor memory device according to the first embodiment of the present invention.

Referring to FIG. 1, the semiconductor memory device according to the present invention includes an information area 10 and a memory area 20. The information area 10 respectively stores real memory addresses corresponding to each block of a real memory and outputs a real memory address in response to an externally input address signal.

The memory area 20 selects a corresponding area from the real address of the information area 10.

FIG. 2 is a block diagram illustrating a basic structure of a semiconductor memory device according to the second embodiment of the present invention.

Referring to FIG. 2, an access password signal as well as the address signal is input to the information area 10 so that the real address is output to the memory area 20 only if the input access password is identical to an access password stored in the information area 10 indicated by the input address signal, thereby accessing information stored in the memory area 20.

In the semiconductor memory devices according to the first and second embodiments of the present invention, the information area 10 may further include various flag information in addition to the address information. The flag information serves to control access to a corresponding address. Examples of the flag information include write protect, write permission, read protect, read permission, read% write protect, and read/write permission.

FIG. 3 is a block diagram illustrating a basic structure of the information area according to the present invention, FIG. 4 is a block diagram illustrating the information area having a real memory address only, FIG. 5 is a block diagram illustrating the information area having a real memory address and flag information, and FIG.

6 is a block diagram illustrating the information area having a real memory address, flag information, and access password.

In other words, as shown in FIG. 3, a unique area 100 is assigned to each of externally input addresses.

Information of a real memory corresponding to the input addresses is stored in the area 100.

The information of the real memory stored in the information area 10, as shown in FIG. 4, includes real memory addresses 110 only. In this case, when a real memory address is not available in an arbitrary location due to a defect of the real memory, a linear address space having no defect address can be used without using the real addresses having a defect.

Generally, if the memory area having no defect continues to operate, a defect occurs therein. When a defect address occurs in the memory area 20, a host system of the memory area 20 tests the memory-area 20 so that the real address information of the information area 10 is updated. As a result, the whole address space that is available is reduced as much as an-area of the defect address. However, the linear address space having no defect address can be provided in the available address space.

Furthermore, as shown in FIG. 5, if the address information stored in the information area 10 includes the real memory addresses 110 and flags 120, the flags 120 serve to control access to the memory area 20 corresponding to the real addresses 110. For example, the flags 120 include 2 bits, the first bit being assigned in a read control type and the second bit being assigned in a write control type. In this case, if a corresponding bit has a logic value of 1', it is defined as access permission'. If a corresponding bit has a logic value of 0', it is defined as no access'. If the two bits are 00', read/write protect is set for the address. If the two bits are 01', read is protected while write is permitted.

If the two bits are 10', read is permitted while write is protected. If the two bits are 11', read/write are permitted.

Although not shown, in the semiconductor memory device according to the present invention, as shown in FIG.

2, the address information stored in the information area 10 may further include real memory addresses and access passwords. In this case, an access password signal as well as the address signal is input to the information area 10 so that the real address is output to the memory area 20 only if the input access password is identical to an access password stored in the information area 10 indicated by the input address signal, thereby accessing information stored in the memory area 20.

Also, as shown in FIG. 6, if the address information stored in the information area 10 includes the real memory addresses 110, flags 120, and the access passwords 130, the access passwords 130 precede the flags 120. That is to say, although the flags 120 can be read and written, the access password 130 allows access to the real memory area 20 corresponding to an external input address only if the access password input when inputting the external input address is identical to the access password stored in the information area 10. The access password 130 serves as a safe device for information stored or to be stored in the memory area 20. The access password serves to not decode the password by reading out information but physically cut off access to information if the password is included in the information written in the memory area 20.

For example, the memory area 20 and the information area 10 are comprised of a nonvolatile memory, and information protected by a copyright is stored in the memory area 20. Then, different passwords 130 (or identical/or partially identical passwords) are input to each address in the information area 10 so that the host system can access the information stored in the memory area 20 only if the host system knows the access password of each address. In this case, if the host system (application program may be used actually) does not know the access password, access to the memory area 20 is cut off. Accordingly, it is more effective than a case where a complicated password is set in the information after access to the memory area 20 is permitted. In addition to this, if the password is set in the information, it is possible to more safely store the information.

In FIG. 6, the flags 120 may not be provided if access to the information stored in the memory area 20 is implemented with the access password 130 only.

FIGS. 7 to 10 illustrate examples of the memory area 20 of FIG. 1. As shown in FIG. 7, a DRAM device, an SRAM device, a FRAM device, a flash device, an EPROM device, an
EEPROM device or a memory array may be used as the memory area 20. One or more registers may be used as the memory area 20.

Furthermore, as shown in FIG. 8, a set of same memory devices or a set of same memory arrays may be used as the memory area. As shown in FIG. 9, a set of different memories may be used as the memory area. As shown in FIG.

10, two or more sets of memories may be used as the memory area, wherein each set includes same memories.

Although not shown, since the information area 10 is a memory that stores information, it is logically constructed as shown in FIGS. 3 to 6 but it is physically constructed in the same manner as the memory area 20 shown in FIGS. 7 to 10. Also, the information area 10 and the memory area 20 may exist in one memory device or one memory array.

FIG. 11 is a block diagram illustrating a method for writing address information in the information area 10 in accordance with one embodiment of the present invention,
FIG. 12 is a block diagram illustrating a method for writing address information in the information area 10 in accordance with another embodiment of the present invention, and FIG. 13 is a flow chart illustrating the operation of writing address information in the information area according to the present invention.

First, as shown in FIGS. 11 and 12, a tester or host system 30 (hereinafter, referred to as tester') is provided to check the status of the real memory area 20, collect memory status information, and store the collected information in the information area 10. That is, the tester 30 is connected with the information area 10 so that the tester inputs address and address information to the information area 10. The memory area 20 to which the real address output from the information area 10 is input is also connected with the tester 30 so that the status of the memory 20 corresponding to the input real address is sent to the tester 30.

Referring to FIG. 12, address information and composite information such as flags 120 or access passwords 130 are stored in the information area 10. The basic structure of FIG. 12 is identical to that of FIG. 11.

The composite information such as flags and access passwords to be stored in the information area 10 are input to the tester 30 and then written in the information area 10 of a corresponding address. The tester 30 checks the status of the memory area 20 in accordance with the test signal and writes the status of the memory area 20 in the information area 10. The test signal may be a test operation after the product is first manufactured, a system reset signal, or a power-up signal.

The method for writing the address information in the information area will be described with reference to FIG.

13.

As shown in FIG. 13, if there is no information written in the information area 10, no real address is input to the memory area 20. This results in that access to the memory area 20 becomes impossible. Accordingly, if the test signal is input to the memory area 20, an address is first written in the information area in step 50. The address physically exists in the memory area 20. The tester 30 inputs the address to the information area 10 and writes the current address in the real memory address area of the information area 10 selected by the address.

This operation is implemented for all the addresses existing in the memory area 20. Then, when the tester 30 accesses the memory area 20 through the information area 10, the address input to the information area 10 is identical to the address stored in the information area 10.

Accordingly, the operation is implemented in the same manner as that the address is directly written in the memory area 20 without through the information area 10.

If the address is written in the information area 10, the tester 30 can access the memory area 20 using the address. Accordingly, all the addresses existing in the memory area 20 are input and status information of the memory area for each address is collected in step 51. To collect the status information of the memory area, for example, previously prepared test data is written in the memory area 20 corresponding to the input address and is read again from the memory area 20, and then the read data is compared with original data, thereby checking whether the memory area¯20 has an error or defect.

After collecting the status information of the memory area 20, the real address information to be written in the address information area of the information area 10 is prepared in step 52. At this time, as shown in FIG. 12, composite information may be prepared by receiving extra control information such as flags and access passwords in step 52. Once the information is prepared, the information is written in the information area in step 53.

The steps of collecting, preparing, and writing the information of the memory area 20 are implemented for all the addresses by changing the addresses for each operation.

These steps may successively be implemented for the selected particular address.

Once the step of writing the information in the information area 10 ends, the physical status of the memory area 20 is protected by the information area 10.

Therefore, it is possible to externally access the memory area 20 through the information area 10 having the linear address space.

FIGS. 14 and 15 illustrate address information written in the information area 10 through a controller 31 which controls the information area and the memory area 20.

Referring to FIG. 14, the controller 31 is connected to the information area 10 so as to input addresses and address information to the information area 10. The controller 31 is also connected to the memory area 20 to which the real address output from the information area 10 is input, so that the status information of the memory area 20 for the input real address is sent to the controller 31. Referring to FIG. 15, the composite information, such as the flags 120 and the access passwords 130, as well as the address information is stored in the information area 10. The basic structure of
FIG. 15 is identical to that of FIG. 14. The composite information such as flags and access passwords to be written for each address is input to the controller 31.

Thus, the composite information is written in the information area 10 of a corresponding address. The controller 31 checks the status of the memory area 20 in accordance with the test signal and writes the status of the memory area 20 in the information area 10. The test signal may be a test operation after the product is first manufactured, a system reset signal, or a power-up signal.

FIGS. 16 and 17 are block diagrams illustrating the controller 31 of FIGS. 14 and 15. Referring to FIG. 16, the controller 31 controls writing of the address information. The controller 31 includes an information address counter 33 for generating a logical address when collecting, preparing, and writing the information of the memory area 20, a real address counter 34 for generating an available real physical address, an address selection register 35 connected to the information address counter 33 and the real address counter 34, for generating either the logical address or the real physical address as address information in accordance with the operation status, and an operational controller 32 connected with the information address counter 33, the real address counter 34, and the address selection register 35, for controlling the whole operation.

Referring to FIG. 17, the controller 31 controls writing of the composite information. The controller 31 of FIG. 17 is implemented in the same manner as that of FIG. 16 except that control information such as flag and access password are additionally input to the operational controller 32 so that corresponding composite information is written in the information area 10 through the information selection register 36.

FIG. 18 is a flow chart illustrating a step of writing the information of FIGS. 14 to 17. In the same manner as FIG. 13, if there is no information written in the information area 10, no real address is input to the memory area 20. This results in that access to the memory area 20 becomes impossible. Accordingly, if the test signal is input to the memory area 20, an address is first written in the information area 10. As shown in FIG. 18, the information address counter 33 is initiated in step 60.

The address output from the information address counter 33 is input to the information area 10 so that the information area 10 assigned to the first address is selected. The address selection register 35 outputs the output signal of the information address counter 33 as address information and writes the address information in the real memory addresses 110 of the information area 10 selected by the address in step 61. This operation is repeated for all the addresses in the memory area 20 so that the real memory address of the information area 10 becomes identical to the address input to the information area 10 in steps 62 and 63.

Once the address is written in the information area 10, the information address counter 33 and the real address counter 34 are initiated in steps 64 and 65. Then, the operational controller 32 inputs the first address indicated by the information address counter 33, i. e., the first real memory address 110 to the memory area 10.

Subsequently, the operational controller 32 tests the memory area 20 corresponding to the first real memory address so as to collect the status information of the memory area 20 in step 66. As a result, if it is determined that the address is available due to no defect in step 67, the real physical address of the currently selected memory should be written in the real memory address 110 indicated by the address of the information area 10. On the other hand, if it is determined that the address is unavailable due to a defect, the real memory address is not stored in the information area 20.

In other words, as shown in FIG. 26, it is assumed that arbitrary real memory addresses"a2"and"a4"have a defect as a result of the test. In this case, if the information address counter 33 and the real address counter 34 are initiated, the first address al of the real memory addresses is output and tested.

At this time, if the first address al is successfully tested without any defect or problem, the value"al"of the information address counter 34 is copied in the address (information) selection register 35, the value"al"of the real address counter 34 is copied in the information address counter 33, and the value"al"of the address (information) selection register 35 is stored in the information area 10 of the address"al"currently indicated by the information address counter 33, thereby storing the real memory address"al"in the address"al"of the information area 10. The value of the address (information) selection register 35 is copied in the value of the information address counter 33.

If the test of the first address"al"is completed, the information address counter 33 and the real address counter 34 are increased by 1 so as to test the second address"a2."
Since the second address"a2"has had a defect as a result of the test, the real address counter 34 is maintained as it is while the information address counter 33 is increased by 1, thereby testing the third address "a3."Since the third address"a3"has had no defect as a result of the test, the value"a3"of the information address counter 33 is copied in the address (information) selection register 35 and the value"a2"of the real address counter 34 is copied in the information address counter 33, so that the value"a2"of the information)

selection register 35 is stored in the information area 10 of the address"a2"currently indicated by the information address counter 33. The value"a3"of the address (information) selection register 35 is copied in the value of the information address counter 33.

If the test of the third address"a3"is completed, the information address counter 33 and the real address counter 34 are increased by 1 so as to test the fourth address"a4."That is, the information address counter outputs"a4"while the real address counter 34 outputs "a3."
Since the fourth address"a4"has had a defect as a result of the test, the information address counter 33 is increased by 1, thereby testing the fifth address"a5."
Since the fifth address"a5"has had no defect as a result of the test, the value"a5"of the information address counter 33 is copied in the address (information) selection register 35 and the value"a3"of the real address counter 34 is copied in the information address counter 33,

so that the value"a5"of the address (information) selection register 35 is stored in the information area 10 of the address"a3"currently indicated by the information address counter 33. The value"a5"of the address (information) selection register 35 is copied in the value of the information address counter 33.

The above operation is repeated until the last address is tested. The real memory address is stored in the information area in accordance with test result.

In other words, when the memory area 20 is tested by increasing counter by 1, an arbitrary address may be unavailable due to a defect. In this case, the information address counter 33 which indicates the real address of the memory area 20 skips the defective address to pass into the next address. The real address counter 34 increases counter only if the address has no defect. Accordingly, if the current address has no defect, the current address having no defect, i. e., the value of the information address counter 33 should be stored in the real memory address 110 of the information area 10 indicated by the real address counter 34 which successively counts the addresses having no defect.

FIGS. 19 and 20 illustrate the memory area 20 of FIG.

1 which includes a memory array 21 having a plurality of cell blocks 200, and a block address decoder 40 for selecting one block in the memory array 21.

Referring to FIG. 19, if an externally input address is input to the information area 10, the information area 10 outputs the real memory address 110 of the memory array 21 corresponding to the input address to the block address decoder 40. Then, the block address decoder 40 selects one block 200 corresponding to the address from the memory array 21.

Referring to FIG. 20, the real memory address 110 and various control information 130 are stored in the information area 10. To externally access the particular block 200 in the memory array 21, the block address and the access password should be input so that the information area 10 outputs an exact block address to access a desired block 200 of the memory array 21. In FIGS.

19 and 20, the information area 10 may be provided with various flag information 120 that control access to a corresponding address,'in addition to the address information 110. For example, examples of the flag information 120 include write protect, write permission, read protect, read permission, read/write protect, read/write permission.

In FIGS. 19 and 20, the memory array 21 may be a register, DRAM, or SRAM, which is a volatile memory. As shown in FIGS. 7 to 10, the memory area 20 may have one type memory or one or more types. In this case, different block address decoders 40 may be provided in each memory area 20. Also, the memory array 21 may be FRAM, EEPROM,
EPROM, or a flash memory, which is a nonvolatile memory.

The memory area 20 may be constructed in the same manner as the volatile memory. Also, the memory array 21 may be provided with a volatile memory and a nonvolatile memory.

Particularly, if the memory array 21 is a flash memory which is a nonvolatile memory, the block 200 includes cells which are erased at the same time.

FIGS. 21 and 22 illustrate the block 200 constituting the memory array 21 of FIGS. 19 and 20, which includes a plurality of sectors 210. In this case, a sector address is stored in the information area 10. Referring to FIGS.

21 and 22, if the memory array 21 includes a flash memory, the block 200 includes cells which are erased at the same time and the sector 210 includes a plurality of cells. The plurality of sectors 210 constitute one block 200.

Referring to FIG. 21, the information area 10 includes sector address information and/or access control flag information 120. Referring to FIG. 22, the information area 10 further includes the access password 130. The structure of FIGS. 21 and 22 is identical to that of FIGS.

19 and 20 except that the memory array 21 includes the sectors 210 and the block 200.

FIG. 23 is a block diagram illustrating the information area 10 and the memory area 20 in the memory array 21, an information decoder 42, and an address decoder 43. The information decoder 42 which controls the information area 10 is separated from the address decoder 43 which controls the memory area 20. If an external address is input to the information decoder 42, the information area 10 in the memory array 21 corresponding to the input address is selected by the information decoder 42 and the real memory address 110 stored in the selected information area 10 is output from the memory array 21 and input to the address decoder 43. The location of the memory area 20 in the memory array 21 corresponding to the real address 110 is selected by the address decoder 43 to access desired information.

The memory array 21, as shown in FIG. 19 or 20, may include the block 200 having a plurality of cells. Alternatively, the memory array 21, as shown in FIG. 21 or 22, may include the sectors 210 and the blocks 200.

FIG. 24 and FIG. 25 illustrate block diagrams in which the information area 10 and the memory area 20 are formed in one memory array 21, the address decoder 43 controls the memory area 20 and performs a function of the information decoder 42, and the address controller 44 is formed to control the operation.

The memory array 21 is divided into two areas, the information area 10 and the memory area 20. Referring to
FIG. 23, the information area 10 and the memory area 20 are physically divided even though the two areas 10 and 20 are formed in one memory array 21. Meanwhile, in FIG. 24 and FIG. 25, since the address decoder 43 is also used as the information decoder 42, the information area 10 and the memory area 20 are not physically divided, but logically divided.

Referring to FIG. 24, there is only real address information 110 in the information area 10, and the address controller 44 controls only address. If the address input for accessing the memory area 20 selects a corresponding location of the information area 10 through the address controller 44 and the address decoder 43, the real address information 110 stored in the information area 10 selected by the memory array 21 is read and sent to the address controller 44, and then accesses information of a desired location in the memory area 20 of the memory array 21 through the address decoder 43.

The information area 10 includes the flag information 120, access control information. When the information controller 44 reads the information area through the address decoder 43 by receiving the address from the address controller, if the flag information 120 is access protect, the address controller 44 does not transmit the real address 110 to the address decoder 43.

FIG. 25 is a block diagram illustrating a case in which composite information including an access password 130 is further stored'in the information area 10. To externally access the memory area 20, the address information and the access password should be input. Then, the address controller 44 compares the input access password with an access password 130 stored in the information area 10. If the input access password is identical to the access password stored in the information area 10, the address controller 44 outputs the real address information 110 to the address decoder 43, thereby controlling access to the memory area 20. The structure of
FIG. 25 is identical to that of FIG. 24 except for the above case.

Referring to FIG. 24 and FIG. 25, information showing whether the real memory address area identical to the current input address is available is stored in the flag 120 of the information area 10. If a value of the flag 120 is available, the input address is sent to the address decoder 43. If not so, a substitute address stored in the real memory address 110 of the information area 10 is sent to the address decoder 43, thereby accessing a desired portion of the memory area 20. In this case, only the flag 120 is written in the information area 10 storing the information of the memory area 20 having no defect, however, the real address information is not written in the information area 10. Also, the substitute address is written in the real address information 110 of the information area corresponding to the memory area having defect.

Accordingly, most of the memory area 20 can be used without any defect, thereby easily initiating the information area 10. Also, if a memory is added to the main memory array 22 like a case forming a redundancy memory to substitute for defects, a size of the address area is not decreased.

If the defect exceeds a capacity of the substitute memory, it is possible to obtain address continuity of the information area 10 for the defect generated in a predetermined address area, however, an available address area is decreased due to the defect.

INDUSTRIAL APPLICABILITY
As described above, the semiconductor memory device and the method for accessing the same according to the present invention have the following advantages.

Access to the address of the memory is implemented through the information area which stores various information of the real memory corresponding to the address for access. Accordingly, no additional circuit is required for a physical defect in the memory and a new logical function of the address in the memory. Also, since a particular function is not limited to a limited memory area but can be used in the whole memory area under the same conditions, the host system or the controller can access the memory area using a linear address space having no defect and having individual attributes per logical address regardless of the status of the physical memory.

While the present invention has been described and illustrated herein with reference to the preferred embodiments thereof, it'will be apparent to those skilled in the art that various modifications and variations can be made therein without departing from the spirit and scope of the invention. Thus, it is intended that the present invention covers the modifications and variations of this invention that come within the scope of the appended claims and their equivalents.

Claims

WHAT IS CLAIMED IS: 1. A semiconductor memory device comprising: a memory area allowing access to corresponding information in accordance with input real memory address information; and an information area storing the real memory address information outputting a real memory address corresponding to an input address to the memory area.

2. The semiconductor memory device of claim 1, wherein the information area is located inside or outside the memory area to be accessed.

3. The semiconductor memory device of claim 1, wherein real memory address information is a real memory address.

4. The semiconductor memory device of claim 1, wherein the real memory address information includes a real memory address and a flag for determining whether to allow access to the memory area.

5. The semiconductor memory device of claim 4, wherein the flag determines whether to allow reading of the memory area, its writing, or its reading/writing.

6. The semiconductor memory device of claim 1, wherein the real memory address information includes a real memory address, a flag for determining whether to allow access to the memory area, and/or an access password.

7. The semiconductor memory device of claim 1, wherein the memory area and the information area include one or more semiconductor memories.

8. The semiconductor memory device of claim 1, wherein the memory area includes a plurality of blocks, and erasure is implemented in each block unit.

9. The semiconductor memory device of claim 8, wherein each block is divided into a plurality of sectors.

10. The semiconductor memory device of claim 9, wherein the real memory address information includes either one of a block address and a sector address, or their combination.

11. The semiconductor memory device of claim 1, further comprising a controller which checks the status of the memory area and stores address and real memory address information in the information area in accordance with the checked result.

12. The semiconductor memory device of claim 11, wherein the flag or the access password is input to the controller, and the flag and the password are stored in the information area so that they are included in the real memory address information.

13. The semiconductor memory device of claim 11, wherein the controller includes: an information address counter generating an address of the information area when collecting, preparing, and writing information of the memory area ; a real address counter generating an available real memory address; a selection register outputting any one of output signals from the information address counter and the real address counter to the real memory address information; and an operational controller controlling the information address counter, the real address counter, and the selection register so that the information area has a linear address space regardless of the status of the memory area.

14. A semiconductor memory device comprising: a memory area provided with a plurality of blocks allowing access to corresponding information in accordance with real block address information; an information area storing the real block address information and outputting a real block address corresponding to an input address; and a block address decoder selecting a corresponding block from the memory area in accordance with the real block address output from the information area.

15. A semiconductor memory device comprising: a memory area provided with a plurality of blocks allowing access to corresponding information in accordance with real sector address information, each block having a plurality of sectors; an information area storing the real sector address information and outputting a real sector address corresponding to an input address; and a sector address decoder selecting a corresponding sector from the memory area in accordance with the real sector address output from the information area.

16. A semiconductor memory device comprising: a memory area allowing access to corresponding information in accordance with input real memory address information; an information area storing the real memory address information and outputting a real memory address corresponding to an input address to the memory area, the information area being arranged in the same array as the memory area; an information decoder controlling the information area; and an address decoder controlling the memory area, wherein the real memory address information stored in the information area is input to the address decoder if the information decoder controls the information area, thereby allowing the address decoder to access the real memory address.

17. A semiconductor memory device comprising: a memory area allowing access to corresponding information in accordance with input real memory address information; an information area storing the real memory address information and outputting a real memory address corresponding to an input address to the memory area, the information area being arranged in the same array as the memory area; an address decoder controlling the memory area and the information area; and an address controller controlling the address decoder in accordance with an externally input address, wherein the address controller allows the real address information of the information area corresponding to the input address to be input to the address decoder, and the address decoder selects the memory area corresponding to the real address.

18. A method for accessing a semiconductor memory device, the semiconductor memory device including a memory area allowing access to corresponding information in accordance with input real memory address information, and an information area storing the real memory address information and outputting a real memory address corresponding to an input address to the memory area, the method comprising the steps of: storing a corresponding address in the information area if a test signal is input thereto; collecting information of each address of the memory area using the address stored in the information area; preparing real address information or composite information in the information area in accordance with the collected information; and writing the prepared information in a real address information area of the information area.

19. The method of claim 18, wherein the composite information includes a flag and/or an access password.

20. The method of claim 19, wherein the flag and/or the access password controls access to the memory area indicated by an externally input address when accessing the memory area using the input address after the test signal is removed.

21. A method for accessing a semiconductor memory device, the semiconductor memory device including a memory area allowing access to corresponding information in accordance with input real memory address information, an information area storing the real memory address information and outputting a real memory address corresponding to an input address to the memory area, an information address counter generating an address of the information area when collecting, preparing, and writing information of the memory area, a real address counter generating an available real memory address, a selection register outputting any one of output signals from the information address counter and the real address counter to the real memory address information, and an operational controller controlling the information address counter, the real address counter,

and the selection register so that the information area has a linear address space regardless of the status of the memory area, the method comprising the steps of: a) writing an address for checking the status of the real memory address if a test signal is input; b) collecting information by testing each address of the memory area using the address stored in the information area; c) writing a currently selected real memory address in a real memory address area of the information area if an available address is collected while not writing the currently selected real'memory address in the real memory address area of the information area if an unavailable address is collected.

22. The method of claim 21, wherein the step a) includes the steps of: initiating the information address counter to a first address; copying a value of the information address counter in the real memory address area of the information area; and implementing the above steps for all the addresses.

23. The method of claim 21, wherein the step b) includes the steps of: initiating the information address counter and the real address counter to a first address; and outputting the real memory address indicated by the information address counter to the memory area to test the memory area and to collect status information of the memory area.

24. The method of claim 21, wherein the step c) includes the steps of: copying a value of the information address counter in the selection register if the available address is collected; copying a value of the real address counter in the information address counter; storing a value of the selection register in the information area of an address currently indicated by the information address counter; copying the selection register in the value of the information address counter; and maintaining the real address counter as it is while increasing the information address counter by 1 if the unavailable address is collected, thereby testing a next memory address.