JPH0845287A - Nonvolatile memory - Google Patents

Abstract

PURPOSE:To obtain the long service life of a memory as a result by enabling an uniform writing frequency while allowing the memory to have a management information corresponding to all stored data blocks one by one. CONSTITUTION:This memory is classified into a data area 11 consisting of plural blocks storing data in memories and an address area 12 managing the data area. The address area 12 has address storage memories corresponding to blocks one by one and stores management information of blocks and since it can operate the storage area of data and the storage area of address management information so that writing frequencies in them become uniform, service lives of internal nonvolatile media become all the same.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory such as a flash memory whose life depends on the number of times of writing to the memory,
In particular, the present invention relates to an address management method that enables a high-speed search while extending the service life.

[0002]

[Prior art]

(The closest known example to the invention) It is a non-volatile memory that retains the contents of data even when the power is turned off, and using a semiconductor memory that does not have a mechanical drive system instead of a video tape using a magnetic medium is a consumption. It is advantageous in terms of power and stability. In recent years, among such semiconductor memories, a flash memory has been attracting attention as a nonvolatile semiconductor memory that can be freely read and written and that retains data even when power supply is cut off. A flash memory is a reliable and stable storage medium without a mechanical drive unit compared to a hard disk, etc., but the number of writes to the memory is limited to about 100,000 times, and if writing is concentrated at the same position, overall There is a problem that the life of the product is shortened. In order to solve this, conventionally, in order to make the writing frequency uniform, the data area to be written is managed, and the management information is stored in the SRAM with a backup power source, a magnetic disk, or the like.

FIG. 10 shows a block diagram of a conventional nonvolatile memory. FIG. 10 shows a data area 101 for storing data,
It is composed of an address area 102 for managing the storage state. An SRAM, for example, is often used as the address area 102. By backing up this SRAM with a battery 103, the location of an active block is stored even when the power of a device using the nonvolatile memory is turned off. ing.

Further, by using a non-volatile memory as the address storage memory, the address management information can be stored without using a backup battery.

[0005]

In the nonvolatile memory using the SRAM as the address storage memory, since the address storage memory is composed of the SRAM with the backup battery, the backup battery is liable to be caused by vibration, contact failure or human error. Due to this, there is a problem of reliability in which the current is temporarily interrupted and the address management information is lost, and a problem of increase in cost due to addition of an interface circuit of a backup battery.

Further, in a non-volatile memory in which the address storage memory is composed of a non-volatile medium, writing concentrates on the address storage memory, and the life of the entire circuit becomes shorter depending on the life of the address storage memory.

An object of the present invention is to configure the address storage memory with a non-volatile medium and to extend the life of the non-volatile memory.

[0008]

[Means for Solving the Problems] A means for solving the above problems has an address storage memory in a number corresponding to all the addresses in a data area, and holds address management information of each block in the corresponding address storage memory. Is to do. FIG. 2 is a schematic diagram thereof.

The data area 21 is divided into a plurality of blocks (eight in the case of the figure) (this block is composed of a plurality of storage memories, and addresses are assigned to the blocks). Then, the latest data is always written with one of them as an active block. On the other hand, the address area 22 is divided into address storage memories corresponding to the blocks of the data area 21 in a one-to-one correspondence, and the address management information of the active block is stored in the address storage memory corresponding to the block. Remembered.

[0010]

According to the above management method, the data areas and the address areas operate so that the same write frequency is made uniform, so that the lifetimes of the internal nonvolatile media are all the same. Since the lifetime of the nonvolatile memory depends on the nonvolatile medium having the shortest life among the nonvolatile media, the nonvolatile memory managed by the above method has the longest life.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a non-volatile memory device according to the present invention is shown in FIG. The characteristic part of the present invention is a part surrounded by a dotted line in the drawing. The circuit of the first embodiment is functionally largely composed of three parts.

The first is a data area 11 for storing data.
Is. The data area 11 is composed of a plurality of blocks. Further, the block is composed of a plurality of storage memories. Addresses are assigned to blocks. The second is an address area 12 that manages the address of the data area 11. The third is a selector 13 for selecting a data bus for reading and writing. For simplicity, the number of management addresses is 8. Therefore, 11 is composed of eight blocks 111 to 118. Further, 12 is divided into an address storage memory 121 for storing address management information, and an address search circuit 4 for searching 121 to read the data area 11 and obtain a position of an active block for writing, and further stores in 121. Control signal lines 48 for sending the address management information to 4 to determine whether the address storage memories of the data lines 41, 121 read or write, address lines 45 for sending addresses from 4 to 121, and signals for controlling the selector 13. Consists of line 47. A functional diagram of a non-volatile memory using the device of FIG. 1 is shown in FIG. This memory is roughly divided into a data area 21 for storing input data and an address area 22 for managing the data area. Further, 21 is composed of a plurality of blocks which are the minimum units of access, and 22 is composed of an address storage memory for storing address management information of the 21 blocks.

Input data is written to the active block. (In this figure, the double circles represent the management information of the active block.) At the same time, the management information of that block is written to the corresponding address storage memory. When writing to one block is completed, the current block is closed, the address storage memory is searched, and the block to be written next is selected and activated. At this time, the block to be activated may be selected in any manner as long as it is selected so as to make the writing frequency of the blocks in the data area 21 uniform. The simplest method is to select the address search memory in order from the top, which is suitable for sequentially using the memory and storing data such as moving images.

Compared to the circuit shown in FIG. 10, this circuit has a simple structure because the circuit can be constituted by a single medium and there is no circuit part such as a backup power source.
As the number of blocks increases, the time required to search the address storage memory becomes a problem.

As a solution to this problem, the search time can be shortened by making the address storage memory a hierarchical structure.

As a modification of FIG. 1, a functional diagram of an apparatus that operates so as to shorten the search time of the address storage memory is shown in FIG. 3 below. This circuit includes a data area 31 for storing data in a memory and an address area 3 for managing the data area.
It is roughly divided into two. Further, 31 is composed of a plurality of blocks 311 and 32 is an address storage memory 321 for storing the address management information of the block 311 and corresponding to the block 311 on a one-to-one basis, and an upper layer address storage memory for managing the layers of 321. 322, and an upper layer address storage memory 323 for managing the layers of 322. (For simplicity, the hierarchical structure is a binary tree with 3 layers and the number of blocks is 8.
There is. 2. Similar to FIG. 2, the input data is written to the active block. At the same time, the management information of the block is written in the corresponding address storage memory. (In this figure, the double circles represent the management information of the active block.) When writing to one block is completed, the current block is closed, the address storage memory is searched, and then the writing is performed. Select the block to do and activate it. If the address storage memories are not hierarchical, the average search time becomes longer in proportion to the number of address storage memories. On the other hand, when the hierarchical structure is adopted, the average search time is proportional to the logarithm of the number of address storage memories. In general, memory capacity is increasing,
It is clear that the reduction of the search time by the above hierarchical structure is effective for the practical memory capacity.

Also in FIG. 3, the block to be activated may be selected in any manner as long as it is selected so as to make the writing frequency of the blocks in the data area 31 uniform.

A specific operation example in FIG. 1 will be described.
For the sake of simplicity, the rule is to activate blocks sequentially from the top, but basically, if the block write order is the same frequency for all blocks, by changing the configuration of the address search circuit Even if you can.

First, when inputting data in this circuit, it is necessary for 4 to obtain address management information of data to 11 from 121. FIG. 5 shows an example of the reading operation.
Here, the address management memory 51 and the address search circuit 5
2 corresponds to 121 and 4 in FIG.

In the operation 1, the content 511 of the 2-bit address memory of the first layer 51 is fetched into 52. Movement 2
Then, with the value of 511, the position of the memory address of the second layer to be searched next is fetched from the ROM. In this example,
Since only the bit before 511 is written, the address memory of the second layer to be searched next is 512 which is connected to the bit before 511 by a branch tree. In operation 3, 5
The contents of 12 are taken out to 52. In operation 4, the position of the memory address of the lowest layer to be searched next is fetched from the ROM. In this example, since the contents of 512 have already been written in both 2 bits, 513 which is connected to the bit after 512 by a branch tree is searched next. In operation 5, the contents of 513 are captured in 52. In the operation 6, the address for finally writing the data to 11 is fetched from the ROM according to the contents of 513. In this example, since the contents of 513 have already been written in both 2 bits, the adjacent 514 is the address to be searched. The address obtained as described above is sent to the selector 13, the data bus is selected, and the data is written in 11.

By the above operation, when the data is written in 11, it is necessary to write the address management information in the position 514 in 121 as well. In FIG. 6, 12
An example of the write operation to 1 will be shown. Here, the address management memory 61 and the address search circuit 62 correspond to 121 and 4 in FIG.

Since the position of the address memory to be written in 62 is known by the operation 6 in FIG. 5, it is used in the operation 1 in the operation 1 in 61 of the address memory 611 in the lowermost layer.
Is written to. Further, in operation 2, the position of the memory address of the second layer to be written is drawn from 62 from the address of 611. In this example, 612 connected to 611 by a branch tree is selected. In operation 3, the contents of 612 are pulled out to 62. In operation 4, since the contents of 612 have not been written, writing is performed to 612. (Note that if it has already been written, the write operation is ended here.) In operation 5, from address 612 to 62
Derive the location of the memory address of the layer to write. In this example, 613 connected to 612 by a branch tree is selected. In operation 6, the contents of 613 are pulled out to 62.
In operation 7, since the contents of 613 have not been written, 613
Write to. The operation ends when the upper layer is lost.

FIG. 4 shows a fifth configuration example 5 of the above-described operation.

The value of the address memory read from 121 passes through 41 and is sent to the write address search ROM 42 and the read address search ROM. The corresponding address is sent to the read / write selection circuit 44. The operation of 44 is determined by whether the operation of 4 is read or written. When the operation of 4 is reading to the address memory, the state of the memory of 121 is set to reading by the control signal 48, and the address indicated by 43 is output from 45. If the output is the lowest address of 121, it is sent to 13 by the output selection circuit 46. When the operation of 4 is writing to the address memory, 44 is 48
The memory state of 121 is set to write or read, and the address indicated by 42 is output to 45.

Next, regarding the reading of data in the present circuit shown in FIG. 1, the method of searching the read address may be performed by the method described in FIG. However, in the case of reading, it is necessary to see the address management information as to where the necessary data is stored. For example, when three different types of data are stored and it is desired to retrieve the data 2, it is necessary to remember the write position for each data in the address management information. This can be realized by devising the value of the address memory when writing data. FIG. 7 shows a configuration example of the address management memory.
In this example, the number of blocks to be managed is 8, and 3 bits are allocated to the address memory in the lowest layer. If different types of data 1, 2, and 3 are stored in this order in the data area, the data 1, 2, and 3 are stored in the address memory of the lowermost layer.
It is only necessary to allocate and write a bit that can distinguish the.

As described above, in FIG. 1, for simplification, the three-level binary tree and the number of addresses to be managed are eight. However, in general, the number of addresses to be managed is considerably larger than that (the storage capacity is 16 Mbit. In this case, the maximum number of addresses to be managed is 16M).

In the address area in which the number of blocks to be managed is N in the l-level a-branch tree (a> 1), the time t for searching an arbitrary address is the time for searching one level (1 for a addresses is 1). (Time to refer to each time) is the unit time,

[0028]

## EQU1 ## t = l = log (N) / log
(A) However, N is a to the 1st power.

On the other hand, if the management address has no hierarchical structure,

[0030]

## EQU00002 ## t = {1 + 2 + ... + (N / a)} /
(N / a) = (N + a) / 2a When the hierarchical structure is not adopted, the search time increases in proportion to the increase in N, but when the hierarchical structure is adopted, l
You only need to order og (N). For example, in the case of a binary tree,
When N is larger than 12, the search time in the hierarchical structure is advantageous. Considering a large-capacity memory, N is much larger than 12. Therefore, the search time is much more advantageous in the hierarchical structure.

Further, if the number of addresses referred to at one time is increased, that is, the number of branch trees is increased, the search time becomes shorter. Theoretically, if you have the same number of address memories as the number of blocks to manage, you can get the required address in one search.
The circuit scale increases in proportion to the number of managed blocks, which is not practical. On the contrary, if the minimum branch tree structure, that is, the binary tree is used, the circuit becomes light, but the search takes time. Therefore, it is advisable to select the number of branch trees according to the purpose of the memory to be configured.

Obviously, the following modifications are also included in the present invention.

Different media may be used as the nonvolatile media of the data area and the address management area. For example, an optical memory is used for the data area and a flash memory is used for the address management area. In this case, the optical memory can easily have a larger capacity than the flash memory, while the flash memory has a higher speed. Therefore, if these two types of nonvolatile media are combined, a faster and larger capacity nonvolatile memory can be obtained. Can be built.

In FIG. 1, the number of branch trees is a = 2 and the number of blocks is N = 8. However, these are 8 to the power of 2, and when the number of hierarchies is 1 = 3, blocks are managed efficiently. Because it was possible. Therefore, it is generally desirable to select N, a, and l such that N is a to the power of l. Also in this case, the same effect as the effect described in the first embodiment can be obtained.

Further, in FIG. 1, the block is explained as a group of a plurality of memories, but even if the block is physically distinguished as hardware, it is not distinguished as hardware, and a uniform memory is suitable. You may use what was divided by the number. Also in this case, the same effect as the effect described in the first embodiment can be obtained.

Also, in FIG. 2, the address storage memory can be divided and managed. FIG. 8 shows a modified example.
2 is different from the block 81 and the address storage memory 8 in FIG.
That is, another address storage memory 82 is placed between 3 and 3. Since the rewriting of 82 can be performed asynchronously with 81 and 83, it is effective when it is desired to change the writing order of blocks for some reason. FIG. 9 shows a circuit configuration example. The operation is almost the same as that of FIG. 1, but the signal from the address search circuit 922 points to the address of the pointer memory 923, and the content of the pointed 923 finally becomes the address of the block and is sent to the selector 94.

[0037]

By using the management system of the present invention for a non-volatile memory, the data area and the address area can be written in a uniform frequency so that the data area and the address area can be stored in a single memory such as a flash memory. It is possible to configure with only the storage medium, and it is possible to have a simpler and cheaper memory configuration than the conventional circuit having a backup power supply.

[Brief description of drawings]

FIG. 1 is a non-volatile memory according to the present invention.

FIG. 2 is a functional diagram of a first nonvolatile memory according to the present invention.

FIG. 3 is a functional diagram of a second nonvolatile memory according to the present invention.

FIG. 4 is an address search circuit diagram.

FIG. 5 is a diagram showing an example of a read operation.

FIG. 6 is a diagram showing an example of a write operation.

FIG. 7 is a diagram showing a configuration example of an address storage memory in an address area.

FIG. 8 is a functional diagram of a third nonvolatile memory according to the present invention.

9 is a configuration diagram of the nonvolatile memory in FIG.

FIG. 10 shows an example of a conventional nonvolatile memory.

[Explanation of symbols]

101 ... Data area, 102 ... Address area, 103 ...
Backup battery, 1 ... First embodiment of non-volatile memory according to the present invention, 11 ... Data area, 12 ... Address area, 121 ... Address storage memory, 4 ... Address search circuit.

Claims (1)

[Claims] 1. In a non-volatile memory whose life depends on the number of times data is written (erased), the memory is composed of a data area for writing data and an address area for managing the data area, and the data area is composed of a plurality of blocks. However, when an address is assigned to a plurality of blocks, the address area is configured by an address storage memory corresponding to the block and the address management information of the corresponding block is written to operate to write data. A non-volatile memory, characterized in that the writing frequency of the area and the address area is made uniform to extend the life of the memory.