JPH04336347A - Memory device - Google Patents

Abstract

PURPOSE:To obtain a continuous real storage area and to facilitate the extension of an option memory by confirming identification signals from identification signal output parts, which send out the identification signals, by a confirming circuit. CONSTITUTION:This memory device has a multiplexer 1, DRAM control 2, a resident RAM 3, and plural, for example, four slots 4-7 for option RAMs. The multiplexer 1 switches the address A1-20 between a row address and a column address with the address switching signal MUX sent from the DRAM control 2 and outputs address signals DRAMAs 0-9 for the resident RAM 3 and option RAMs. In this cases, the confirming circuit 2 recognizes the identification signals of the identification signal output parts 4-7 which send out the identification signals for discriminating the memory capacity and constitution of the plural storage means. Consequently, the mount state of the respective storage means are detected to obtain the continuous real storage area.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to memory devices such as controller boards of laser printers and microcomputers, and particularly to simplifying the addition of optional memory.

0002

[Prior Art] Conventionally, CPU, program code ROM
, RAM, and peripheral circuits, many microcomputer boards and printer controller boards are equipped with sockets or connectors for adding RAM to which option boards can be attached.

0003

SUMMARY OF THE INVENTION In such devices, the memory capacity of the option board to be installed is predetermined. For this reason, when the number of new applications increases and the memory capacity that must be used increases, the memory capacity may become insufficient. In this case, the application could not be used, or the main board had to be rebuilt.

The present invention has been made to deal with such a case, and aims to provide a memory device that allows applications to be used simply by adding optional memory even when a large memory capacity is used. This is the purpose.

[0005]

[Means for Solving the Problems] A memory device according to the present invention is a memory device in which a plurality of storage means are detachably attached, and includes an identification signal output section that sends out an identification signal to distinguish the memory capacity and configuration of each storage means. , and a confirmation circuit that recognizes the identification signal from the identification signal output section and detects the mounting state of each storage means.

[0006] It is also preferable to have means for checking the entire area in which the storage means can be installed, determining whether the storage means can be used or not, and changing the identification signal sent to the confirmation circuit. The storage means may be a RAM element, a RAM module, a RAM board, or a combination thereof.

[0007]

[Operation] In the present invention, by recognizing the identification signal from the identification signal output unit that sends out an identification signal that distinguishes the memory capacity and configuration of each storage means, the storage means can be identified by the order of installation, position, capacity, etc. Even if the device is attached without being aware of the storage means, the mounting state of each storage means is detected and a continuous real storage area is obtained.

[0008] Furthermore, by checking the entire area in which the storage means can be installed, determining whether the storage means can be used or not, and changing the identification signal sent to the confirmation circuit, continuous blocks can be stored excluding unusable blocks. Get real storage area.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention. This embodiment shows a case where a dynamic RAM (DRAM) is used as the expansion memory. As shown, the memory device has a multiplexer 1, a DRAM control 2, a resident RAM 3 and slots 4-7 for a plurality of optional RAMs, for example four.

The multiplexer 1 switches addresses A1-20 between row addresses and column addresses by an address switching signal MUX sent from the DRAM controller 2, and outputs address signals DRAMA0-9 for the resident RAM 3 and option RAM. The DRAM controller 2 receives address signals A19 to A24, a signal REF for refreshing the DRAM, control signals R/W, AS, and DS from the CPU (not shown), and slots 4 to 7 for option RAM. Signals sent SLOTA~D, IM/
4MA-D, BLOCK1/2A-D, signals RAS0-9, CAS, OE, WR for controlling DRAM
and generates an address switching signal MUX. Resident RA
M3 has two blocks each having a capacity of 0.5 Mbytes, and has a total capacity of 1 Mbytes.

[0011] Slots 4 to 7 for option RAM are
A board having two sets of blocks 21, 22, each shown in FIG. 2, can be mounted. Each block 2
1 and 22 are each composed of four DRAM elements.

Signal SL on this option RAM board
OTA~D are connected to ground and pulled up on the main board side, so the optional RAM board
High level when the cord is not connected. Signals 1M/4M and signals BLOCK1/2 are connected to the ground through jumper pins, and the pins can be attached or removed depending on the mounting situation on the option RAM board. Specifically, jumper pins are attached when a 4Mbit chip is used and when both blocks 21 and 22 are used, and when a 1Mbit chip is used and blocks 21 and 22 are used. The jumper pin is removed when only one is used. In this way, when 4 Mbit DRAM is mounted in two blocks, the maximum capacity is reached, and the capacity is 4 bytes. The system as a whole has a maximum capacity of 17 bytes when four optional RAM boards each having two blocks of 4 Mbit DRAM are installed.

Signal SLOT from these slots 4 to 7
A to D, signals 1M/4MA to D and signal BLOCK1
/2 is sent directly to DRAM control 2. Signals SLOTA~D indicate whether or not an optional RAM board is installed, and signals 1M/4MA~D indicate whether the optional RAM board is installed.
Indicates whether the RAM chip is 1Mbit or 4Mbit. Also, option R connected with signal BLOCK1/2
The block of DRAM used in the AM board is shown.

The DRAM controller 2 has a decoder 31, a timing controller 32, and an RSA decoder 33, as shown in FIG. The decoder 31 creates 64 areas of 0.5 Mbytes by decoding the input address signals A19-24. In this embodiment, since the maximum is 17 Mbytes, 34 areas are used, and the signals are AREA0 to AREA33. timing control 3
2 is the refresh signal REF and the signal A from the CPU
Signals RAS, CAS, OE, and WR for accessing the DRAM are generated from S, DS, and R/W. RSA deco
33 is a signal SL sent from the option RAM board.
OTA~D, signal 1M/4MA~D and signal BLOC
Based on K1/2, it is determined how much capacity each of slots 4 to 7 of the option RAM should use. The capacity and the number of areas used when these are combined are shown in the explanatory diagram of FIG. These signals and signals RAS and signals AREA0 to 3
3 to generate signals RAS0 to RAS9.

In the memory device configured as described above, the slots 5 and 7 are divided into two blocks, as shown in FIG.
In slot 6, the operation when an option RAM is mounted in one block will be explained. In this case, the total capacity of the DRAM is 8 Mbytes. Signals SLOT, signals 1M/4M and signals BL output from the option RAM board
The levels of each OCK1/2 signal are shown in FIG. At this time, since no DRAM is mounted in slot 4, the levels of all signals are high due to the pull-up of the main board. These signals SLOT
, signal 1M/4M and signal BLOCK1/2 are directly DR
It is sent to AM controller 2. The DRAM controller 2 performs mapping based on each signal sent. The mapped results are shown in FIG. As shown in FIG. 6, a RAM area of 8 Mbytes can be obtained continuously from address 0 to 7FFFFF.

[0016] Note that the above embodiment uses an optional RAM board.
The case where the signal SLOT, signal 1M/4M, and signal BLOCK1/2 output from the DRAM controller 2 are sent directly to the DRAM controller 2 has been explained, but the signal SLOT, signal 1M/4M
The usable area may be confirmed from the signals BLOCK1/BLOCK1/2, and these identification signals may be changed based on the confirmed results.

In this case, the signals SLOT, 1M/4M and BLO output from the option RAM board
These signals are sent indirectly to the DRAM controller 2 in order to manage CK1/2 by software. Then, first, signals SLOTA~D, signals 1M/4MA~D
and all signals BLOCK1/2A to D are set to low level. By doing this, it is possible to select 17 Mbytes, which is the maximum possible capacity for this system. Figure 7 shows an example of the first mapping at this time.
Shown below. By writing data to all areas in this state and reading and confirming the written data, it can be determined which capacity of the optional RAM board is mounted in slots 4 to 7. Based on the result, the signal SLOTA
~D, signal 1M/4MA~D and signal BLOCK1/2
Reset the values of A to D. The changed identification signal is then sent to the DRAM controller 2 and mapped to obtain a continuous RAM area. Additionally, in this case, even if there is a faulty RAM, an error will occur when checking for writing/reading in that area, so by mapping and skipping that area, a continuous RAM area can be obtained. .

Although the above embodiments have been explained using DRAM, static RAM (SRAM) is also used.
A similar effect can be obtained when using M).

[0019]

Effects of the Invention As explained above, the present invention allows the storage means to be installed by recognizing the identification signal from the identification signal output unit that sends out the identification signal for distinguishing the memory capacity and configuration of each storage means using the confirmation circuit. Even if you do not pay attention to the order, position, capacity, etc. of
Since a continuous real storage area can be obtained, memory can be easily expanded.

[0020] Furthermore, by checking the entire area in which the storage means can be installed, determining whether the storage means can be used or not, and changing the identification signal sent to the confirmation circuit, blocks that are determined to be unmounted or unusable can be checked. If there is, it is possible to set consecutive addresses without selecting that block, allowing effective use of memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the invention.

FIG. 2 is a block diagram showing slots in the above embodiment.

FIG. 3 is a block diagram showing DRAN control in the above embodiment.

FIG. 4 is an explanatory diagram showing the capacity and the number of areas used.

FIG. 5 is an explanatory diagram showing the mounting state of slots.

FIG. 6 is an explanatory diagram showing mapping results.

FIG. 7 is an explanatory diagram showing mapping results in another example.

[Explanation of symbols]

1 Multiplexer 2 DRAM control 3 Resident RAM 4 Slots 5 Slot 6 slots 7 Slot

Claims (6)

[Claims] 1. A memory device having a plurality of removable storage means, comprising: an identification signal output section that sends out an identification signal that distinguishes the memory capacity and configuration of each storage means; and an identification signal output section that recognizes the identification signal from the identification signal output section. and a confirmation circuit for detecting the mounting state of each storage means. 2. The memory device according to claim 1, further comprising means for confirming the entire mountable area of the storage means, determining whether the storage means can be used or not, and changing an identification signal sent to the confirmation circuit. . 3. A memory device according to claim 1, wherein said storage means comprises a RAM element. 4. A memory device according to claim 1, wherein said storage means comprises a RAM module. 5. A memory device according to claim 1, wherein said storage means comprises a RAM board. 6. A memory device according to claim 1, wherein said storage means comprises a combination of a RAM element, a RAM module and a RAM board.