SU1628064A1 - Addressing device - Google Patents

Abstract

The invention relates to computing technology, can be used in the construction of computer memory systems, and allows for expanding the functionality by ensuring the virtual mapping of virtual pages to physical ones. The device contains a block of 2 dual-port operational chi, a register of 3 addresses and a selector of 4 addresses. Through the first address input of block 2, the virtual address is converted to a physical one, in which the number of the physical page is assigned to the virtual page number specified by the higher-order bit of the virtual address. Through the second address input of block 2, the recording of the number of active physical pages is made. 4 il. with s

Description

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The invention relates to computing and can be used in the construction of computer memory systems.

The purpose of the invention is to expand the functionality by providing an arbitrary mapping of virtual pages to physical.

FIG. I presents the functional diagram of the proposed device; Fig. 2 illustrates the algorithm of the memory selector; FIG. 3 is a functional block diagram of a dual-port one memory; 4 shows an example of mapping virtual address spaces onto physical space.

The addressing device contains the address input 1 of block 2 of dual-port RAM, register 3 addresses, address selector 4, input 5 of the virtual page, output 6 of the physical page, input 7 of data, input 8 of synchronization and entry 9 of write resolution .

Block 2 contains a buffer register 10, a multiplexer 11 and an asynchronous operational storage node 12.

The device works as follows.

First, the numbers of the required physical pages are recorded, for which an address is supplied to the address input 1 of the device, and an exchange synchronization signal (SYNC) is fed to the input 8, at which the address selector 4 (figure 1) in accordance with its work algorithm (figure 2) records the fact of access to block 2 in its internal trigger (T); address register 3 fixes the lower bits of the addresses that are fed to the second address input (A2) of block 2; after that, the information about the number of the required physical boundary and the input 9 is turned on Recording (DOUT), according to which the address selector 4 in accordance with the algorithm of its operation generates recording resolution signals (W), the recording resolution signal (W) causes the recording of information on the second address input of block 2. Removed the recording and synchronization signals exchange, the address selector 4 goes to the initial state. Thus, Ipolchu N write cycles (N defined

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5) by the number of low-order bits (P) of the address,), it is possible to fill in block 2 with the required values of the number of physical pages. This completes the preparatory stage of the device operation.

When the device works with address expansion, input 5 receives information specifying the virtual page number that goes to the first address input of block 2. Since the address selector 4 waits for the exchange synchronization signal and does not generate a write enable signal, block 2 operates in read mode and outputs to D1 information corresponding to the number of the physical page, i.e. The virtual address is converted to physical.

Consider an example of mapping virtual address spaces to physical (Fig. 4). There are two different virtual address spaces (1 and 2) corresponding to different tasks that map to the same physical address space.

The ordered pages (0,1,2 ..,) of the first virtual address space are mapped into disordered pages (0.5,7,. O.2 ...) of the physical address space, i.e. fragmented (consisting of alternating randomly occupied and free pages physical address space can correspond to a continuous virtual address space, which facilitates memory allocation and leads to its more rational use.

In addition, some physical pages (e.g., null 0- and K-) may be common to tasks performed in different virtual address spaces.

Through these pages, tasks can exchange data.

Since the mapping shown in the example may change during the execution of tasks, these tasks can access memory having a larger volume than the virtual address space (which has a fixed size depending on the size of the virtual address).

Thus, in the proposed device, the possibilities of data exchange between tasks are increased and the distribution flexibility is increased.

Lenip memory by ensuring the switchability of the memory as a whole when splitting it into several independently displayed pages. At the same time, as in the prototype, the address space is expanded.

The size of the achieved positive effect depends on the ratio of the number of higher and lower racs when virtually dividing the address into two parts, when the high-order bits define the virtual page number, and the low-order ones are inside the address, and from the block size 2a. the proportion of older air traffic pages that mark the virtual page number increases the total number of independently displayed virtual pages while decreasing the size of individual pages, which leads to an increase in the storage memory bandwidth. However, with the age of the virtual number of virtual pages, the required capacity of unit 2 increases exponentially, which increases hardware costs. In addition, the overhead costs associated with the entry in block 2 of initial information when switching virtual address spaces increase. Therefore, when determining the 30 pages of the device, and not Jiopnai, if the required number of virtual pages is selected, some optimum should be achieved depending on the specific tasks being solved. In the illustrated embodiment, the virtual address space is divided into 16 pages.

The width of block 2 affects the degree of expansion of the address space. At the same time, the minimum number of bits of the dual-port memory block, at which the address space expands, is defined as XR (ID M- | -1, where M is the number of most significant bits of the virtual address specifying the virtual page number.

The maximum bit size of a two-port memory is equal to the size of the data sent out by the processor to a bit.

With a maximum razridg of eg-i k, the maximum will be given a glim.i effect from the rhenium point of raggyrpa rat-ml-iH with a slight increase in equipment

Formula Iobr

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us; input - data / ohm of the device data, information format of the register a: rgsa is the input of the lower rpch, device address ids, the register register register is connected to the first address block of the two port memory, the address selector is connected to the control register of the address register and is the synchronization input of the device exchange, the control input of the address selector is the write enable input of the device, and the control output of the address selector is connected to the write / read enable input of the two-port block th random access memory.

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Claims (1)

Claim Device dg; .. destination ”·, containing an address selector, the information input of which is the input of the upper digits of the device address, with the fact that, in order to expand the functionality by ensuring the permissibility: ”On the mapping of virtual straps to physical ones, a two-ready RAM block and an address register are introduced into it, the first address input of the dual-port random access memory block being the input of the device’s virtual page number, and the information output the output of the financial number. oh art the device’s name, but the mon form .. the ion input is the device data input, the address register information input is the low-order address of the device address, the register output is. address is connected to the second address input of the dual-port random access memory unit, the address selector enable input is connected to the control into the address register and is the synchronization input of the device’s exchange, the control input of the address selector is the write enable input of the device, and the control output of the address selector is connected to the read-write block dual-port · RAM. Figure 2 Fig.Z Physical Fie 4