JPS63133234A - Microcomputer - Google Patents

Abstract

PURPOSE:To perform a highly effective test with a microcomputer even though a bus line is not led outside by providing a circuit into the microcomputer to compress and stored a bit of information on a data bus or an address bus. CONSTITUTION:When a CPU 1 receives an instruction for a test via a data line 9, the CPU 1 sets a CRC arithmetic register 10 under an initial state to be a workable state. Then the CPU 1 carries out the instructed test and stops the operation of the register 10 to read out the contents of the register 10. The contents of the register 10 and the test result are transmitted via the line 9. In such a way of the test, the information on a data bus 6 under a test can be obtained in the form of the compressed information. Furthermore an address bus 5 is available as the input of the register 10 and both buses 5 and 6 are also available. Thus it is possible to perform a highly effective test even though the bus line is not led outside.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to one-chip microcomputers, and particularly to improvements to increase the ease of testing thereof.

[Conventional technology]

Figure 2 is a block diagram showing an example of a conventional microcomputer.
1) is the central processing unit (C!PU) that performs all processing.
), (2) is a read-only memory (ROl, J) that stores the program executed by OP U (1), (3) is OP
(4) is the input/output unit (Ilo) that communicates with the outside, (5) is the CPU (1) is the ROM + 2). , an address bus that selects RAM (31 or Ilo (4)) and sends address information that specifies data therein; (6) is address information sent by CPU (1) via address bus (5); The data bus (7) on which the specified data is carried is whether the data on the data bus (6) is sent from cP U (t) to RAM (3) or IROM (2).
, from RAM (31 or Ilo (4) (:!P
A read/write (R/W) signal bus that indicates the direction of data being sent to U (11), and (8) a timing signal bus that supplies timing signals ψ when reading and writing data via the data bus (6). , (9) are data lines for communicating with the outside.

The operation of this conventional microcomputer is obvious from the above explanation of the configuration, so the explanation will be omitted. It is necessary to confirm that the correct address is on the data bus (6) and that the correct data is on the data bus (6). 5) and the data bus (6) are not exposed to the outside, the data cannot be confirmed, so the status of all memories must be read and confirmed. Therefore, there was a problem that the test efficiency was extremely low. This invention was made to solve the above-mentioned problem and waste, and it is possible to check the information on the internal bus line without exposing the bus line to the outside. The aim is to obtain a microcontroller configuration with high test efficiency.

[Means to resolve the problem]

The microcomputer according to the present invention is provided with an ORC operation register that compresses and stores information on internal bus lines.

[Effect]

The microcomputer of this invention compresses and stores internal bus line information in the ORC operation register according to instructions from the CPU.
It can be read and checked as needed.

[Embodiments of the invention]

FIG. 1 is a block diagram showing an embodiment of the present invention, and the same reference numerals as in the conventional example of FIG. 2 indicate equivalent parts to avoid duplication of explanation. In FIG. 1, Oe receives information from the data bus (6) using the timing signal ψ of the timing signal bus (8), compresses it, and stores it in an ORC calculation register, ul) of the CPU (i). Based on the instructions, initial state setting, operation/stop, O
This is a control circuit that issues instructions such as reading out the contents of the RO calculation register itself.

This embodiment configured as described above operates as follows during testing.

(() CPU (1) receives test instructions through data line (9).

(b) 0PU(1) sets the initial state of the ORC calculation register 0■ and makes it ready for operation.

(c) OP U (11 executes the instructed test.

CPU (1) stops the ORC operation register (10) and reads its contents.

(e) OP U (11 is through the data line (9),
The test result and the contents of the read CRC calculation register a are sent.

By testing as described above, the information on the data bus (6) under test can be obtained as compressed information.

Furthermore, the address bus (5) can also be used as an input to the ORC calculation register 00, and both of the above buses (
5) and (6) can also be used. Therefore,
Unlike the conventional example, it is no longer necessary to check all data by reading it, making it possible to improve the efficiency of testing.

In addition, in the conventional example, only the calculation results are known, but in this embodiment, information in the middle can also be extracted, and since it is compressed, the failure detection rate is high.

〔Effect of the invention〕

As explained above, the microcontroller according to the present invention has an internal circuit (CRO operation circuit) that compresses and stores information on the data bus, address bus, or both, so the bus does not go outside. It also enables efficient testing and improves the failure detection rate. Therefore, it is suitable for IC card microcontrollers that cannot take out the bus to the outside.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional microcomputer. In the figure, (5) is an address bus line, (6) is a data bus line, α is a CRC calculation circuit (a circuit for compressing and storing information), and (b) is a control circuit. In addition, the same reference numerals in the figures indicate the same or corresponding parts. Indication of the case Patent application No. 61-281353 2, name of the invention Microcomputer 3, person making the amendment Relationship to the case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (60
1) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Postal code 532 Address Shin-Osaka Yachiyo Building 5, 4-1-45 Miyahara, Yodoyou-ku, Osaka City Drawings subject to amendment (Fig. 1) 6. Amendment Contents (1) Figure 1 is corrected as shown in the attached sheet. that's all

Claims (4)

[Claims] (1) A microcomputer that is formed within a single semiconductor chip and includes a circuit that can compress and store information on bus lines that are not drawn out to external terminals, and read it out as necessary. (2) The microcomputer according to claim 1, wherein the bus line is a data bus line. (3) The microcomputer according to claim 1, wherein the bus line is an address bus line. (4) The microcomputer according to claim 1, wherein the bus lines include a data bus line and an address bus line.