JPH05346870A - Digital computer system - Google Patents

Abstract

PURPOSE:To provide the computer system which can monitor an operation of a processor at a desired timing without imposing a burden on a software, and without exerting influence on an operation of the processor itself. CONSTITUTION:In addition to an instruction fetch unit IFU, a sequencer SEQ, an operation unit OU, an internal register unit IRU and an external interface EXT-I/F, constituted as processors of the computer system, a diagnostic control circuit 100 is provided. The diagnostic control circuit 100 is provided with counters 101, 102, a timer 103 and a main diagnostic control processing circuit 104. In order to set a diagnostic timing and its function, diagnostic bits DIAGA, DIAGB are prescribed to an instruction word. In response to a set diagnostic condition, the main diagnostic control processing circuit 104, for instance, allows a first counter 101 to count the number of times of fetch of an instruction, and allows the timer 103 to count an operation time of a program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital computer system, and more particularly to a digital computer system suitable for diagnosis and debugging.

[0002]

2. Description of the Related Art Monitoring or diagnosing the operation of a processor in a digital computer system is performed, for example, during program debugging, during maintenance of the digital computer system, or when a failure occurs in the digital computer system. It is valid. Therefore, various measures have been taken to monitor or grasp the internal operation of the digital computer system, in particular, the operating state of the program. Directly access the internal bus to monitor the details of the processor and the movement. Has not been realized yet, and software is usually used to monitor the input / output status of the processor via the external bus.

Computer system diagnosis, debugging, and statistics collection functions are usually performed by software.
This is realized by simulating (emulating).

[0004]

Since the internal bus of the digital computer system cannot be directly monitored, the problem that the processor itself cannot be directly monitored has been encountered. In addition, since the operation of the digital computer system is limited by using software to monitor the input / output state, the operation of the monitoring software causes the operation of the digital computer system to operate the original software. In different states, specifically,
It is unavoidable to monitor the digital computer system in a state where the operating speed is reduced or in a special operating state for diagnosis. This encounters the problem of not being able to monitor the operation of the program or the entire digital computer system under actual operating conditions. In addition, the scale of the software becomes large, and the burden of creating diagnostic programs is heavy. The conventional method of diagnosing a digital computer system cannot perform diagnosis by externally giving conditions such as condition setting to the program for the diagnosis.

In addition, the hardware itself cannot be diagnosed by the above-mentioned diagnosis by software emulation, debugging, and statistics collection, the degree of freedom of diagnosis is small, and accurate information collection cannot be performed. It is difficult to obtain the accurate dynamic characteristics of a computer system, which does not perform the original processing of the processor because it spends execution cycles.

The present invention solves the above problems and provides a digital computer system, and in particular, a digital computer system having a high degree of freedom and capable of directly monitoring or diagnosing the operating state of a processor in the digital computer system. To aim.

[0007]

In order to solve the above-mentioned problems and achieve the above-mentioned object, a digital computer system of the present invention is connected to an instruction sequencer for decoding an instruction to be executed and connected to the instruction sequencer for diagnosis. It has a processing function and a diagnostic control circuit for controlling the diagnostic state. The instruction word handled by the instruction sequencer defines bits that determine the diagnostic timing. The instruction sequencer and the diagnostic control circuit cooperate with each other to perform a diagnostic control process according to a preset diagnostic function and a diagnostic state according to a diagnostic timing set in an instruction word to be executed.

Specifically, the diagnostic control circuit has at least a counter that counts the fetch or execution of instructions. Further, specifically, the diagnostic control circuit has at least a timer for clocking. More specifically, the diagnostic control circuit comprises a first counter, a second counter, and
It has a timer.

The command word has a plurality of diagnostic bits, and a diagnostic function is defined by a combination of bits set in these diagnostic bits. The diagnostic control circuit responds to the diagnostic function by the counter and the timer. To operate. Also,
A diagnostic state for operating the diagnostic function in an instruction fetch or execution state is defined, and the diagnostic control circuit performs the set diagnostic function in response to the set diagnostic state.

[0010]

The instruction sequencer which decodes the instruction to be executed decodes the instruction executed by the processor and outputs it to the arithmetic unit. The diagnostic control circuit connected to this instruction sequencer controls the diagnostic processing function and diagnostic state. The diagnostic control process in the diagnostic control circuit is performed at a timing according to the set state of the bit that defines the diagnostic timing and is defined at a predetermined position of the instruction word. The diagnostic control circuit has a counter and a timer, and measures the number of fetched instruction words, the processing time of a certain program, and the like.

A plurality of diagnostic functions are defined by a combination of the bits of the above-mentioned instruction word, a diagnostic state for operating these diagnostic functions is defined, and a diagnosis is performed according to the combination of the diagnostic state and the diagnostic function. Examples of the diagnostic function and diagnostic status are listed below. Diagnostic Function Function 1: The first diagnostic bit is used for the counter and the second diagnostic bit is also used for the counter 1. Function 2: Uses the first diagnostic bit for the counter and the second diagnostic bit for the timer. Use this timer for toggle operations. Function 3: Both the first diagnostic bit and the second diagnostic bit are used for the timer. Function 4: Use the first diagnostic bit and the second diagnostic bit to set a breakpoint. This is used when halting any processor (halt, stopping the operation by stopping the clock). Function 5: Uses the first diagnostic bit and the second diagnostic bit to set a breakpoint. However, this breakpoint setting is used when halting all processors. The number of diagnostic bits is not limited to two, but three or more multiple bits can be used. Diagnostic State State X: Both the first diagnostic bit and the second diagnostic bit act on fetch. State Y: The second diagnostic bit affects execution when the first diagnostic bit is a fetch. State Z: Operates when both the first diagnostic bit and the second diagnostic bit are running. Note that "acting at the time of fetching" means that the first diagnostic bit and the second diagnostic bit can be set when the instruction is fetched.

[0012]

1 is a block diagram of an embodiment of a digital computer system of the present invention. This digital computer system is composed of an instruction fetch unit IFU and a sequencer SE that form the processor body.
Q, operation unit (arithmetic unit) OU, internal register unit IRU, external interface EXT-I /
F, these units have internal control signal bus C1
To C4 are connected to internal data buses D1 to D4.
The internal control signal bus C1 and the internal data bus D1 are connected to the outside of the processor. Further, the computer system includes a first counter (CTRA) 101, a second counter (CTRB) 102, and a timer (TMR) 1.
03, a main diagnostic control processing circuit (IDCC) 104, and a diagnostic control circuit 100 having a bus 105 connected to a diagnostic interface DIAG-I / F is provided inside the processor body. Main diagnostic control processing circuit 104
Via the bus 105 a diagnostic interface DIAG-I
In addition to being connected to / F, it is also connected to the sequencer SEQ.

Further, in the digital computer system of this embodiment, a diagnostic interface D is provided as a diagnostic processing means in the processor so that the operating state of the processor inherent in the computer system can be directly monitored.
IAG-I / F is provided. Diagnostic interface DI
The AG-I / F is an internal data bus D connected to the operation unit OU via the internal data bus D3.
2 or is connected to the sequencer SEQ via the internal control signal bus C4. This diagnostic interface DIAG-I / F also constitutes a processor. The digital computer system further outputs the operation status of the operation unit OU to the outside of the processor via the diagnostic interface DIAG-I / F, or the operation unit OU is forced to perform a special operation by the user. It has a terminal UT.

The instruction fetch unit IFU reads a program to be executed from the outside of the processor, fetches an instruction (instruction) to be executed each time, and applies it to the sequencer SEQ via the internal control signal bus C2. .. The sequencer SEQ sequentially (sequentially) decodes (analyzes) the instruction fetched by the instruction fetch unit IFU, and decodes the instruction to the operation unit OU via the internal control signal buses C3 and C3a according to the instruction. Applied or via the internal control signal bus C3, C3b to the internal register unit I
Applied to RU or internal control signal bus C3, C3
It is applied to the external interface EXT-I / F via c. Therefore, the operation unit OU, the internal register unit IRU, the external interface EXT-I
/ F is controlled by the sequencer SEQ. Instruction fetch unit IFU and sequencer S
In cooperation with the EQ, it decodes and controls the instructions executed in the operation unit OU.

The operation unit OU executes the decoded instruction in the sequencer SEQ. Data is transferred to the internal data bus D2 in accordance with the execution of the instruction in the operation unit OU.
a, D2, and the internal control signal bus C2b, the operation unit OU and the internal register unit IR
Data transmission with U. Similarly, data is transmitted between the operation unit OU and the external interface EXT-I / F via the internal data buses D2a and D2 and the internal control signal bus C2c in response to the execution of the instruction in the operation unit OU. It The internal register unit IRU is a general term for a memory in the processor, and stores data in an internal register without going through the operation unit OU, for example.
Alternatively, the data is sent to the outside. The external interface EXT-I / F is a part that interfaces with the outside of the program, and transmits / receives data to / from the outside via the internal data bus D2. Alternatively, the external interface E is connected via the internal data buses D2c, D2, D2a.
Data transmission / reception between the XT-I / F and the operation unit OU, or internal data buses D2c, D
2, D2b, external interface EXT-I /
Data is transmitted and received between F and the internal register unit IRU.

The diagnostic interface DIAG-I / F has an operation unit O via an internal data bus D3.
U, the internal register unit IRU, and the internal data bus D2 connected to the external interface EXT-I / F. Therefore, the diagnostic interface DI
The AG-I / F can read various data transmitted on the internal data bus D2. In addition, as described above, the sequencer SEQ, in accordance with the instruction decoded therein, the operation unit OU, the internal register unit IRU, the external interface EXT-I.
Controls operations such as / F. Diagnostic interface DIA
The G-I / F is directly connected to the sequencer SEQ, and like the instruction fetch unit IFU, can externally fetch an instruction to be forcibly executed from the user terminal UT. As a result, the data appearing on the internal data bus D2 by externally drivingly controlling the operation unit OU, the internal register unit IRU, the external interface EXT-I / F, etc. according to the instruction applied and fetched via the user terminal UT. Can be read via the internal data bus D3. The diagnostic interface DIAG-I / F also includes the diagnostic control circuit 10
0 main diagnostic control processing circuit 104 to the user terminal UT
The diagnostic command from is sent.

The user terminal UT is connected to the diagnostic interface DIAG-I / F via the internal data bus D4, and controls the diagnostic interface DIAG-I / F from outside the program to monitor the internal state of the program. Or control the program externally. The user terminal UT is realized by using, for example, a personal computer.

The diagnostic control circuit 100 performs diagnostic control processing instructed by the user terminal UT via the diagnostic interface DIAG-I / F. In order to define the control operation of the diagnostic control circuit 100, as shown in FIG.
A first diagnostic bit DIAGA and a second diagnostic bit DIAGB are defined in the field of the instruction word operated by the processor. The combination of these diagnostic bits defines the diagnostic processing content in the diagnostic control circuit 100.

The function and diagnostic status of the combination are illustrated below. Diagnostic function (1) Function 1 The diagnostic bit DIAGA is used for the counter, and the diagnostic bit DIAGB is also used for the counter 1. (2) Function 2 The diagnostic bit DIAGA is used for the counter, and the diagnostic bit DIAGB is used for the timer. Use this timer for toggle operations. (3) Function 3 The diagnostic bit DIAGA and diagnostic bit DIAGB are both used for the timer. That is, the first diagnostic bit DIAG
A is used to start the timer and the second diagnostic bit DIAGB
Is used to end the timer. (4) Function 4 The diagnostic bit DIAGA and the diagnostic bit DIAGB are used to set a breakpoint. This is used when halting any processor (halt, stopping the operation by stopping the clock). (5) Function 5 The diagnostic bit DIAGA and the diagnostic bit DIAGB are used to set a breakpoint. However, this breakpoint setting is used when halting all processors.

The functions described above are processed in the following diagnostic states: Diagnostic state (a) State X First diagnostic bit DIAGA and second diagnostic bit D
Both IAGBs work when fetching. (B) State Y When the first diagnostic bit DIAGA is fetched, the second
The diagnostic bit DIAGB of 0 operates on execution. (C) State Z First diagnostic bit DIAGA and second diagnostic bit DIA
It works when GB and execution together. It should be noted that "acting at the time of fetching" means that when the instruction is fetched in the instruction fetch unit IFU, the first diagnostic bit DIAGA and the second diagnostic bit
It means that the diagnostic bit DIAGB can be set. In addition, it is said that the action at the time of execution is the first time when the instruction is executed.
Diagnostic bit DIAGA and second diagnostic bit DIA
Indicates that GB can be set.

Therefore, by combining the above-mentioned functions and states, it is possible to perform diagnosis of various contents in a total of 15 diagnosis modes. The instruction word shown in FIG. 2 can be arbitrarily set by a user such as a programmer. Therefore, it is possible to specify an accurate diagnostic mode at the program level. In addition, it is possible to easily collect statistical data for evaluation of dynamic characteristics of a processor in a hardware test and a software test or debugging. Since this diagnostic does not use diagnostic software, there is a delay in the operation caused by operating the diagnostic software.
Alternatively, it is possible to prevent the processing content from being changed due to the diagnosis.

First, the diagnostic interface DIAG-I /
The operation of monitoring the internal state of the processor via F will be described. The user (user) is the user terminal UT
Examples of diagnostic modes that are performed via the diagnostic interface DIAG-I / F by using the following are listed below.

(1) Simple data reading mode This mode is a processing mode of reading the data flowing through the internal data bus D2 to the user terminal UT via the diagnostic interface DIAG-I / F. In this mode, start time and end time can be set. Alternatively, the process can be terminated when the read data reaches a predetermined number.

(2) Conditional data reading mode According to the simple reading mode described above, a very large amount of data is read out to the user terminal UT, so the storage capacity and effective utilization of the read out data difficult. Therefore, this conditional data read mode is
A condition for data reading, for example, reading is performed only when data is stored in a certain address of the internal register unit IRU, or the external interface EX is used.
The diagnostic interface DIAG-I / F fetched by the instruction fetch unit IFU by imposing conditions such as reading only when data is output from the T-I / F to the outside via the internal data bus D1. The diagnostic interface DIAG-I / F reads the data flowing to the internal data bus D2 only when the instruction is input from the internal data bus via the internal control signal bus C5 and the corresponding condition set from the user terminal UT is met. However, diagnostic interface DIAG-I /
This is an operation mode in which the data is temporarily stored in the buffer memory provided in F and is output to the user terminal UT. In this mode, for example, the internal data bus D only when the program set by the user terminal UT runs
You can also read the data flowing through 2. Various other conditions can be set for such conditions.

(3) Data write mode In this mode, the diagnostic interface DIAG-I / F interrupts the data set by the user terminal UT to suspend the operation of the instruction fetch unit IFU and replaces the instruction fetch unit IFU. , A data write instruction is fetched via the internal control signal bus C4 and applied to the sequencer SEQ to be transferred from the internal data bus D3 to the internal register unit IRU or to the external interface EXT-I.
/ F is an operation mode of writing data from the user terminal UT to / F. After this operation is completed, the diagnostic interface D
The IAG-I / F restarts the operation of the instruction fetch unit IFU whose operation has been interrupted, and resumes the original program operation again.

(4) Operation unit drive mode In the above data write mode, data is transferred to the internal register unit IRU or the external interface EXT-I / F.
In this mode, the instruction fetch unit IFU is suspended and the operation unit OU is forcibly operated by the instruction from the user terminal UT. Then, the operation result of the operation unit OU is read from the data flowing through the internal data bus D2, and the operation result accompanying the operation of the operation unit OU is monitored.

(5) Statistical processing (analysis) of read data
Processing mode The data read in the simple data reading mode or the conditional data reading mode is statistically processed and the result is output to the user terminal UT. For example,
In the above-described conditional data reading mode, there are processes such as counting the number of times data written in a certain address, calculating an average value, and detecting the time and the value when the value changes.

For example, a more detailed operation of the simple data read mode described above will be described. The user
The "simple data read mode" is set via the user terminal UT. In response to the mode setting, the user terminal UT specifies the mode and drives the diagnostic interface DIAG-I / F. The diagnostic interface DIAG-I / F recognizes the simple read mode, reads the data flowing on the internal data bus D2, and stores it in the internal buffer memory. The diagnostic interface DIAG-I / F continues this operation. In the above-mentioned mode, the user outputs the read data via the user terminal UT to the diagnostic interface DIAG-I.
Request to / F. Diagnostic interface DIAG-I / F
Responds to the request, the read data stored in the buffer memory is sequentially output to the user terminal UT.
The user terminal UT is a diagnostic interface DIAG-
The data output from the I / F is displayed on a CRT display device or output to a printer, for example. As a result, the data transmitted from the operation unit OU to the internal register unit IRU can be transferred to the processor without interfering with the operation on the processor side and without changing or modifying the original program running on the processor. User terminal U provided outside
Can be output to T. As a method of utilizing the data output to the user terminal UT, for example, in the case of debugging, analysis of the intermediate result of the operation of a certain program,
Alternatively, it can be used as a history analysis of a program operating in a series of program processing.

Considering the contents of each of the above-mentioned modes and the operation of the above-mentioned simple data reading mode, the detailed operation in each diagnostic mode is clear, so the detailed operation in the other diagnostic modes described above will be omitted. To do. Configuration shown in FIG. 1 and diagnostic interface D
From the processing functions of the IAG-I / F and the user terminal UT, and the combination of these functions, there is no need for any software load other than the above-mentioned diagnostic mode, and there is no need for debugging, maintenance, or a processor. It goes without saying that other diagnostic processing for monitoring the operation of can be performed.

If such diagnostic modes are used alone or in combination, various usage forms as exemplified below and the effects as a result thereof can be obtained. (1) The processor, such as the programmer, maintenance staff, and customer, does not affect the original operation of the processor itself such as the operation unit OU, the internal register unit IRU, and the external interface EXT-I / F, and the processor is operated under the conditions desired by the user. It is possible to grasp the internal operation status of. As a result, for example, it is possible to analyze the behavior of the program when debugging the program or evaluate the processing result and the validity of the program. (2) By a command from the user terminal UT outside the program, it becomes possible to interrupt or change the processing contents of the program already loaded in the digital computer system. For example, via the user terminal UT the diagnostic interface DIAG-
Data can be given to the I / F and the data can be written to the internal register unit IRU. This process is performed, for example, when performing a time-consuming convergence calculation at the time of debugging, or when the result of the convergence calculation is known in advance, the calculation result is written to the internal register unit IRU via the user terminal UT, It is used for the purpose of shortening the debug time by jumping to the program processing after the calculation. Alternatively, it can be used when the function of the malfunction detection circuit of the processor is confirmed by giving a command that causes a clear malfunction from the outside during maintenance and inspection. (3) The usage status of the circuit module of the processor or the operation analysis of the program can be analyzed by statistically processing the monitoring result of the internal operation of the processor. (4) Enables automatic testing of computer systems during mass production. (5) It can be incorporated as a self-diagnosis circuit of a processor to perform self-diagnosis.

Next, the diagnostic processing operation via the diagnostic control circuit 100 will be described. The command word shown in FIG. 2 is set by software. Therefore, at the time of debugging, the programmer sets the desired condition in the first diagnostic bit DIAGA and the second diagnostic bit DIAGB of the instruction word shown in FIG. 2 in the program desired to be diagnosed in advance. For example, the diagnostic function 1 is set in the diagnostic state X. Then, when the instruction is fetched by the instruction fetch unit IFU, the instruction fetch unit IFU drives the diagnostic control circuit 100 and the main diagnostic control processing circuit 104.
Causes the first counter 101 to count the number of fetches.
The result will be described later in the diagnostic interface DIAG-I / F.
It is output to the user terminal UT via the, and the user can confirm the count value of the first counter 101.

When the diagnostic function 2 is set, the first
The counter 101 counts the fetch of a predetermined instruction, and the timer 103 measures the time from the arrival of the instruction to the arrival of the next predetermined instruction. Timer 10
The target to be clocked by 3 is not limited to the arrival time of the instruction, but is also used to clock the time during which a certain program operates, for example, according to the set diagnostic content.

The operation of 15 combinations of the above-mentioned diagnostic function and diagnostic state is performed in the same manner as above. This diagnostic control circuit 1
The diagnostic processing via 00 is desired by the programmer under the conditions desired by the programmer, reflecting the intention of the programmer, as compared with the case of reading the data flowing through the internal data bus D2 via the diagnostic interface DIAG-I / F described above. The advantage is that the internal operation of the processor or the operation result of the program can be finely recognized. However,
Also in this case, except for the diagnostic functions 4 and 5, the program processing result can be confirmed without affecting the original operation of the processor. The diagnostic functions 4 and 5 can also be executed when it is desired to confirm a certain state in the processor in the case of data.

Further, the diagnostic interface DIAG-I /
Data collection from the internal data bus D2 by F and diagnosis by the diagnosis control circuit 100 can be combined. As a result, various kinds of diagnosis, debugging support, maintenance and inspection in the computer system can be realized very effectively. When performing these diagnostic processes, the prosema, the maintenance staff, and the user can perform them through the user terminal UT, and the desired diagnostic can be easily realized.

FIG. 3 is a block diagram of a more specific digital computer system of the present invention. The digital computer system shown in FIG. 3 is a parallel distributed processing type digital computer system using a symbol processing language, for example, LISP, and an evaluator unit EU.
, Resource manager RM, data storage STR
G, diagnostic interface DIAG-I / F, and
It has a diagnostic means DIAG. Here, the evaluator unit EU is located as a computer main body, and the workstation WS in the resource manager RM is located as an external computer corresponding to the user terminal UT. The diagnostic interface DIAG- shown in FIG.
The I / F and the diagnostic means DIAG are the diagnostic interface DIAG-I / F and the diagnostic control circuit 100 in FIG.
It corresponds to. In the configuration example shown in FIG. 3, the diagnostic means D
The IAG has the diagnostic interface DIAG-I shown in FIG.
/ F and the processing of the diagnostic control circuit 100, the diagnostic interface DIAG-I / F shown in FIG. 3 corresponds to the internal data bus D4 shown in FIG. 1 simply used for connection with the workstation WS. There is. Therefore, the diagnostic means DIAG incorporates the circuit of the diagnostic control circuit 100 shown in FIG. The data storage STRG is one type of external device of the processor.

The modules constituting the digital computer system shown in FIG. 1 are as follows when the relevant parts of the modules in the computer system shown in FIG. 2 are associated. The instruction fetch unit IFU shown in FIG. 1 is the instruction cache IC in the evaluator unit EU shown in FIG. 3, the sequencer SEQ is the system controller SC in the evaluator unit EU, and the operation unit OU is the arithmetic unit ALU in the evaluator unit EU. And a masker MSK, an internal register unit IRU is a local memory LM in the arithmetic unit ALU, an external interface EXT-I / F is a main memory interface MM-I / F and a resource manager interface RM-I / F in the arithmetic unit ALU, and a user. Terminal U
T is a workstation WS in the resource manager RM
Is.

Further, the internal data buses D1 to D shown in FIG.
4 corresponds to the internal data buses IB1 to IB3 in FIG. However, the internal control signal bus C is not shown in FIG. The diagnostic means DIAG includes internal data buses IB1 to IB.
3 through internal bus connection lines IL1 to IL3. The diagnostic means DIAG is connected to the system controller SC corresponding to the sequencer SEQ via the internal bus connection line IL4. Also, diagnostic means D
The IAG is connected to the workstation WS via a diagnostic interface D-I / F, and this diagnostic interface D-I / F corresponds to the internal data bus D4 shown in FIG.

In the digital computer system shown in FIG. 3, as in the digital computer system shown in FIG. 1, the user terminal UT shown in FIG.
In accordance with the specification of the diagnostic mode from the workstation WS that functions as a user, operation monitoring within the evaluator unit EU desired by the user, setting of external drive conditions,
Other actions can be performed.

The diagnostic means DIAG shown in FIG. 3 including the diagnostic control circuit 100 shown in FIG. 1 has a 32-bit first counter 101 and a second counter 102, a resolution of 50 ns and a timer 103 having a 32-bit width. Have. Therefore, the timer 103 has a maximum of 200
Can measure seconds. The instruction words in the digital computer system shown in FIG. 3 include a data transfer type, a branch type, a data operation type, a multidirectional branch type, and the like. The first diagnosis bit DIAGA and the second diagnosis shown in FIG. The bit DIAGB is located at a common fixed position, for example, the MSB and the next bit position, regardless of the structure of these instruction words. Therefore, in the diagnostic means DIAG, the diagnostic control circuit 100 shown in FIG.
When the main diagnostic control processing circuit 104 of (1) operates, the diagnostic processing for the above-mentioned diagnostic function can be performed regardless of the configuration of the instruction word.

Since the diagnostic means DIAG shown in FIG. 3 performs the operation of the diagnostic means DIAG shown in FIG. 1 and the operation of the diagnostic control circuit 100, as described above, in the digital computer system shown in FIG. The diagnostic processes can be combined.

[0041]

According to the present invention, the operating state of a program or the operating state of a processor does not hinder the operation of the program or the original operation of the processor,
I can know. Further, according to the present invention, a desired diagnosis timing can be set in the command word, so that detailed diagnosis processing, statistics collection, etc. can be performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of a digital computer system of the present invention.

FIG. 2 is a diagram showing a configuration of an instruction word that supports diagnosis in the digital computer system of FIG.

FIG. 3 is a block diagram of a parallel distributed processing digital computer system using a symbolic language as a second embodiment of the digital computer system of the present invention.

[Explanation of symbols]

IFU ... Instruction fetch unit SEQ ... Sequencer IRU ... Internal register unit OU ... Operation unit EXT-I / F ... External interface C1 to C4 ... Internal control signal bus D1 to D4 ... Internal data bus DIAG ... Diagnostic means DIAG-I / F ... Diagnostic interface DIAG-I
/ FUT ··· User terminal EU · · Evaluator unit RM · · Resource manager STRG · · Data storage ALU · · Arithmetic unit (operation unit) IB1 to IB4 · Internal bus IL1 to IL4 · Internal bus connection line WS ·・ ・ Workstation IC ・ ・ ・ Instruction cache SC ・ ・ ・ System controller LM ・ ・ ・ Local memory 100 ・ ・ Diagnostic control circuit 101 ・ ・ First counter 102 ・ ・ Second counter 103 ・ ・ Timer 104 ・ ・ Main Diagnostic control processing circuit

Claims (6)

[Claims] 1. An instruction sequencer for decoding an instruction to be executed, and a diagnostic control circuit connected to the instruction sequencer for controlling a diagnostic processing function and a diagnostic state. Defines a bit that determines the diagnostic timing, and the instruction sequencer and the diagnostic control circuit cooperate with each other to set a preset diagnostic function and diagnostic state according to the diagnostic timing set in the instruction word to be executed. Digital computer system that performs diagnostic control processing according to. 2. The diagnostic control circuit has a counter for counting at least instruction fetch or execution.
The described digital computer system. 3. The digital computer system according to claim 1, wherein the diagnostic control circuit has at least a timer for clocking. 4. The digital computer system according to claim 1, wherein the diagnostic control circuit has a first counter, a second counter, and a timer. 5. The command word has a plurality of diagnostic bits, a diagnostic function is defined by a combination of bits set in these diagnostic bits, and the diagnostic control circuit responds to the diagnostic function by the counter. And operating a timer.
4. The digital computer system according to any one of 4 to 4. 6. A diagnostic state for operating the diagnostic function in an instruction fetch or execution state is defined, and the diagnostic control circuit executes the set diagnostic function in response to the set diagnostic state. 5. A digital computer system according to any one of 5).