JPS58221424A - Testing method of data - Google Patents

Abstract

PURPOSE:To detect a default between interfaces of a host device and a subordinate device, by returning data sent from the subordinate device to the host device reversely from the host device to the subordinate device to collate them with each other. CONSTITUTION:The data of the subordinate device which are inputted from a BUS IN by a strobe signal S1 are stored in registers 1-4 successively through a counter 16. When receiving the data, an IOC (I/O controller) host device sends the data to a BUS OUT and responds by a strobe signal S2. The signal S2 is inputted to an FF 11 and a counter 14, and a decoder 13 sends signals to open gates 5-8 successively. The returned data from the IOC are inputted to a comparator 9 and compared with the data stored in a register of which gate is opened by the specification from the decoder 13. The output of an OR circuit 10 is changed to ''1'' and ''0''. If the data of the BUS OUT are incorrect and the compared output is kept dissident the FF 11 is set up by the signal S2 and an AND circuit 12 outputs ''1'' to inform the data error.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a data inspection method for detecting errors occurring during data transfer between a higher-level device and a lower-level device. (b) Prior art and problems with a higher-level device When transferring data from a lower-level device to a higher-level device, such as between a channel and an input/output control device or between an input/output control device and an input/output device, the lower-level device, such as an input/output device, must undergo an FCC check or a A click check is performed, and if there is an error in the sent data, the input/output control device of the host device is notified. However, in this case, although errors occurring inside the input/output device can be detected, it is unclear whether the input/output control device received the data correctly.
Therefore, if an error occurs in the data between the input/output device and the input/output control device for some reason, there is a drawback that the cause cannot be determined and a large amount of time is required to investigate.

(e) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks by transmitting data sent from a lower-level device to a higher-level device from the higher-level device to the lower-level device;
The object of the present invention is to provide a data inspection method that allows a lower-level device to detect the occurrence of a data error by comparing the data, and detects a failure between an interface between a higher-level device and a lower-level device.

(d) Structure of the Invention The structure of the present invention includes means for temporarily storing data sent to a higher-level device in a lower-level device, and means for determining one address of the storage device based on data transfer timing between the lower-level device and the higher-level device. means for comparing the data stored in the storage means with the data sent back to the host device and sent back from the host device; and means for reporting a discrepancy between the data detected by the comparison means. This system is designed to detect errors that occur during data transfer between a higher-level device and a lower-level device.

Embodiment of the Invention FIG. 1 is a block diagram of a circuit showing an embodiment of the invention.
FIG. 2 is a time chart explaining the actions of the first prisoner.

For example, the lower device is an input/output device (hereinafter abbreviated as I10), and the upper device is an input/output control device (hereinafter abbreviated as IOC).
The strobe signal indicating data reception from the IOC side is assumed to be 82. First, when IOC requests data transfer to rlo, Ilo sends BUS with strobe signal S1.
0 terminal R that puts data on IN and sends it to IOC
EAD p counter 14.16'i is enabled.

Strobe signal 5IU input from terminal S1 enters counter 16 and decoder 15, increments counter 16, enables decoder 15, decodes the counted value of counter 16, and sequentially inputs from register 1 to register 2,
Supplies register 3, register 4 and clock. Terminal B
The data entered from US IN is stored in one of the registers 1-4 pointed to by the decode 15. Second
In the figure, Sl is the strobe signal S1, and data 19 input from BUS IN is stored in register IK because the counter 16 is initially 0. Then, data oo is stored in register 2, data 02 is stored in register 3, and data o4 is stored in register IK. is register 4
Then, data 08u register 1 and strobe signal S are sequentially sent to data 08u register 1.
It is stored in the same register during the four pulses of 1.

When the IOC receives data, it puts the data on BUS o'6r and responds with a strobe signal S2. The strobe signal S2 input from the terminal S2 enters the flip-flop block 11 and the 2-bit counter 14, and the 0 decoder 13, which increments the counter 14, decodes the count value of the counter 14, and sequentially passes the gate 5 to the gate 6. 7. Gate 8
0 terminal BUS OUT which sends the signal to open the gate.
The input data returned from the IOC is sent to the comparator circuit 9.
Then, the data is compared with the data stored in the register whose gate is opened as indicated by the decoder 13. In FIG. 2, S2 is a strobe signal S2, and since the counter 14 is initially 0, the gate 5 is opened and the data 19 input from the BUS OUT is compared with the data 19 stored in the register 1. Subsequently, the gate 6 is opened and the data 00 on the BUS OUT is compared with the data 00 stored in the register 2. Similarly, data 02 is compared with gate 7 opened, and data 04 with gate 8 opened. When the data reaches 08, it returns to the original state, gate 5 opens, and new data 0 is stored in register 1.
Compared to 8. The output of the comparison circuit 9 is the strobe signal S.
2 enters, gates 5 and υ gates 6 are switched sequentially, but BU
Since the S OUT data does not switch immediately, it is reversed as a match or mismatch, and the output of the OR circuit 10 changes to "1", '0', but the arriving BUS OUT data is incorrect as 05, and I10 is sent. If the output compared with data 04 remains inconsistent, the flip-flop 11 is reset by the strobe signal S2' as shown by FFII. When the END signal, which indicates the end of data transfer to , becomes 1", and the data read signal READ becomes 1" due to completion of data reading, the terminal ERRt becomes "1" and reports that there was a data error during data transfer. do. Terminal RESE
The flip-flop 11 is reset by the signal from T and the alarm is canceled. In this example, the number of registers is 4, and the counters 14 and 16 are 2 bits. However, as the interface between Ilo and IOC becomes faster, the exchange of strobe signals becomes more complicated due to the cable length and delay in logic circuit operation. The deviation between the strobe signals S1 and 82 increases.

The delay amount of this strobe signal S1 and pS2 is the number of pulses N.
The following conditions are required between the number of registers and the number of registers.

Number of registers 〉 N (f) As described in the detailed description of the invention, the present W" can detect errors in transferred data that occur between interfaces between upper and lower devices, thereby improving data reliability. At the same time, it is possible to shorten the total time required for fault investigation, which has a great effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a drinking water circuit according to an embodiment of the present invention, and FIG. 2 is a time chart illustrating the entire operation of FIG. 1. 1 to 4 are registers, 5 to 8 are gates, 9 is a comparison circuit, 1
1 is a flip 70 tube, 13.15 is a decoder, 14,
16 is a counter.

Claims (1)

[Claims] In a method for detecting errors that occur in data being transferred between a higher-level device and a lower-level device, the lower-level device includes means for temporarily storing all data sent to the higher-level device, and data between the lower-level device and the higher-level device. means for determining the address of the storage means based on the transfer timing; means for comparing the data stored in the storage means with the data sent back from the host device to the host device; 1. A data inspection method, characterized in that it detects an error occurring during data transfer between a higher-level device and a lower-level device.