JPH03175770A - Parallel data test method - Google Patents

Abstract

PURPOSE:To reduce the processing time required for the check by providing a check function as to a transferred data to a 2nd program processing unit such as each line adaptor section so as to relieve the check load as to the transferred data from a 1st program processing unit such as a main controller. CONSTITUTION:A main controller 200 writes the order for program start to the control register of a lie processing section 220 under the control of a main controller 200 after the transfer of a transfer program to a line adaptor section 260i and the execution of a transfer data test program transferred already to the line adaptor section 2601 is started by the line adaptor section 2601. When the execution of the transfer data test program is started in the line adaptor section 2601, a start reply is transferred to a main controller 200 via a line processing section 220. The main controller 200 obtaining the start confirmation of the transfer data test program by the normal start reply reception reads the data for the transfer test from a display device 340 to the main storage device 300 via a channel controller 2m.

Description

[Detailed Description of the Invention] [Summary] Concerning a parallel data testing method in which a second program processing device performs a normality test of data transferred from a first program processing device to a second program processing device, the present invention relates to a test control method. With the aim of reducing test time and improving reliability while reducing the burden, a first program processing device having a transfer data test program for checking transferred data is transferred to a plurality of second program processing devices. In a system for checking the normality of data transferred to a second program processing device, prior to checking the transferred data, the transferred data test program and test data are sent to the plurality of second program processing devices in parallel. The transfer is performed in a predetermined order, and the normality of the data transferred to each second program processing device is checked by the transfer data test program received by the second program processing device. .

[Industrial application field]

The present invention relates to a parallel data testing method in which a second program processing device performs a normality test on data transferred from a first program processing device to a second program processing device.

In digital exchanges and the like, data is transferred from one control device to another control device, and the data is used by the other control device to perform necessary control. This type of device does not guarantee that the transferred data is always correct. Therefore, in this type of device, data normality tests are always performed.

[Conventional technology]

The above-mentioned data transfer in a conventional digital exchange is performed by a main controller (CC-1) as shown in FIG. 4, for example.
0) Disk unit (DKCO) 3 under 20° control
This is a transfer of the program from 4° to the line corresponding unit (LCO) 26oo to the 1 line corresponding unit (LC7) 2607.The transfer method is the disk device (DKCO) 34
The program read from ゜ is sent to the channel control device (
CHCot)2B. The main storage device 30. is stored in Its main storage device 30. The program is stored in the line processing unit buffer in the line processing unit 22° via the channel control device (CHCO□) 32°. To transfer the program in each line corresponding section buffer to the corresponding line corresponding section,
The reception request from the line handling unit and the line processing unit 26oo
, . . . is generated from the line processing unit 22° to the line corresponding unit when the transfer request in the two-line corresponding unit 26o7 matches.

In this way, a test to determine whether or not the transferred program has been correctly transferred to the line corresponding section is carried out by the diagnostic program executed by the main controller 20°. read out,
The purpose is to test its normality.

Note that the program transfer process described for the O system described above also applies to the I system. In Figure 4, components that are the same as each component of the 0 series are indicated by the suffix of the respective reference number attached to each component of the 0 series.
Reference numbers are given to those components of series 1.

[Problem to be solved by the invention]

As mentioned above, the conventional transfer data testing method is a method in which tests are sequentially performed on each line corresponding part under the control of the main controller, so the burden of test control is placed on the main controller. Not only will the exam take longer, but it will also take longer to complete the exam.

Prolonging the test time leads to a decrease in the reliability of the switching system.

The present invention was created in view of such problems, and its purpose is to provide a parallel data testing method that can shorten test time and improve reliability while reducing the burden of test control. do.

[Means to solve the problem]

The present invention provides a system for checking the normality of data transferred from a first program processing device to a plurality of second program processing devices, which has a transfer data test program for checking transferred data. , prior to checking the transferred data, transferring the transferred data test program and test data to the plurality of second program processing devices in parallel in a predetermined order, and transmitting the transferred data test program and test data to each second program processing device. The transfer data test program is configured to check the normality of the transferred data using the transfer data test program received by the second program processing device.

[For production]

When checking the normality of data transfer, the transfer data test program and the test data are transferred in parallel from the first program processing device to the plurality of second program processing devices in a predetermined order. For example, as shown in FIG. 1, transfer data test programs and test data are transferred in parallel from a first program processing device to a plurality of second program processing devices in order.

Each second program processing device checks the transferred data using a transferred data test program.

The result is used by the first program processing device or the second program processing device.

〔Example〕

One embodiment of the present invention is an example implemented in a digital exchange with a duplex configuration as shown in FIG. It is shown in Figure 3. A program for performing each process shown in this process flow is stored in the disk device 34 and the disk device 341 before the process is executed. The storage is performed by a conventional, well-known program loading device (not shown). The program is executed between the main controller 20o or 20 and the line controller 24 or 241 by following the steps described below to ensure the normality of the transferred data according to the present invention. A test will be conducted regarding. In this test, control registers and the like in the line processing section 22o are used.

Next, a test of the normality of transferred data in the constituent exchange system will be described. Since both systems perform the same processing, the O system, which is a backup system, will be explained as a representative.

When the main unit of the exchange enters a test to determine whether the transferred data was transferred normally (see 100 in Figure 2), the transfer program including the data check function transfers the data to the disk under the control of the main controller 20°. device 34 to the main storage device 300 via the channel control device 28° (second
(See 102 in the figure and ■ in Figure 4). Then, in order to transfer the program to a predetermined line control device 24°, the main control device 20. writes the order for program transfer to the control register of the line processing unit 22., and then the line processing unit 22. is the main storage device 20.
writes the transfer program read out from the main storage 30° into a buffer in the line processing unit 22o under the control of the line processing unit 22o (see ■ in FIG. o, ..., 7
) (see 104 in Figure 2 and ■ in Figure 4).

After transferring this transfer program to the line processing unit 26o, the main control unit 20° writes an order for starting the program into the control register of the line processing unit 22° under the control of the main control unit 20°. The line handling unit 26. starts executing the transfer data test program that has already been transferred to the line handling unit 26. bring about i. When execution of the transfer data test program is started in the line handling unit 26o1 (see 200 in FIG. 3), a startup response is sent from the line handling unit 26o to the main controller via the line processing unit 22o. 2
It is transferred to 0°. Upon receiving the normal startup response, the main controller 20°, which has confirmed the startup of the transfer data test program (see 202 in FIG. 3 and 108 in FIG. 2), transfers the data for the transfer test from the disk device 34°. a channel control device 28; The main storage device 30. (see 110 in FIG. 2). When an abnormal activation response is received, the abnormality processing is performed in the same manner as before. The line handling unit 26o that sent out the activation response sends a reception request to receive the test data to the line processing unit 22° (
(See 204 in Figure 3). In response to this reception request, the main control device 20° transfers the transfer test data from the main storage device 30° to the channel control device 32° and the line processing unit 22° to the line handling unit 26o.

(see 112 in FIG. 2).

It is checked whether the data for the transfer test is a normal value (see 206 in FIG. 3). In this check, if the received data is an invalid value, the corresponding bit in the check result storage area is turned on. When all the received data have been successfully checked, a notification of normal completion is sent to the main controller 20 via the line processing unit 22°.
(See 208 in Figure 3). Line support section 26
When an abnormal termination notification is received from ゜-), the abnormality processing is performed in the same manner as before.

0 The main control device 20, which has received the notification that the check for all received data has been completed from the line correspondence unit 26° (see 114 in FIG. 2), reads out the check result storage area in the line correspondence unit 260f. Line processing unit 22. (see 116 in FIG. 2). The normality of the transferred data is confirmed by checking whether the check bit corresponding to each read transfer test data is on or off (see 118 in FIG. 2).

In the above embodiment, a test for the normality of data transferred from the main controller 20° to the line handling unit 26o via the line processing unit 22° in a duplex digital exchange was explained. The present invention can also be applied to a data transfer system in which the transfer destination is a device or system that can be equipped with the program processing function described above.

〔Effect of the invention〕

As is clear from the above, according to the present invention, the second program processing device such as each line corresponding section 26.4 is provided with a check function for transferred data. The burden of checking the data is no longer placed on the first program processing device such as the main controller 20, and the checking processing in each line correspondence section 26 can be performed in parallel, reducing the processing time required for checking. It can be shortened. This enables real-time checking and helps improve system reliability.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a diagram showing a processing flow on the exchange main body side in an embodiment of the present invention. FIG. 3 is a diagram showing a processing flow on the line side in an embodiment of the present invention. Figure 4 is a configuration diagram of a digital exchange with duplex configuration, Figure 5
The figure shows a transfer data test method in a conventional digital exchange. 2 In Figure 4, 20°, 20. 22°, 221 is the main controller, 221 is the line processing unit, 24°, 24. is a line processing device, 26°. ,...,260? , 26. . ,... 26
17 is a line support section, 28°, 2B, 32°, 32. 30° and 301 are main storage devices, and 34° and 34I are disk devices. 3 This month's βλ engineering theory square diagram Figure 1 JP-A-1999-3 175770 (5) I'm afraid of Danshifu p9 - Power recovery Omo 1 and Brochure Figure 5

Claims (1)

[Claims] (1) In a system for checking the normality of data transferred from a first program processing device to a plurality of second program processing devices having a transfer data test program for checking transferred data, Prior to checking the transferred data, the transferred data test program and test data are transferred to the plurality of second program processing devices in parallel in a predetermined order, and the transferred data is transferred to each second program processing device. A parallel data testing method characterized by checking the normality of data using the transfer data test program received by the second program processing device.