JPS61163460A - Data transfer system of multiprocessor system - Google Patents

Abstract

PURPOSE:To shorten the transfer time an to check securely the transfer by providing a flag for a bus controller in a submodule and transferring data, etc., to each processor through the action of each flag in terms of multiple address. CONSTITUTION:When a program and data are transferred to each submodule 2, with the control of a disk controller 8 a main module 1 loads a common program, etc., in a magnetic disk device 9 in a memory 6. Then the common program, etc., are loaded in the memory 6 of the module 2 through the bus controller 4 of the submodule 2. In this case flags 13-15 in the controller 4 of the module 2 are operated, whereby the common program and data are transferred in terms of multiple address. Upon the completion of the transfer the processor 5 of the module 1 checks the transfer state. If it is abnormal re-transfer is carried out. Thus the transfer time can be shortened, and the transfer of data, etc., can be confirmed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data transfer method for a multiprocessor system.

[Background of the Invention J] One type of multiprocessor system is a so-called flexible coupling multiprocessor system in which each processor has its own main memory and operates on programs stored in the main memory. Initial program loading (hereinafter referred to as I) for each of these processors
(abbreviated as PL), there is no problem if it is performed independently from its own external storage device, or if one processor is the main processor and the other processors are
In some cases, the main processor reads a program from an external storage device possessed by the main processor, supplies the program to each sub-processor, and loads the program.

Normally, the main processor loads programs serially to each sub-processor, so if the number of processors increases, the IPL time will be 9.30 minutes or more.
Sometimes it took an hour. Also for each subprocessor.

Although there is a multiprocessor system that performs an IPL by running a subprocessor, there is no system that checks whether the programs and data necessary for each subprocessor are reliably stored in the main memory of each subprocessor.

An example of IPL in a multiprocessor system is the technique disclosed in Japanese Patent Laid-Open No. 58-169279.

(Object of the invention) The invention is to reduce the required time by concurrently transferring data to each processor of a multiprocessor system,
It is also an object of the present invention to provide a data transfer method that can check whether data has been transferred reliably.

(Summary of the Invention) In the present invention, a transmitting processor forces a receiving processor to take in data, and after performing data transfer in a circular manner via a common transmission path, each receiving processor Detects whether the above data transfer was performed normally for the processor, cancels the above state for the normal receiving processor, and transfers the same data again while maintaining the above state for the receiving processor for which an abnormality was detected. It is characterized by a data transfer method for multiprocessor systems.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. FIG. 1 is a block diagram of a multiprocessor system to which the present invention is applied. Reference numerals 1 and 2 are modules that constitute the multiprocessor system. :J
11 is a main module that controls and monitors all other modules; 2 is a submodule under the control of the main module 10; 3 is a bus that transmits signals between 7 joules; 4 is a bus that transmits data on bus 6 or bus 6; 5 is a microprocessor, 6 is a memory that stores programs and data, 7 is an I/◇ controller that controls terminals or communication lines connected to this system, 8 is an I10 control 2
A disk controller 9, which is one type of disk controller, is a magnetic disk device that stores programs and station data for the main module 1 and submodule 2. FIG. 2 is a block diagram of the submodule 2, and i5.13.14 and 15 are flags held by the bus controller 4. Figure 3 shows main module 1 to sub module 2.
This is a diagram hierarchically showing the structure of the program transferred to. 10 is a common program used by all submodules; 11 is a procedure program that executes control procedures for connected terminals or communication lines; and 12 is a unique program that provides control information about terminals and lines connected to the submodules. This is the station data.

Next, a case where this embodiment is applied to IPL will be described using FIGS. 1, 2, and 3. As shown in FIG. 3, the program structure loaded into each sub-module consists of a procedure program 11 common to each sub-module group and a station data program 12 different for each sub-module group. There is. The main module 1 loads the main module control program of the magnetic disk device 9 into the memory 6 of the main module under the control of the disk controller 8. When the program loading of the main module 1 is completed, the processor 5 of the main module 1 starts and starts loading the program of the submodule 2 from the magnetic disk device 9 to the memory 6 of each submodule 20 according to the procedure described below. .

The processor 5 of the main module 1 transfers the common program 10 from the magnetic disk drive 9 to the memory 6 of the main module 1, and then sets the common program loading flag 13 of the sub module 2 to 1' via the bus controller 4 of the main module 1. Then, each module 2 sends the common program 10 from the main module 10 memory 6 to ... 3 via the bus controller 4.
This common program 10 is taken in parallel through its own bus controller 4 and loaded into the memory 6. In this way, all submodineal 72g1
By setting 3 to 11, each submodule is forced into a state where it can take in data, and under this state, the common program 10 is transferred in a circular manner. Main module 1 processor? 5 reads a partial area of the memory 6 of each sub-module 2 through the bus 3 after the sending of the common program 10 is completed, and checks whether or not the common program 10 of the sub-module 2 has been successfully loaded. do.

In the normal case, the main module 1 sets the 7-lug 13 of the bus controller 4 of the sub-module 2 to 'o I. In case of abnormality, leave it at 1'.

Next, the procedure program 11 is transferred from the magnetic disk drive 9 to the memory 6 of the main module 1, and the 7 lug 14 of the bus controller of the loading hex sub-module is moved to 1'.
Loading and checking are performed using the same procedure as for loading the common program 10 described above. If normal, the 7 lugs 14 of submodule 2 are set to 10'. Next, the station data 12 is loaded in the same procedure as above. After loading the common program 102 procedure program 11 and station data 12 for all sub-modules 2, the processor 5 of the main module 1 reads the flags 15, 14, 15 of each sub-module 2) to determine whether the loading is normal or abnormal. Check for abnormal submodules and reload the program.

Note that the method for starting program execution after IPL is well known and will not be described in detail.

Although this embodiment has been explained using an example of initial program loading, it is clear that generally any data can be transferred between modules using the same method.

Also, the transmission path between modules is not a bus-type transmission path;
Other types of transmission paths may also be used. In addition, the above embodiment is
When checking whether the program loading to the sub-module 2 is normal, the main module 1 reads and checks a part of the area of the memory 6 of the sub-module 20, but the check may be performed using other methods. For example, after a program is loaded into the submodule 2, the submodule 2 itself checks the program using a test routine and reports the result to the main module 1 within a predetermined time.

[Effects of the Invention, 1] According to the present invention, there is an effect that data transfer to each processor of a multiprocessor system is performed in parallel, the time required for the transfer is shortened, and it is possible to check that the data has been transferred reliably.

[Brief explanation of drawings]

FIG. 2 is a block diagram of the M111t multiprocessor system, FIG. 2 is a block diagram of the submodule, and FIG. 5 is a diagram showing the configuration of the transferred program. 1... Main module, 2... Sub module, 3... Bus, 4... Bus controller, 5... Microprocessor, 6... Memory,
13, 14, 15...flags. Part) National Tradition 2I! 1

Claims (1)

[Claims] A plurality of processors, each equipped with a computer and a storage device,
In a multiprocessor system that is interconnected by a common transmission path and transfers data from a storage device of a transmitting processor to a storage device of at least one other receiving processor in parallel, the transmitting processor The processor forcibly puts the receiving processor in a state where it can take in data, performs the data transfer in a broadcast manner, and then detects whether or not the data transfer has been performed normally for each receiving processor. A data transfer method for a multiprocessor system, characterized in that a normal receiving processor is released from the above state, and a receiving processor in which an abnormality has been detected transfers the same data again while maintaining the state.