KR940004732B1 - Initial method of input/output apparatus - Google Patents

Abstract

The method has the effect of initialization to an intelligence input-output device by execution of procedure functions. The method a main processing board (1;MPMA), a control register (2;CR) which manages interrupt functions, a state register (11;SR), an initialization control block (13;ICB), and an input-output interface board (4;IOIA). The method includes a 1st step (26,27) which manages a memory and synchronous management signals, a 2nd step (28) which executes an initialization function, and a 3rd step (25,29,31) which terminates or initializes functions.

Description

Initialization method of input / output device in real time operating system

1 is a block diagram of an upper processor (MPH) of an electronic switching system which is hardware to which the present invention is applied.

2 is an internal configuration diagram of an input / output interface board.

3 is a schematic flowchart of initialization processing of the entire processor.

4 is a detailed flowchart of the present invention.

* Explanation of symbols for main parts of the drawings

1: Central Processing Unit Board (MPMA) 2: Memory Fault Control Board (MECA)

3: Dual Operation Control Board (DCCA) 4: Mass Storage Board (MSIA)

5: Processor communication control board (PCCA) 6: I / O interface board (IOIA)

7: Initial control block (ICB) 8: Control register (CR)

9: Status register (SR)

The present invention relates to an initialization method of an intelligent input / output device for an operating system of a large-capacity electronic switching system.

In the recent exchange system, an intelligent input / output device (hereinafter referred to as IOIA) is installed and matched for high reliability, stability, and convenience of operation management function, thereby enabling a dialogue function between the exchange and the operator. Such a system has a modularity and reliability structure compared to a conventional single system in order to accommodate a distributed system structure to distribute the load of the main processor unit to maximize efficiency. In this structure, the input / output device has its own processing capability, but the operation type is a passive type that performs intellectual processing for the request of the main processor. And a redundancy structure is essential to increase availability and reliability.

Accordingly, an object of the present invention is to provide a method for initializing an intelligent input / output device of the electronic switching system.

In order to achieve the above object, the present invention provides a central processing unit board (MPMA) having a central processing unit, and a bus connected to the central processing unit board and controlling a redundant operation mode and interrupt type and interrupt termination function. And an input / output interface board (IOIA) having a register (CR) and a state register (SR) having a state of a response to the request of the MPMA and a state of an input / output processor and an initial control for initial state setting. Applied to the upper processor of the electronic switchboard, the first step of determining whether there is an IOIA, erasing the IOIA-related vector initialization and shared memory, and allocating a memory and a synchronous management signal required for input / output management, and performing the first step And a second step of performing an initialization function according to the duplication state of the IOIA by calling an initialization setting function; According to the result of the second step, the success or failure of the initialization is determined by requesting a restart function, and in the case of success, it is performed by the third step of initializing and terminating a function other than IOIA.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

FIG. 1 is a configuration diagram of an upper processor (MPH) of an electronic switching system, which is hardware to which the present invention is applied, and FIG. 1a is a redundant configuration diagram of all hardware, and b is an initialization related hardware configuration diagram.

In the drawings, 1 is a central processing unit board (MPMA), 2 is a memory error control board (MECA), 3 is a redundant operation control board (DCCA), 4 is a mass storage board (MSIA), 5 is a processor communication control board (PCCA) And 6 denote I / O interface boards (IOIA), respectively.

As shown in the figure, the upper processor hardware (MPH) to which the present invention is applied has a central processing unit board (1) and a memory board (4), and the central processing unit board (1) on which the software of the present invention is mounted and operated. : MPMA), a processor communication control board (PCCA) that is in communication with another processor under the control of the MPMA (1), and redundant operation control in charge of D-channel and C-channel control in connection with redundancy. Board (4: DCCA) is connected to the system main bus.

In order to communicate between the central processing unit 1 (hereinafter referred to as MPMA) and the input / output interface board 4 (IOIA) related to the present invention, input / output matching is obtained by placing a shared memory. Therefore, the shared memory, status register and control register are initialized prior to the input / output operation to determine the operation mode of the input / output board.

FIG. 2 is an internal configuration diagram of the input / output interface board, where 7 is an initial control block (ICB), 8 is a control register (CR), and 9 is a status register (SR).

The figure shows the internal components of the shared memory and control register (hereinafter referred to as CR) and the status register 11 (hereinafter referred to as SR) and the memory of the input / output interface board 4 (hereinafter referred to as IOIA) that accommodates redundancy. The CR (12) manages the redundant operation mode and interrupt type and interrupt termination function, and the SR (11) has the status of the IOIA (4) and the response state to the MPMA (1) request and is shared. The memory is partitioned so that an initial control block 13 (hereinafter referred to as ICB) can be set to control for setting the initial state of the IOIA 4.

3 is a schematic flowchart of the initialization process of the entire upper processor of the electronic switchboard.

Initialization begins when the upper processor of the electronic changer is powered on. First, hardware initialization of the MPMA 1 is performed (20), and hardware initialization and related operations other than the IOIA (4) are performed. The IOIA (4) check address is set (22) to determine whether or not the board exists with the help of the bus error handling function (23).

If the IOIA 4 is not present, it is marked with the presence or absence of the IOIA 4 flag (24). After the initialization process of a board other than the input / output board 4, that is, the main processor, etc., the process ends (25). However, if there is an IOIA (4), it is marked with the presence or absence of the IOIA (4) flag to initialize the relevant interrupt vector and erase the shared memory between the MPMA (1) and the IOIA (4) (26). Then, a work space of memory required for input / output management and a semaphore for synchronous management are allocated (27).

Next, perform the initialization setting function of IOIA (28), check whether it succeeds (29) and if the result is failed, if the retry is necessary, the process of performing the initialization setting function (25) three times, and the result is In the same way, if the user fails to communicate with the operator at all, the cause is outputted and checked, and the restart function is performed (30, 31). If the initialization is successful, various initialization functions other than input / output are performed (25) and the process ends.

4 is a detailed flowchart related to the initialization of the input / output interface function corresponding to the present invention.

When the initialization setting function of the IOIA 4 is called (28 in Fig. 3), the IOIA 4 is read to check the self-test state (41), and the normal state is checked (42). After outputting the uninitialization of the IOIA 4 (43) abnormally terminates, and if it is in a normal state, the redundancy state of the MPMA 1 is checked (44).

As a result of the check (44), if the standby state (Standby), the IOIA (4) does not have any effect on the upper processor unit and prepares to make the zomb state which is ready to receive the redundancy transfer immediately (45) In the active state (Active), it prepares for IOIA (4) initialization command and state reception (35).

When the above preparation is made, the ICB generation process is carried out in which the ICB 7 loads the interrupt vector number to inform the MPMA 1 when the IOIA 4 fails, the interrupt level, the packet for the IOIA control command, and the address for the status notification packet. (47), the interrupt type is determined according to the redundancy state of the MPMA (48) (48), the interrupt type and the redundancy mode are written to the CR (8), and the interrupt is interrupted to the IOIA 4 (49, 50). . That is, when the MPMA 1 is in the standby state, it requests an interrupt to the invoice, and if it is in the operating state, it initializes to the operating state. When the IOIA 4 receives an interrupt, it completes the initial setting and informs the MPMA 1 of the result through the SR 9. In the input / output initialization function of the MPMA 1, the IOIA 4 gives a sufficient time to respond and checks the response (51). If the time is not exceeded, the state of the SR (9) is inquired to check the state change of the SR. If it detects (52) and analyzes it, in case of abnormality such as IOIA (4) failure or IOIA (4) inoperability, the corresponding message is output (53) and checked and returned. Since the input / output initialization function of 1) and the input / output operation wait of the IOIA have been completed, the timeout is output and returned (54).

Therefore, the present invention performed by the above processing procedure has an application effect of smoothly operating the operating state and the standby state of the electronic switching system, and performing an initial role of the intelligent input / output device by performing a series of preceding functions. .

Claims (2)

A central processing unit board (MPMA) having a central processing unit (9) and a bus connection to the central processing unit board (hereinafter referred to as MPMA) provide a redundant operation mode, interrupt type and interrupt termination function. Control register 12 (hereinafter referred to as CR) and the state of the I / O processor and status register 11 (hereinafter referred to as SR) having a response state to the MPMA (1) request and initial control for initial state setting. Intelligent input / output device that is applied to an upper processor of an electronic switching system including an input / output interface board having a control block 13 (hereinafter referred to as ICB) (hereinafter referred to as IOIA) to allow redundancy of the electronic switching system. In the method of performing the initialization of the method, the presence or absence of the IOIA (4) is determined to erase the IOIA (4) -related vector initialization and shared memory, and for the memory and synchronization management required for input / output management A first step (26, 27) of allocating a signal, and a second step of performing an initialization function according to the redundancy state of the IOIA (4) by calling the initialization setting function after performing the first step (26, 27) ( 28) and a third step (25) of determining whether the initialization is successful according to the result of the second step 28, requesting a restart function upon failure, and initializing and terminating a function other than the IOIA (4) upon success. , 29 to 31) the initialization method of the input / output device in consideration of redundancy. 2. The second step 28 reads the SR 9 to determine the self test result, and notifies the state of inability when the determination result cannot be initialized, and the redundant state of the MPMA 1 when initiation is possible. In step 41 to 44 of checking and, as a result of the steps 41 to 44, the ICB 7 is generated after the initialization command and the preparation for the state reception if the operation state is received, and if the standby state, the redundancy switching is immediately received. Generating an ICB 7 (45 to 47) after making the invoice state to be in a state; and after interrupting the IOIA (4) using the initial state information after performing the steps (45 to 47) (49) 50, and after performing the steps 49 and 50, reading the SR (8) value to determine the initialization result of the IOIA (4), and determining the initialization end or IOIA (4) failure according to the result ( 51 to 54) the initialization unit of the input-output device in consideration of redundancy characterized in that performed by Way.