JPH0232270A - Test circuit for soldering defect inspection of multi-pin lsi - Google Patents

Abstract

PURPOSE:To enable inspection with a small number of test patterns without knowing the circuit operation of the multi-pin LSI by selecting the outputs of two-input selectors by a selector input terminal according to normal operation and test operation. CONSTITUTION:Input terminals 2-5 are connected to input buffers 2a-5a, whose outputs are connected to a signal processing block 6 which performs digital signal processing and also connected to AND circuits 12 and 14 directly or through NOT circuits 13 and 15. Then the output of the block 6 and the output of the circuit 12 which is obtained directly; or inverted by a NOT circuit 17 are inputted to two-input selectors 18-21. The outputs of those selectors 18-21 are outputted to output terminals 7-10 through flip-flops 7b-10b and output buffers 7a-10a. Then the outputs of the block 6 and circuit 12 are selected by all the selectors 18-12 by the input terminal 22 according to the normal operation and test operation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a test circuit for inspecting soldering defects in multi-pin LSIs.

BACKGROUND OF THE INVENTION In recent years, L'31 technology has progressed and LSI packages have become smaller and have more pins. An example of a conventional multi-pin LSI will be described below with reference to the drawings.

FIG. 3 shows a conventional multi-pin LSI circuit. In FIG. 3, 1 is a multi-pin LSI. 2 is the first
is connected to a signal processing block 6 that performs various digital signal processing via a first input buffer 2a. The second input terminal 3, the third input terminal 4, and the fourth input terminal 5 also pass through the second input buffer 3m, the third input buffer 4a, and the fourth input buffer 5a, respectively, to the signal processing block 6. Connected to the input terminal. Signal processing block 6
The respective output terminals of to the terminal 8, from the third output flip-flop 9b to the third output terminal 9 via the third output buffer 9a, from the fourth output flip-flop 10b to the fourth output terminal 10 via the fourth output buffer 10m. are connected to each other. Further, the third output terminal 9 and the fourth output terminal 1o are connected to the input terminals 9G and 10c of the memory 11, respectively, and the output terminals 9d and 10d of the memory 11 for the input terminals 9G and 10c are connected to multi-pin terminals, respectively. 3rd of LS11
input terminal 4 and a fourth input terminal 5.

The operation of the multi-pin Lll configured as described above will be described below.

First, input signals from the first input terminal 2 and the second input terminal 3 are input to the signal processing block 6 via the first input buffer 2m and the second input buffer 31, respectively. After various digital signal processing is performed in the signal processing block 6, the output signal is sent from the first output flip-flop 7b to the first output terminal 7 via the first output buffer 7b, and then to the second output flip-flop 7b. from the flip-flop 8b to the second output terminal 8 via the second output buffer 8m; from the third output flip-flop 9b to the third output terminal 9 via the third output buffer 9a; The signals are outputted from 10b to the fourth output terminal 10 via the fourth output buffer 10. Further, each output signal from the third output terminal 9 and the fourth output terminal 1o is inputted to the memory 11, and is outputted to the third output terminal of the multi-pin LS11 with a certain delay time.
is input to the input terminal 4 and the fourth input terminal 5. Each input signal passes through a third input buffer 4a and a fourth input buffer 5a, and is input to a signal processing block 6, where it is used for various signal processing.

Problems to be Solved by the Invention However, in the above configuration, when a multi-pin LSI and a memory are mounted on a printed circuit board, soldering defects must be inspected by visual observation, signal input/output response, etc. With recent advances in LSI technology, packages have become smaller and have more terminals, but there are limits to package size and number of terminals when visually inspected.
The problem is that a huge number of test patterns must be created after understanding the circuit operation of the memory.

Therefore, in view of the above-mentioned problems, the present invention enables soldering defect inspection when multi-bin LSIs and memories are mounted on printed circuit boards, without knowing the circuit operation of multi-pin LSIs, and using a smaller number of test patterns than before. This test can be performed by looking at the input/output response of signals, and when there is an abnormality in the test result, the defective location can be predicted to some extent based on the type of test pattern that caused the abnormality. It provides a test circuit.

Means for Solving the Problems In order to solve the above problems, the test circuit for inspecting soldering defects of multi-pin LLL according to the present invention includes a signal processing block that performs digital signal processing and is connected to the output terminal of each input buffer. , an AND circuit or an OR circuit connected to the output end of each input buffer, and one or more two
It is equipped with an input selector, each output flip 70 tube connected to the output terminal of each two-input selector, and a select input terminal for selecting the output of the two-input selector.

In the above case, if there are no input terminals or output terminals connected to the memory, and if there are input terminals or output terminals connected to the memory, digital signal processing is performed that is connected to the output terminal of each input buffer. a signal processing block, a first AND circuit or an OR circuit connected to the output end of each input buffer connected to an input terminal not connected to the memory, and an output of each input buffer connected to the input terminal connected to the memory. A second AND circuit or OR circuit connected to the end, a test output terminal connected to the output end of the second AND circuit or OR circuit, and an output signal and signal processing of the first AND circuit or OR circuit. One or more 2-input selectors that receive the output signal of the block, each output flip-flop connected to the output terminal of each 2-input selector, and each output connected to the output terminal of each output flip-flop. The device includes a buffer, each output terminal connected to the output end of each output buffer, and a select input terminal for selecting the output of the two-input selector.

For production The effect of this technical means is as follows.

That is, when the multi-pin Ill performs normal operation, it is sufficient to cause all two-input selectors to select the output of the signal processing block using the select input terminal. Further, when performing a test for inspecting soldering defects, the select input terminal causes all two-input selectors to select the output of an AND circuit or an OR circuit. Thereby, when a test pattern is input to the input terminal, a signal is obtained from each output terminal of the multi-pin LSI.

Here, if there are no input terminals or output terminals connected to the memory, it is possible to inspect the soldering defects of all input/output terminals by checking the signals of each output terminal.

The test pattern is an AND input to a 2-input selector.
A pattern in which the output signal of the circuit or OR circuit is a logical value "1" when using an AND circuit, and a logical value W+ when using an OR circuit, and the logical value of each input terminal is the same as above for each terminal. All you have to do is create a pattern that is the opposite of the test pattern.

If there are input terminals and output terminals connected to the memory, it is possible to inspect all input/output terminals for soldering defects by looking at the signals of the test output terminal and each output terminal not connected to the memory. In the test pattern, the output signal of the AND circuit or OR circuit input to the 2-input selector is a logical value "'1" when the AND circuit is used, and a logical value "φ" when the OR circuit is used.
'', and a pattern in which the logical values of the input terminals not connected to the memory are opposite to the above test pattern one by one.

Embodiment Hereinafter, a test circuit for inspecting soldering defects in a multi-pin LSI according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a multi-pin LSI circuit including a built-in test circuit for inspecting soldering defects in a multi-pin LSI according to an embodiment of the present invention.

In FIG. 1, 1 is a multi-bin LSI. Input terminal 2
．． 3.4.5 are connected to the power supply 12 via resistors 2b, 3b, 4b, and 5b, respectively, and at the same time input buffers 2a,
Connect to each input terminal of 3m, 4a, and 5m. The output of the input buffer 2a is input to the signal processing block 6 and also to the ANO circuit 12. The output of the input buffer 3m is input to the signal processing block 6 and also to the NOT circuit 1.
3 to the AND circuit 12. input buffer 4
The output of m is input to the signal processing block 6 and
It is input to the ND circuit 14. The output of the input buffer 5a is
Input to signal processing block 6 and NOT circuit 15
The signal is inputted to the AND circuit 14 via. The output of the AND circuit 14 is connected to a test output terminal 16. Selector 18
selects the output 18a of the signal processing block 6 and the output of the AND circuit 12, and supplies them to the output terminal 7 from the output flip-flop 7b via the output buffer 7.

The selector 19 selects an output 19a with the signal processing block 6.
The output of the AND circuit 12 is selected by being inverted by the NOT circuit 17, and is applied to the output terminal 8 from the output flip-flop 8b via the output buffer 8a. The selector 20 is
Output 20a with signal processing block 6 and AND circuit 12
is selected and applied to the output terminal 9 from the output flip-flop 9b via the output buffer 9a. selector 21
selects the output 21a of the signal processing block 6 and the output of the AND circuit 12 which are inverted by the NOT circuit 17,
It is applied from the output flip-flop 10b to the output terminal 10 via the output buffer 10a. In addition, output terminal 9.10
are connected to the input terminals 9G and 10c of the memory 11, respectively, and their output terminals 9d and 10d are respectively connected to the input terminal 4.5. Select input signals for the four selectors 18, 19, 20, and 21 are collectively applied from the select input terminal 22.

Regarding the multi-pin LSI circuit configured as described above, which has a built-in test circuit for inspecting soldering defects in the multi-pin LSI,
The operation will be explained below.

First, a case where a multi-pin LSI performs normal operation will be described. In this case, the select input terminal 22 has a logical value "
- by inputting four selectors 18.19.
20.21 to each output terminal 18m of signal processing block 6
, 19m, 120m, and 21m are outputted to each output terminal 7.8.9.10 via each output flip 70 knob 7b, 8b, 9b, 10b and each output buffer 7a, 8a, 9m, 10m.

Next, a case will be described in which a test for inspecting soldering defects is performed. In this case, the select input 22 has a logical value "1".
After inputting, perform the following test.

Test 1: Input logical value "1"≠'' to input terminals 2 and 3, respectively.

Test 2: Input logical values ゛≠'' and ≠'' to input terminals 2 and 3, respectively.

Test 3: Input logic value "1" Jl+ to input terminals 2 and 3, respectively.

In test 1, the input logical value "1" of the input terminal 2 and the logical value "1'" obtained by inverting the input logical value "≠" of the input terminal 3 by the NOT circuit 13 are input to the AND circuit 12, and the AND circuit The output of 12 becomes a logical value "1". Also, since the logical value f'1++ is input to the select input terminal 22, the output of the AND circuit 12 (logical value I+111) is output from the selector 18.20, and the AN
The NOT circuit 17 inverts the output of the D circuit 12 and outputs it (logical value f). The output signals from the output terminals 9 and 10 are given a delay time by the memory 11 and then input to the input terminals 4 and 5, respectively. Therefore, input terminals 4 and 5 receive input signals "1" and "1" respectively. The inverted value (logical value "1") is input by the NOT circuit 15, and the output of the AND circuit 14 is the logical value +
1111, and the test output terminal 16 outputs the logical value "
1". Eventually, as shown in Figure 2, input terminal 2
．． When the logical values ``'1'' and ``≠'' are inputted to the output terminals 7 and 3, respectively, the logical value +1111 ``≠'' is obtained from the output terminals 7 and 8, and the logical value ``1'' is obtained from the test output terminal 16.

AND circuit 1
2, and the output of the AND circuit 12 becomes the logical value "Ou". Also, since the logical value "1" is input to the select input terminal 22, the AND circuit 1 is input from the selector 18.20.
2 output (logical value + 1011) and selector 19
．． 21 outputs the output of the AND circuit 12 which is inverted by the NOT circuit 17 (logical value "1"). As a result, output terminals 7, 8, 9, and 10 each output a logical value ``Q''.
"1" +40 n 1'.

Output. The output signals at the output terminals 9, 10, after being given a delay time in the memory 11, are respectively input to the input terminals 4, 4, .
Enter 5. Therefore, input terminals 4 and 5 each have a logic value of +
+011 1 is input. The AND circuit 14 receives the input signal of the input terminal 4 (logical value "117') and the input signal of the input terminal 5.
The input signal of is inverted by the NOT circuit 15 (logical value "
1'') is input, and the output of the AND circuit 14 is the logical value +10
”, and the test output terminal 16 outputs the logical value “On”. As a result, as shown in FIG. 2, when the logical values +40++ and □ I+ are input to the input terminals 2.3, the output terminals 7.8 output the logical values ``O'' +411+, and the test output terminal 16 outputs the logical values ``O'' and □ I+. The value "O" is obtained.

Furthermore, in test 3, the input logic value RI of input terminal 2
T+ and input logic value "1" of input terminal 3 to NOT circuit 1
The logic value "O"" inverted in step 3 is input to the AND circuit 12, and the output of the AND circuit 12 becomes the logic value II□".The rest of the operation is the same as in test 2, and in the end, the result shown in FIG. As shown, when the logical values ``1'' and 1'' are input to the input terminals 2 and 3, respectively, the output terminals 8 and 11 output the logical values ``1'' and 11, respectively.
'l p4, logic value 140 from test output terminal 16
” is obtained.

In addition, each resistor 2b, 3b, 4b, 5b is connected to each input terminal 2.
．． 3.4.5 to each input buffer 2a, 3.
m, 4a, 5m, and each input terminal 2.3.
When 4.5 is high impedance, each input buffer 2m, 3g, 4a.

The value is set to give a logical value of "1" to 5a.

At least all input terminals other than the power supply, ground, clock input terminal, and free terminals are connected to the power supply 12 through resistors.

Since the above tests 1, 2, and 3 can be performed, all soldering defects can be detected by looking at the signals of output terminals 7 and 8 and test output terminal 16, and if there are any abnormalities in the test results. When a failure occurs, the location of the failure can be predicted to some extent based on the type of test pattern in which the abnormality occurred.

For example, the logical value +1 due to the signal at input terminal 2.
If it continues to be 111, test 2 will show output terminal 7.
8 and the logic of the signal at the test output terminal 16, test 1,
In test 3, the logic values of the signals at the output terminals 7 and 8 and the test output terminal 16 are all opposite to those described above. The signal of input terminal 3 becomes logic value "P1", and terminal 7.8 and test output terminal 1
The logic values of the 6 signals are all the opposite of the above. Also, any one of the signals at the output terminal 9, the input terminal 9c of the memory 11, the output terminal 9d of the memory 11, and the input terminal 4 remains at the logical value "1", so that the signal at the input terminal 4 remains at the logical value. If it remains at the value "1", the logical value of the test output terminal 16 in test 2 and test 3 will be opposite to the above. On the other hand, if the signal at the input terminal 4 remains at logic "φ", the logic value at the test output terminal 16 becomes the opposite of the above-mentioned logic value in test 1.

Output terminal 10, memory 1 input terminal 10C, memory 1
If either the output terminal 10d or the input terminal 5 of 1 remains at the logical value "1", and the signal at the input terminal 5 remains at the logical value "1", test with test 1. The logical value of the signal at the output terminal 16 becomes the opposite of the above,
Conversely, if the signal at the input terminal 5 remains at the logical value ``≠'', the logical value of the signal at the test output terminal 16 becomes the opposite of the above-mentioned value in tests 2 and 3. Also, output terminal 7.8
If there is a defect in the test output terminal 16, an abnormality will appear in the signal of that terminal itself. Furthermore, if any of the input terminals is floating from the printed circuit board, each input terminal is connected to the power supply 12 via a resistor, so the signal at the input terminal remains at a logic value of 1". Furthermore, when inputting the outputs of the input buffers 72m, 3a, 4m, and 5m to the AND circuits 12 and 14, the multi-pin LS1
If the NO7 circuit 13.15 is used to invert the signal and input it to every other input buffer connected to the adjacent input terminals on the same package, the input logical values of the test pattern will be different between the adjacent input terminals ( ``≠'' and ``1''
), it is possible to detect solder contact with the terminal next to the input terminal. Also, each selector 18.19.20.21
When inputting the output of the AND circuit 12 to the
The NO7 circuit 17 connects the output of every other selector to adjacent output terminals on the multi-pin LSI package.
If you invert and input the test pattern using
), it is possible to detect solder contact with the terminal next to the output terminal.

As described above, according to this embodiment, each input terminal 2.3.4
．． 5 is connected to the power supply 12 via resistors 2b, 3b, 4b, and 5b, and the output of the input buffer 2m is connected to the signal processing block 6.
The output of the input buffer 3a is input to the signal processing block 6, and the output of the AND circuit 1/car 4a is input to the signal processing block 6 via the NO7 circuit 13. 14, the output of the input buffer 5a is input to the signal processing block 6, the output is input to the AND circuit 14 via the NO7 circuit 15, the output of the AND circuit 14 is connected to the test output terminal 16, and the output is input to the selector 18. The output 18a of the signal processing block 6 and the output of the AND circuit 12 are selected, and the selector 19 selects the output 191 of the signal processing block 6 and the output of the AND circuit 12 to the NO7 circuit 17.
The selector 20 selects the output 20a of the signal processing block 6 and the output of the AND circuit 12, and the selector 21 selects the output 21a of the signal processing block 6 and the output of the AND circuit 12 to the NO7 circuit 17. to select the inverted item, and use the four selectors 18, 19, 20
, 21 are collectively applied from the select input terminal 22, test 1, test 2, and test 3 can be performed to inspect soldering defects of all input/output terminals of the multi-pin LS 11 and the memory 11. When there is an abnormality in the test result, the location of the defect can be predicted to some extent based on the type of test pattern in which the abnormality occurred.

In the above embodiment, the input terminals that are not connected to the memory 11 are the two input terminals 2 and 3, the input terminals that are connected to the memory 11 are the two input terminals 4 and 5, and the output terminals that are not connected to the memory 11 are the output terminals 7 and 8. The output terminals connected to the memory 11 are the output terminals 9 and 10, but any number of these terminals may be used.If the number of input terminals not connected to the memory increases, the number of inputs to the AND circuit 12 increases. AN if the number of input terminals connected to memory increases
As the number of inputs to the O circuit 14 increases and the number of output terminals increases, the number of selectors also increases. However, the number of tests depends on the number of input terminals that are not connected to memory. That is, in test 1, the output of the AND circuit 12 has a logical value of "1".
Apply an input pattern that makes u+ to an input terminal that is not connected to memory. All that is left to do is to create a pattern in which the logical values of the input terminals that are not connected to the memory are opposite to those in Test 1 for each terminal.

For example, if there are four input terminals that are not connected to memory, the following five test patterns will be used.

Connect each of the four input terminals that are not connected to memory to input terminal A.
If we call it %B%C1O, Test 1: Input terminals A, B, C, [) each have “1 11
Input ``'0'', 1''O''.

Test 2: Input terminals A1 and C1D respectively ", O",
Input 1” Q++.

Test 3: Input terminals A%B%C%D each have "1" and "1",
1. Enter “QO”.

Test 4: Input terminal A. ``1'' JT (
)”, +10+l Q”.

Test 5: “1” and “0” to input terminals A, BSC, and D, respectively.
, °1” fllll+.

Note that the AND circuits 12 and 14 may be configured with an OR circuit.

Effects of the Invention As described above, according to the present invention, there is a signal processing block that performs digital signal processing that is connected to the output terminal of each input buffer when there is no input terminal connected to the memory, and an output terminal of each input buffer, and each input buffer. an AND circuit or an OR circuit connected to the output terminal of the circuit, one or more two-input selectors that receive the output signal of the AND circuit or OR circuit and the output signal of the signal processing block, and one or more two-input selectors for each of the two-input selectors. It is equipped with each output flip-flop connected to the output terminal and a select input terminal for selecting the output of the 2-input selector, and if there are input terminals and output terminals connected to the memory, each input buffer has a signal processing block connected to the output; a first AND circuit or OR circuit connected to the output terminal of each input buffer connected to an input terminal not connected to the memory; and a first AND circuit or OR circuit connected to the output terminal of each input buffer connected to the input terminal not connected to the memory; A second ANC) circuit or OR circuit connected to the output end of the input buffer, a test output terminal connected to the output end of the second AND circuit or OR circuit, and a test output terminal connected to the output end of the first AND circuit or OR circuit. one or more two-input selectors that receive the output signal and the output signal of the signal processing block;
Each output flip-flop connected to the output end of the input selector, each output buffer connected to the output end of each output flip-flop, each output terminal connected to the output end of each output buffer, and the two-input By providing a select input terminal for selecting the output of the selector, it is possible to inspect soldering defects when multi-pin LSI and memory are mounted on a printed circuit board, without knowing the circuit operation of the multi-pin LSI, and without knowing the circuit operation of the multi-pin LSI. This can be done by looking at the signal input/output response using a smaller number of test patterns, and furthermore, when there is an abnormality in the test results, it is possible to predict the defective location to some extent based on the type of test pattern in which the abnormality occurred.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a multi-pin LSI incorporating a test circuit for inspecting soldering defects according to an embodiment of the present invention, Fig. 2 is a logic diagram showing input/output logic in each LSI operation, and Fig. 3 is a circuit diagram of a conventional LSI. It is a circuit diagram of a multi-pin LSI. 1...Multi-pin LSI, 2.3.4.5...
... Input terminal, 21.3m, 4m, 5m ... Input buffer, 2b, 3b, 4b, 5b ... Resistor, 6 ... Signal processing block, 7.8 .9.10
...Output terminal, 7a, 8a19a, 10m...
...Output buffer, 7b, 8b, 9b, 10b...
...Output flip-flop, 9c110c...
...Memory input terminal, 9d. 10d...Memory output terminal, 11...
・Memory, 12.14...AND circuit, 13.
15.17...N07 circuit, 16...
Test output terminal, 18.19.20,21...
・Selector, 18g, 19m. 20a, 21a...Output of signal processing block 6, 22...Select input terminal. Name of agent: Patent attorney Shigetaka Awano and 1 other person 2nd
figure

Claims (5)

[Claims] (1) One or more input terminals, a plurality of input buffers connected to each input terminal, a signal processing block that performs digital signal processing connected to the output terminal of each input buffer, and an output of each input buffer. An AND circuit or OR circuit connected to the terminal, one or more 2-input selectors that receive the output signal of the AND circuit or OR circuit and the output signal of the signal processing block, and an output terminal of each 2-input selector. a plurality of output flip-flops connected to the output terminal, a plurality of output buffers connected to the output terminal of each output flip-flop, a plurality of output terminals connected to the output terminal of each output buffer, and an output of a two-input selector. A test circuit for inspecting soldering defects in a multi-pin LSI, which is equipped with a select input terminal for selecting a terminal. (2) One or more input terminals, multiple input buffers connected to each input terminal, a signal processing block that performs digital signal processing connected to the output terminal of each input buffer, and inputs not connected to memory. A first AND circuit or OR circuit connected to the output terminals of the plurality of input buffers connected to the terminal, and a second AND circuit or OR circuit connected to the output terminals of the plurality of input buffers connected to the input terminal connected to the memory. A
An ND circuit or an OR circuit, a test output terminal connected to an output terminal of a second AND circuit or an OR circuit, an output signal of the first AND circuit or an OR circuit, and an output signal of a signal processing block are input. one or more two-input selectors, a plurality of output flip-flops connected to the output terminal of each two-input selector, a plurality of output buffers connected to the output terminal of each output flip-flop, and each output buffer. A test circuit for inspecting soldering defects in a multi-pin LSI, comprising a plurality of output terminals connected to the output terminal of the 2-input selector, and a select input terminal for selecting the output of a 2-input selector. (3) Among the one or more input terminals, all input terminals other than at least the power supply, ground, clock input terminal, and vacant terminal are connected to the power supply via a resistor.
A test circuit for inspecting soldering defects in a multi-pin LSI according to item 1 or 2. (4) The multi-pin LSI according to claim 1 or 2, wherein the AND circuit or the OR circuit inputs at least one of its inputs by inverting the logical value of the signal from the input terminal. Test circuit for inspecting soldering defects. (5) One or more two-input selectors that receive the output signal of the AND circuit or OR circuit and the output signal of the signal processing block input the inverted output of the AND circuit or OR circuit. A test circuit for inspecting soldering defects in a multi-pin LSI according to claim 1 or 2, which has three or more.