JPH03283599A - Inspecting method for continuity of ceramic multilayer board - Google Patents
Inspecting method for continuity of ceramic multilayer boardInfo
- Publication number
- JPH03283599A JPH03283599A JP2081379A JP8137990A JPH03283599A JP H03283599 A JPH03283599 A JP H03283599A JP 2081379 A JP2081379 A JP 2081379A JP 8137990 A JP8137990 A JP 8137990A JP H03283599 A JPH03283599 A JP H03283599A
- Authority
- JP
- Japan
- Prior art keywords
- continuity
- ceramic multilayer
- check
- wire bonding
- multilayer board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000012360 testing method Methods 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 25
- 239000000523 sample Substances 0.000 abstract description 17
- 238000007689 inspection Methods 0.000 abstract 2
- 230000007257 malfunction Effects 0.000 abstract 1
- 239000011295 pitch Substances 0.000 abstract 1
- 230000002950 deficient Effects 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、セラミック多層基板の導通検査方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for testing continuity of a ceramic multilayer substrate.
(従来の技術)
厚膜多層基板、グリーンシート印刷多層基板、グリーン
シート積層多層基板等のセラミック多層基板においては
、セラミック多層基板パッケージが完成した時点で導通
検査を行っている。(Prior Art) Ceramic multilayer substrates such as thick film multilayer substrates, green sheet printed multilayer substrates, and green sheet laminated multilayer substrates are tested for continuity when the ceramic multilayer substrate package is completed.
例えば、第2図に概略的に示すようなセラミック多層基
板3を導通検査するには、多数のプローブピンをチェッ
ク用端子として有する導通検査用治具を用い、このプロ
ーブピンを、リードパターン4、ワイヤーボンディンン
グパ・ノ、ド5、ダイポンディングパッド6と接触させ
る。そして、導通検査用治具の各プローブピンをそれぞ
れコンピュータ一端末へと接続し、コンピューターに予
め入力しておいた所定のプログラムに従ってプローブピ
ンの組み合わせを選んでチェック用信号を入力し、対応
するワイヤポンディングパッド5とリードパターン4と
の間に導通不良が生じていないかどうかを検査する。な
お、第2図中、7は半導体素子収容部を示す。For example, to conduct a continuity test on a ceramic multilayer board 3 as schematically shown in FIG. Make contact with wire bonding pad No. 5 and die bonding pad 6. Then, each probe pin of the continuity test jig is connected to a computer terminal, a combination of probe pins is selected according to a predetermined program input into the computer, a check signal is input, and the corresponding wire is It is inspected whether there is any conduction failure between the bonding pad 5 and the lead pattern 4. In addition, in FIG. 2, 7 indicates a semiconductor element housing part.
(発明が解決しようとする課題)
しかし、最近ウェーハプロセスの進歩に伴ない、半導体
素子の高集積化、多端子化が急速に進行している。この
ため、チップの寸法を一定に保つべく、ワイヤポンディ
ングパッド5の間隔やリードパターン4の間隔が非常に
小さくなり、ボンディング精度が高まっている。これに
より、導通検査時に、治具のプローブピンを対応するワ
イヤポンディングパッド5やリードパターン4へと正確
に接触させることが困難となりプローブピンとパッド5
やリードパターン4との間で接触不良が発生する。(Problems to be Solved by the Invention) However, with recent advances in wafer processing, semiconductor devices are rapidly becoming more highly integrated and have more terminals. Therefore, in order to keep the dimensions of the chip constant, the intervals between the wire bonding pads 5 and the intervals between the lead patterns 4 have become extremely small, improving bonding accuracy. This makes it difficult to accurately bring the probe pins of the jig into contact with the corresponding wire bonding pads 5 and lead patterns 4 during a continuity test.
A contact failure occurs between the lead pattern 4 and the lead pattern 4.
この結果、導通検査に非常に時間がかかり、しかも、導
通状態のチェックを行えない配線が残ることから適正な
チェックができず、不良品を見逃すおそれがあり、問題
となっている。As a result, the continuity test takes a very long time, and since some wiring remains that cannot be checked for continuity, proper checks cannot be carried out and defective products may be overlooked, which is a problem.
本発明の課題は、セラミック多層基板において、ワイヤ
ポンディングパッド等の半導体素子接続用端子とリード
パターン等の外部接続用端子との間の導通状態のチェッ
クを正確かつ迅速に行えるような、セラミック基板の導
通検査方法を提供することである。An object of the present invention is to provide a ceramic multilayer board that can accurately and quickly check the continuity state between semiconductor element connection terminals such as wire bonding pads and external connection terminals such as lead patterns. An object of the present invention is to provide a continuity testing method.
(課題を解決するための手段)
本発明は、複数のチェック用端子を有する冗長部をセラ
ミック多層基板被検体に設け、前記チェック用端子を外
部接続用端子又は半導体素子接続用端子へと電気的に接
続し、導通検査用治具の端子を前記チェック用端子と接
触させて導通検査を行い、次いで前記冗長部を除去する
ことを特徴とする、セラミック多層基板の導通検査方法
に係るものである。(Means for Solving the Problems) The present invention provides a redundant section having a plurality of check terminals on a ceramic multilayer substrate test object, and electrically connects the check terminals to external connection terminals or semiconductor element connection terminals. The present invention relates to a method for testing continuity of a ceramic multilayer board, the method comprising connecting a terminal of a continuity testing jig to the checking terminal to perform a continuity test, and then removing the redundant portion. .
(実施例)
本実施例においては、まず、第1図に示すように、セラ
ミック多層基板3の両側に冗長部IA、 IBを設けて
セラミック多層基板被検体10を作製する。(Example) In this example, first, as shown in FIG. 1, redundant portions IA and IB are provided on both sides of a ceramic multilayer substrate 3, and a ceramic multilayer substrate test object 10 is manufactured.
各冗長部IA、 IBにはそれぞれ所定個数のチェック
用端子2を設け、各チェック用端子2は、例えば破線A
、Bで示すように、それぞれ対応するワイヤポンディン
グパッド5、リードパターン4へと配線し、電気的に接
続する。冗長部IA、 IBとセラミック多層基板3と
の間には、溝9を設ける。Each redundant part IA, IB is provided with a predetermined number of check terminals 2, and each check terminal 2 is connected to the broken line A, for example.
, B, wires are connected to the corresponding wire bonding pads 5 and lead patterns 4, respectively, and electrically connected. A groove 9 is provided between the redundant parts IA, IB and the ceramic multilayer substrate 3.
この被検体10を製造するには、予め製品であるセラミ
ック多層基板3よりも所定寸法だけ大きいセラミック焼
成基板又はグリーンシートを焼成又は成形しておき、後
は通例の方法に従って絶縁層と導体層とを交互に形成し
、焼成する。この際、従来は、ワイヤポンディングパッ
ド5とリードパターン4との間に所定の配線を設ければ
よいが、本発明においては、更に、例えば破線A、Bで
示すように、チェック用端子2とリードパターン4又は
ワイヤポンディングパッド5との間に、導体パターンに
より配線を設ける。この配線を設けるに際しては、セラ
ミック多層基板3に必要な配線を施した後の空地を利用
し、配線同士が交わらないように設計する。この設計方
法自体は、セラミック多層基板の通例の配線方法を応用
すればよい設計事項である。To manufacture this test object 10, a ceramic fired substrate or green sheet that is larger than the product ceramic multilayer board 3 by a predetermined dimension is fired or formed in advance, and then an insulating layer and a conductive layer are formed in accordance with a usual method. are formed alternately and fired. In this case, conventionally, it is sufficient to provide a predetermined wiring between the wire bonding pad 5 and the lead pattern 4, but in the present invention, as shown by broken lines A and B, for example, a check terminal 2 is provided. Wiring is provided between the lead pattern 4 or the wire bonding pad 5 using a conductive pattern. When providing this wiring, the vacant space after the necessary wiring has been provided on the ceramic multilayer substrate 3 is used, and the wiring is designed so that the wiring does not intersect with each other. This design method itself is a design matter that can be applied by applying the usual wiring method for ceramic multilayer substrates.
ワイヤポンディングパッド5及びリードパターン4のす
べてについて、上記のようにそれぞれ対応するチェック
用端子を設け、配線を施すことも一応可能であるが、む
ろんすべてのリードパターン4及びワイヤポンディング
パッド5についてチェック用端子を設ける必要はない。For all of the wire bonding pads 5 and lead patterns 4, it is possible to provide corresponding check terminals and conduct wiring as described above, but of course, for all of the lead patterns 4 and wire bonding pads 5. There is no need to provide a check terminal.
例えば、ワイヤポンディングパッド5が一定のピッチで
多数設けられている場合には、一つ置き、二つ置きなど
所定間隔をおいて規則的にワイヤポンディングパッド5
を選定し、選定したワイヤポンディングパッド5だけに
ついてチェック用端子2を設け、配線を行ってもよい、
これにより、ワイヤポンディングパッド5(リードパタ
ーン4)と接触すべきプローブピンの本数、密度を下げ
ることができる。For example, if a large number of wire bonding pads 5 are provided at a constant pitch, the wire bonding pads 5 may be placed regularly at predetermined intervals such as every other or every two.
The check terminal 2 may be provided only for the selected wire bonding pad 5, and wiring may be performed.
Thereby, the number and density of probe pins that should come into contact with the wire bonding pad 5 (lead pattern 4) can be reduced.
また、ワイヤポンディングパッド5(又はリードパター
ン4)のうち一部分のみが非常に密集して設けられてい
る場合や、基板のデザイン上の都合などからワイヤポン
ディングパッド5(又はリードパターン4)の一部分に
プローブピンを接触させることが困難となっている場合
もありうる。In addition, if only a portion of the wire bonding pads 5 (or lead patterns 4) are provided very closely, or due to board design considerations, the wire bonding pads 5 (or lead patterns 4) may be There may be cases where it is difficult to bring the probe pin into contact with a portion.
このような場合には、むろん、これらのプローブピンを
接触させることが難しい部分のみについて、ワイヤポン
ディングパッド5(又はリードパターン4)と対応する
チェック用端子を設け、配線を行えばよい。In such a case, of course, it is only necessary to provide check terminals corresponding to the wire bonding pads 5 (or lead patterns 4) and perform wiring only in areas where it is difficult to contact these probe pins.
溝9は被検体の焼成前に予め設けておくとよいが、焼成
後に設けることも可能である。Although it is preferable to provide the groove 9 in advance before firing the test object, it is also possible to provide it after firing.
次いで、被検体10を焼成し、作製した後、図示しない
導通検査用治具を所定位置に配置し、プローブピンをそ
れぞれ対応するワイヤポンディングパッド5、リードパ
ターン4、チェック用端子2に接触させ、導通検査を行
う。この際、プローブピンは予めチェック用端子2のパ
ターンに従って設けておくと共に、チェック用端子2へ
の配線を施したリードパターン4、ワイヤポンディング
パッド5の位置にはプローブピンを設けないようにして
おく。Next, after baking and producing the test object 10, a continuity test jig (not shown) is placed in a predetermined position, and the probe pins are brought into contact with the corresponding wire bonding pads 5, lead patterns 4, and check terminals 2, respectively. , perform a continuity test. At this time, probe pins are provided in advance according to the pattern of the check terminal 2, and probe pins are not provided at the positions of the lead pattern 4 and the wire bonding pad 5 that are wired to the check terminal 2. put.
次いで、予めコンピューターに入力したプログラムに従
って導通状態のチェックを順次行う。このとき、例えば
特定のリードパターン4Aをチェック用端子2Aへと配
線し、特定のワイヤポンディングパッド5Bをチェック
用端子2Bへと配線しておくと、リードパターン4A、
ワイヤポンディングパッド5Bへはプローブピンを接触
させる必要はなく、プローブピンをチェック用端子2A
、 2Bへと接触させて導通不良の有無を調べることで
、リードパターン4Aとワイヤポンディングパッド5B
との導通状態をチェックすることができる。そして、チ
ェック用端子2Aと2Bとの間の導通状態が良好であれ
ば合格とする。また、仮にチェック用端子2Aと2Bと
の導通が不良であるときは、導通検査を一旦終えて後、
リードパターン4A及びワイヤポンディングパッド5B
のみにプローブピンを接触させ、直接導通不良の有無を
調べる。むろん、多数の端子に多数のプローブピンを一
斉に接触させる導通検査とは異なり、特定の端子のみに
プローブピンを確実に接触させることは容易である。こ
れにより、万一チェック用端子2A、 2Bとリードパ
ターン4A又はワイヤポンディングパッド5Bとの間で
導通不良が生じていたとしても、問題は起らない。Next, the continuity state is sequentially checked according to a program input into the computer in advance. At this time, for example, if a specific lead pattern 4A is wired to the check terminal 2A and a specific wire bonding pad 5B is wired to the check terminal 2B, the lead pattern 4A,
There is no need to contact the probe pin with the wire bonding pad 5B, and the probe pin is connected to the check terminal 2A.
, 2B to check for conductivity defects, the lead pattern 4A and the wire bonding pad 5B
You can check the continuity between the If the conduction state between the check terminals 2A and 2B is good, the test is passed. In addition, if the continuity between the check terminals 2A and 2B is poor, after completing the continuity test,
Lead pattern 4A and wire bonding pad 5B
Contact the probe pin to directly check for continuity defects. Of course, unlike a continuity test in which a large number of probe pins are brought into contact with a large number of terminals all at once, it is easy to reliably bring a probe pin into contact with only a specific terminal. Thereby, even if a conduction failure occurs between the check terminals 2A, 2B and the lead pattern 4A or wire bonding pad 5B, no problem will occur.
上記したように、本実施例によれば、たとえリードパタ
ーン4、ワイヤポンディングパッド5のピッチが小さす
ぎること等の理由でプローブピンを確実に接触させるこ
とが困難であっても、リードパターン4、ワイヤポンデ
ィングパッド5とチェック用電極2との間に配線を設け
、チェック用電極2にプローブピンを接触させて導通状
態を検査するので、導通検査を確実に、迅速に行うこと
ができ、不良品の発生を防止できる。As described above, according to this embodiment, even if it is difficult to bring the probe pins into reliable contact with each other due to reasons such as the lead pattern 4 and the wire bonding pad 5 being too small, the lead pattern 4 , a wiring is provided between the wire bonding pad 5 and the check electrode 2, and the continuity state is tested by bringing the probe pin into contact with the check electrode 2, so that the continuity test can be performed reliably and quickly. It is possible to prevent the occurrence of defective products.
次いで、溝9で冗長部IA、 1Bを分離して除去し、
セラミック多層基板3を得る。このとき、人間の手で被
検体10を押えて溝9で割ることができるが、機械で行
ってもよい。Next, the redundant parts IA and 1B are separated and removed by the groove 9, and
A ceramic multilayer substrate 3 is obtained. At this time, the subject 10 can be held down manually and broken by the groove 9, but it may also be done by a machine.
冗長部は第1図に示すように2箇所に設ける必要はなく
、1箇所または3箇所以上でもよく、形状も変更してよ
い。The redundant portions do not need to be provided at two locations as shown in FIG. 1, but may be provided at one location or three or more locations, and the shape may also be changed.
本発明は各種のセラミック多層基板、例えば厚膜多層基
板、グリーンシート印刷多層基板、グリーンシート積層
多層基板、厚膜/Wl膜の組み合わせ基板、CR入り基
板、低温焼成型セラミック基板、低収縮率基板等に適用
可能である。The present invention is applicable to various ceramic multilayer substrates, such as thick film multilayer substrates, green sheet printed multilayer substrates, green sheet laminated multilayer substrates, thick film/Wl film combination substrates, CR-containing substrates, low temperature firing ceramic substrates, and low shrinkage rate substrates. It is applicable to etc.
(発明の効果)
本発明に係るセラミック多層基板の導通検査方法によれ
ば、冗長部のチェック用端子を外部接続用端子又は半導
体素子接続用端子へと電気的に接続し、導通検査用治具
の端子をチェック用端子と接触させて導通検査を行うの
で、外部接続用端子又は半導体素子接続用端子のピッチ
が小さすぎること等の理由で上記治具の端子を外部接続
用端子又は半導体素子接続用端子へと確実に接触させる
ことが困難な場合にも、上記治具の端子をチェック用端
子へと接触させればチェックを行える。従って、導通検
査を確実、迅速に行うことができ、不良品の発生を防止
できる。(Effects of the Invention) According to the method for testing continuity of a ceramic multilayer board according to the present invention, the check terminal of the redundant portion is electrically connected to the external connection terminal or the semiconductor element connection terminal, and the continuity test jig is used. Since the continuity test is performed by bringing the terminals of the above jig into contact with the check terminals, if the pitch of the external connection terminals or semiconductor element connection terminals is too small, etc. Even if it is difficult to reliably contact the check terminal, the check can be performed by bringing the terminal of the jig into contact with the check terminal. Therefore, the continuity test can be performed reliably and quickly, and the occurrence of defective products can be prevented.
第1図はセラミック多層基板被検体を示す概略平面図、
第2図はセラミック多層基板を示す概略平面図である。
IA、 IB・・・冗長部
2、2A、 2B・・・チェック用端子3・・・セラミ
ック多層基板
4.4A・・・リードパターン(外部接続用端子)5.
5B・・・ワイヤポンディングパッド(半導体素子接続
用端子)
6・・・ダイポンディングパッド
9・・・溝
10・・・セラミック多層基板被検体FIG. 1 is a schematic plan view showing a ceramic multilayer substrate to be tested, and FIG. 2 is a schematic plan view showing the ceramic multilayer substrate. IA, IB...Redundant parts 2, 2A, 2B...Check terminal 3...Ceramic multilayer board 4.4A...Lead pattern (terminal for external connection)5.
5B... Wire bonding pad (semiconductor element connection terminal) 6... Die bonding pad 9... Groove 10... Ceramic multilayer board test object
Claims (1)
多層基板被検体に設け、前記チェック用端子を外部接続
用端子又は半導体素子接続用端子へと電気的に接続し、
導通検査用治具の端子を前記チェック用端子と接触させ
て導通検査を行い、次いで前記冗長部を除去することを
特徴とする、セラミック多層基板の導通検査方法。1. A redundant part having a plurality of check terminals is provided on the ceramic multilayer substrate test object, and the check terminals are electrically connected to an external connection terminal or a semiconductor element connection terminal,
A method for testing continuity of a ceramic multilayer board, comprising: performing a continuity test by bringing a terminal of a continuity test jig into contact with the check terminal, and then removing the redundant portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2081379A JPH03283599A (en) | 1990-03-30 | 1990-03-30 | Inspecting method for continuity of ceramic multilayer board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2081379A JPH03283599A (en) | 1990-03-30 | 1990-03-30 | Inspecting method for continuity of ceramic multilayer board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03283599A true JPH03283599A (en) | 1991-12-13 |
Family
ID=13744669
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2081379A Pending JPH03283599A (en) | 1990-03-30 | 1990-03-30 | Inspecting method for continuity of ceramic multilayer board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03283599A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6249114B1 (en) | 1997-08-25 | 2001-06-19 | Nec Corporation | Electronic component continuity inspection method and apparatus |
JP2007035739A (en) * | 2005-07-25 | 2007-02-08 | Murata Mfg Co Ltd | Circuit board and circuit board manufacturing method |
JP2012064869A (en) * | 2010-09-17 | 2012-03-29 | Toshiba Hokuto Electronics Corp | Method of manufacturing flexible printed wiring board |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6149470B2 (en) * | 1979-03-29 | 1986-10-29 | Ishikawajima Harima Heavy Ind | |
JPS6210468B2 (en) * | 1977-05-25 | 1987-03-06 | Hitachi Ltd |
-
1990
- 1990-03-30 JP JP2081379A patent/JPH03283599A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6210468B2 (en) * | 1977-05-25 | 1987-03-06 | Hitachi Ltd | |
JPS6149470B2 (en) * | 1979-03-29 | 1986-10-29 | Ishikawajima Harima Heavy Ind |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6249114B1 (en) | 1997-08-25 | 2001-06-19 | Nec Corporation | Electronic component continuity inspection method and apparatus |
JP2007035739A (en) * | 2005-07-25 | 2007-02-08 | Murata Mfg Co Ltd | Circuit board and circuit board manufacturing method |
JP2012064869A (en) * | 2010-09-17 | 2012-03-29 | Toshiba Hokuto Electronics Corp | Method of manufacturing flexible printed wiring board |
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