JP2007035739A - Circuit board and circuit board manufacturing method - Google Patents

Circuit board and circuit board manufacturing method Download PDF

Info

Publication number
JP2007035739A
JP2007035739A JP2005213756A JP2005213756A JP2007035739A JP 2007035739 A JP2007035739 A JP 2007035739A JP 2005213756 A JP2005213756 A JP 2005213756A JP 2005213756 A JP2005213756 A JP 2005213756A JP 2007035739 A JP2007035739 A JP 2007035739A
Authority
JP
Japan
Prior art keywords
circuit board
circuit
insulating layer
electrode
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005213756A
Other languages
Japanese (ja)
Other versions
JP4839713B2 (en
Inventor
Kazuyuki Yuda
和之 湯田
Tsutomu Iegi
勉 家木
Makoto Kawagishi
誠 河岸
Hiroki Kawabata
宏樹 河端
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2005213756A priority Critical patent/JP4839713B2/en
Publication of JP2007035739A publication Critical patent/JP2007035739A/en
Application granted granted Critical
Publication of JP4839713B2 publication Critical patent/JP4839713B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board and a manufacturing method of the same circuit board for realizing size reduction and high density of circuit board, accurately testing natural circuit wires for propagating high-frequency signals in the course of the board manufacturing process, assuring higher application efficiency of electronic components to be embedded in the circuit board, removing restrictions on the manufacturing process, and improving the board manufacturing yield. <P>SOLUTION: The circuit board 21 comprises a flexible board 25 provided with the projected portions 31A, 31B projected more than a laminating part 32, and insulating layers 22A, 22B embedding electronic components. A monitor electrode for testing of the predetermined area is provided at the area guided from the adjacent area of the natural circuit wires in the circuit structure for propagating high-frequency signals. The flexible board circuit wires are provided up to the projected areas 31A, 31B from the circuit structure for propagating low-frequency signals, and these are connected with contact electrodes 27A, 27B for testing at the projected areas 31A, 31B. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は、回路基板の構造および製造方法に関するものである。   The present invention relates to a structure of a circuit board and a manufacturing method.

従来、MCM(マルチチップモジュール)の小型化や高密度化の要求に対応するために、絶縁層の内部に電子部品を埋設し、さらにその絶縁層を積層した回路基板が提供されている(特許文献1参照。)。   Conventionally, in order to meet the demand for miniaturization and high density of MCM (multi-chip module), a circuit board is provided in which an electronic component is embedded in an insulating layer and the insulating layer is laminated (patent). Reference 1).

ここで特許文献1を参考にした回路基板の構成を図1に示す。回路基板11は、複数の絶縁層12を積層してなる。絶縁層12の一部には複数の電子部品13が埋設され、複数の絶縁層12の層間には電子部品13同士を接続する回路配線が設けられる。また、異なる層間の回路配線同士を接続する絶縁層ビアホール14を各絶縁層12に設ける。   Here, the configuration of a circuit board with reference to Patent Document 1 is shown in FIG. The circuit board 11 is formed by laminating a plurality of insulating layers 12. A plurality of electronic components 13 are embedded in part of the insulating layer 12, and circuit wiring for connecting the electronic components 13 is provided between the plurality of insulating layers 12. Insulating layer via holes 14 for connecting circuit wirings between different layers are provided in each insulating layer 12.

このような回路基板11では、回路基板11自体を小型化、高密度化でき、電子部品13間を接続する回路配線長を短縮化できる。この短縮化により、例えばマイクロ波帯やミリ波帯の高周波信号を扱った場合に回路配線に起因する寄生成分(寄生インダクタンス、寄生キャパシタンス)を抑制できる。   In such a circuit board 11, the circuit board 11 itself can be miniaturized and densified, and the circuit wiring length connecting the electronic components 13 can be shortened. This shortening can suppress parasitic components (parasitic inductance, parasitic capacitance) caused by circuit wiring when a high frequency signal in, for example, a microwave band or a millimeter wave band is handled.

しかしながら、このような回路基板11では、電子部品13のような回路素子を絶縁層12に埋設した後では内部の回路配線に検査用のプローブを当接してプロービングすることができず、部分的な電気特性の検査や、結線状態または電子部品実装状態の確認が困難であった。   However, in such a circuit board 11, after a circuit element such as the electronic component 13 is embedded in the insulating layer 12, the probe for inspection cannot be brought into contact with the internal circuit wiring for probing. It was difficult to check the electrical characteristics and confirm the connection state or electronic component mounting state.

また、回路基板の製造途中で検査を行うことができないため、製造途中で不具合が発生したとしても最終工程でしか確認ができず、無駄な工程費用が発生するとともに、歩留を低下させる可能性があった。   In addition, since inspection cannot be performed in the middle of manufacturing a circuit board, even if a failure occurs during manufacturing, it can be confirmed only in the final process, resulting in unnecessary process costs and a decrease in yield. was there.

また、内装した電子部品13から回路基板11の表面にまで検査用の電極を引き出してプロービングすることも可能であるが、このような検査用電極を設けると回路基板11の小型化や高密度化の要求に反して回路面積が増大するため、望ましいものではなかった。   In addition, it is possible to carry out probing by pulling out an inspection electrode from the built-in electronic component 13 to the surface of the circuit board 11, but if such an inspection electrode is provided, the circuit board 11 can be reduced in size and density. This is not desirable because the circuit area increases against this requirement.

一方、可撓性基板であるフレキシブル基板に突出する突出部を設け、その突出部に検査用電極を設けて(以下、このように突出部に設けた検査用電極をコンタクト電極という。)プロービングすることで、結線状態または回路動作の確認を可能とする技術が公知である(特許文献2参照。)。   On the other hand, a protruding portion is provided on a flexible substrate, which is a flexible substrate, and an inspection electrode is provided on the protruding portion (hereinafter, the inspection electrode provided on the protruding portion is referred to as a contact electrode) for probing. Thus, a technique that enables confirmation of a connection state or circuit operation is known (see Patent Document 2).

ここで特許文献2を参考にしたフレキシブル基板の構成を図2に示す。リジッド部(積層部)1および2は複数のフレキシブル基板を多層化して構成することにより屈曲しにくくした部分であり、フレックス部(突出部)3は単層のフレキシブル基板で構成することにより、屈曲しやすくした部分である。このリジッド部(積層部)1および2は、突出部3により結合している。リジッド部(積層部)1および2の表面には、電子部品5,6,7,8を搭載している。また、リジッド部(積層部)1および2の内部の回路から突出部3まで引出線を設け、引出線の先端に電気特性検査用のコンタクト電極4を設けている。これによりコンタクト電極4にプローブを当接してプロービングすることで、結線状態または回路動作の確認や電気特性の検査が可能になるとともに、リジッド部(積層部)1および2の回路面積の抑制が可能になる。なお、この方式において、リジッド部(積層部)を部品内蔵基板として構成することも可能である。
特開2002−280744号公報 特開2000−59032号公報
Here, the configuration of the flexible substrate with reference to Patent Document 2 is shown in FIG. Rigid portions (laminated portions) 1 and 2 are portions that are made difficult to bend by forming a plurality of flexible substrates in layers, and flex portions (projecting portions) 3 are bent by being formed from a single-layer flexible substrate. It is the part that made it easy to do. The rigid portions (laminated portions) 1 and 2 are connected by a protruding portion 3. Electronic parts 5, 6, 7, and 8 are mounted on the surfaces of the rigid parts (laminated parts) 1 and 2. Further, a lead wire is provided from the circuit inside the rigid portions (laminated portions) 1 and 2 to the projecting portion 3, and a contact electrode 4 for electrical property inspection is provided at the tip of the lead wire. As a result, the probe is brought into contact with the contact electrode 4 to perform probing, so that it is possible to check the connection state or circuit operation and to inspect the electrical characteristics, and to suppress the circuit area of the rigid parts (laminated parts) 1 and 2. become. In this system, the rigid portion (laminated portion) can be configured as a component built-in substrate.
JP 2002-280744 A JP 2000-59032 A

しかしながら、特許文献2においては、コンタクト電極には本来の回路配線から突出部までにある程度の長さの引出線が必要となる。この長い引出線は、仮に計測点が高周波回路である場合には、引出線自体の寄生成分(寄生インダクタンスや寄生キャパシタンス)が生じ、検査結果や回路特性に影響を及ぼすものであった。また、複数のリジッド部(積層部)を結合するようにフレックス部(突出部)を設けてしまうと、フレックス部(突出部)自体のサイズの分だけ基板サイズが増大することになっていた。   However, in Patent Document 2, a certain length of lead wire is required for the contact electrode from the original circuit wiring to the protruding portion. If the measurement point is a high-frequency circuit, this long lead wire has a parasitic component (parasitic inductance or parasitic capacitance) of the lead wire itself, which affects the inspection result and circuit characteristics. Further, if a flex part (protrusion part) is provided so as to connect a plurality of rigid parts (laminate parts), the substrate size is increased by the size of the flex part (protrusion part) itself.

また、コンタクト電極を設ける場合には、突出部とコンタクト電極とを設けた後でしかプロービングできないため、製造工程(工程設計)に制約があった。したがってフレックス部(突出部)を設ける前に不具合が生じた場合には、フレックス部(突出部)とコンタクト電極の形成を待ってプロービングを行い、初めて不具合を察知するしか無く、電子部品の利用効率や製造工程の良品率が低下する可能性があった。   Further, when the contact electrode is provided, the probing can be performed only after the protrusion and the contact electrode are provided, so that the manufacturing process (process design) is restricted. Therefore, if a problem occurs before the flex part (protrusion part) is provided, probing must be performed after the flex part (protrusion part) and the contact electrode are formed, and the first time the problem is detected. And there was a possibility that the non-defective product rate in the manufacturing process was lowered.

そこで、本発明の目的は、回路基板の小型化や高密度化を実現しながら、基板製造工程途中で高周波信号の電気特性の正確な検査や結線状態、または電子部品実装状態の確認などができ、また、回路基板に埋設する電子部品の利用効率が高く、さらに製造工程に制約がなく、基板製造歩留を向上できる回路基板および回路基板製造方法を提供することにある。   Therefore, the object of the present invention is to accurately check the electrical characteristics of high-frequency signals, check the connection state, or check the electronic component mounting state in the middle of the board manufacturing process while realizing the miniaturization and high density of the circuit board. Another object of the present invention is to provide a circuit board and a circuit board manufacturing method capable of improving the board manufacturing yield with high use efficiency of electronic components embedded in the circuit board, without restrictions on the manufacturing process.

上記課題を解決するために本発明の回路基板は、複数の絶縁層を積層した積層部を備え、前記積層部の絶縁層間に回路配線を設けた回路基板であって、前記複数の絶縁層のうち少なくとも1つの絶縁層に、その面方向に前記積層部から突出する突出部を設け、前記回路配線に接続された検査用電極を、前記突出部および前記積層部のそれぞれの表面に設けたことを特徴とする。   In order to solve the above problems, a circuit board according to the present invention is a circuit board having a laminated portion in which a plurality of insulating layers are laminated, and circuit wiring is provided between the insulating layers of the laminated portion. At least one insulating layer is provided with a protruding portion protruding from the laminated portion in the surface direction, and an inspection electrode connected to the circuit wiring is provided on each surface of the protruding portion and the laminated portion. It is characterized by.

このように、積層部と突出部とを設け、突出部に検査用電極(コンタクト電極)を設けるとともに、積層部にも検査用電極(以下、モニタ電極)を設けることで、回路基板の積層部の小型化と高密度化を最大限に図りながら、これらの検査用電極を用いてプロービングできる。したがって、電子部品に対する電気特性の検査や、結線状態または電子部品実装状態の確認が容易にできる。例えば、積層部にモニタ電極を設けるために回路基板の面積を大きくする必要がある場合には、その計測点については突出部にコンタクト電極を設ければよい。また、積層部にモニタ電極を設けても回路基板の面積を大きくする必要がない場合には、そのまま積層部にモニタ電極を設ければよい。このように状況に応じてモニタ電極とコンタクト電極とを使い分けることで、積層部の小型化と高密度化を最大限に図ることができる。   As described above, the laminated portion and the protruding portion are provided, the inspection electrode (contact electrode) is provided on the protruding portion, and the inspection electrode (hereinafter referred to as a monitor electrode) is provided on the laminated portion. Probing can be performed using these inspection electrodes while minimizing the size and increasing the density. Therefore, it is possible to easily check the electrical characteristics of the electronic component and confirm the connection state or the electronic component mounting state. For example, when it is necessary to increase the area of the circuit board in order to provide the monitor electrode in the stacked portion, the contact electrode may be provided in the protruding portion for the measurement point. Further, if it is not necessary to increase the area of the circuit board even if the monitor electrode is provided in the laminated portion, the monitor electrode may be provided in the laminated portion as it is. Thus, by properly using the monitor electrode and the contact electrode according to the situation, it is possible to maximize the miniaturization and density of the laminated portion.

なお、突出部の機能が検査機能だけで、コンタクト電極と引出線のみが形成されている場合には、突出部を切断することで基板サイズを抑制できる。また、必ずしも突出部を切断しなくともよく、その場合には突出部に他の回路を設けて利用したり、コンタクト電極を外部接続端子として利用したりすると好適である。
なお、モニタ電極を本来の回路配線から近接して引き出したところに設け、その大きさを、確実にプロービングできる大きさ、例えばプローブ先端と略同面積にする。このようにすることで引出線の寄生成分(寄生インダクタンス、寄生キャパシタンス)を抑制し、回路特性、特に高周波特性を正確に測定できる。また、モニタ電極にプロービングによるプローブ痕が発生しても、本来の回路配線や回路特性に影響を与えることがない。さらに、このようにモニタ電極の大きさを抑制することで基板(製品)サイズを抑制できる。
In addition, when the function of the protrusion is only the inspection function and only the contact electrode and the lead line are formed, the substrate size can be suppressed by cutting the protrusion. In addition, it is not always necessary to cut the protruding portion. In that case, it is preferable to use the protruding portion by providing another circuit or to use the contact electrode as an external connection terminal.
The monitor electrode is provided at a position where it is drawn close to the original circuit wiring, and the size thereof is set to a size that can be reliably probed, for example, approximately the same area as the probe tip. By doing so, parasitic components (parasitic inductance, parasitic capacitance) of the leader line can be suppressed, and circuit characteristics, particularly high frequency characteristics can be accurately measured. Further, even if probe marks are generated by probing on the monitor electrode, the original circuit wiring and circuit characteristics are not affected. Furthermore, the size of the substrate (product) can be suppressed by suppressing the size of the monitor electrode in this way.

また、上記課題を解決するために本発明の回路基板では、前記回路配線は、高周波信号が伝搬する高周波回路部と、低周波信号が伝搬する低周波回路部とを備え、高周波回路部用の検査用電極を前記積層部の表面にのみ設けることを特徴とし、低周波回路部用の検査用電極は場合に応じて前記突出部の表面、または前記積層部と前記突出部の両方の表面に設ける。   In order to solve the above problems, in the circuit board of the present invention, the circuit wiring includes a high-frequency circuit unit through which a high-frequency signal propagates and a low-frequency circuit unit through which a low-frequency signal propagates. The inspection electrode is provided only on the surface of the laminated portion, and the inspection electrode for the low frequency circuit portion is provided on the surface of the protruding portion or both the surface of the laminated portion and the protruding portion depending on the case. Provide.

このようにして、回路基板の小型化と高密度化を最大限に図りながら、特に高周波回路部では引出線による寄生成分が生じることを抑制できる。これにより、本来の回路構成の高周波特性の検査や、結線状態または電子部品実装状態の確認ができる。また、低周波回路部のプロービングには場合により、コンタクト電極とモニタ電極とを適宜使い分けて設けることで、回路基板の積層部の小型化と高密度化を実現できる。   In this way, it is possible to suppress the occurrence of parasitic components due to lead lines, particularly in the high-frequency circuit section, while minimizing the size and density of the circuit board. As a result, the high frequency characteristics of the original circuit configuration can be inspected, and the connection state or electronic component mounting state can be confirmed. Further, when probing the low-frequency circuit unit, the contact electrode and the monitor electrode are appropriately used as appropriate, so that the stacked portion of the circuit board can be reduced in size and density.

また、上記課題を解決するために本発明の回路基板は、前記回路配線に接続された電子部品を備え、該電子部品を前記積層部に埋設した。
ここで本発明の電子部品とは、半導体やチップ部品だけではなく、印刷抵抗などの素子を含むものである。
In order to solve the above problems, a circuit board according to the present invention includes an electronic component connected to the circuit wiring, and the electronic component is embedded in the stacked portion.
Here, the electronic component of the present invention includes not only a semiconductor and a chip component but also an element such as a printed resistor.

これにより、回路基板のさらなる小型化や高密度化が可能となり、電子部品間を接続する回路配線長を短縮化することができる。この短縮化を行うことと高周波回路部にモニタ電極のみを設けることにより、回路配線に起因する寄生成分の発生をさらに抑制でき、マイクロ波帯やミリ波帯の高周波信号の場合でも本来の回路特性を正確に測定できる。   As a result, the circuit board can be further reduced in size and density, and the length of the circuit wiring connecting the electronic components can be shortened. This shortening and the provision of only monitor electrodes in the high-frequency circuit block can further suppress the generation of parasitic components due to circuit wiring, and the original circuit characteristics even in the case of high-frequency signals in the microwave band and millimeter wave band Can be measured accurately.

また、電子部品を回路基板に埋設した後であっても、その電子部品から突出部まで引き出したコンタクト電極や積層部表面に設けたモニタ電極を用いてプロービングできる。   Further, even after the electronic component is embedded in the circuit board, it is possible to perform probing using a contact electrode drawn from the electronic component to the protruding portion or a monitor electrode provided on the surface of the laminated portion.

また、単一の電子部品にコンタクト電極とモニタ電極を共に設けておくと、電子部品を回路基板に埋設する前の工程ではモニタ電極を用い、埋設後には電子部品と共に埋設されるモニタ電極ではなくコンタクト電極を用いることで、プロービングできる。これにより、プロービングを行う工程がコンタクト電極を形成する工程よりも前工程でも後工程でもよくなり、製造工程から制約をなくすことができる。   In addition, if both a contact electrode and a monitor electrode are provided in a single electronic component, the monitor electrode is used in the process before embedding the electronic component in the circuit board, and after the embedding, the monitor electrode is not embedded with the electronic component. Probing is possible by using contact electrodes. As a result, the probing process may be performed before or after the process of forming the contact electrode, and restrictions can be eliminated from the manufacturing process.

また、上記課題を解決するために本発明の回路基板においては、前記突出部を設けた絶縁層は可撓性基板からなる。   In order to solve the above problems, in the circuit board of the present invention, the insulating layer provided with the projecting portion is made of a flexible substrate.

このように、可撓性基板(例えばフレキシブル基板など)で突出部を構成するために、この突出部を屈曲させることができる。また、一般的な可撓性基板は加工が容易であるため、突出部を除去することも容易となる。   As described above, in order to form the protruding portion with a flexible substrate (for example, a flexible substrate), the protruding portion can be bent. In addition, since a general flexible substrate is easy to process, it is easy to remove the protruding portion.

また、上記課題を解決するために本発明の回路基板は、前記突出部を設けた絶縁層の両主面に前記回路配線を配し、前記突出部に前記両主面の回路配線間を接続するビアホールを設ける。   Further, in order to solve the above problems, the circuit board of the present invention has the circuit wiring arranged on both main surfaces of the insulating layer provided with the projecting portion, and the circuit wiring on both main surfaces is connected to the projecting portion. A via hole is provided.

このように、前記突出部を設けた絶縁層の両主面のそれぞれに回路配線を設けることで、この突出部を設けた絶縁層を、他の絶縁層の中間に配置することができ、回路基板の一部として構成できる。また、前記突出部の両主面に回路配線を設け、さらにその回路配線間を接続するビアホールを設けることで、より多くのコンタクト電極を設けることができる。   Thus, by providing circuit wiring on each of the two main surfaces of the insulating layer provided with the protruding portion, the insulating layer provided with the protruding portion can be disposed in the middle of other insulating layers, It can be configured as part of the substrate. Further, more contact electrodes can be provided by providing circuit wirings on both main surfaces of the protruding portion and further providing via holes for connecting the circuit wirings.

また、上記課題を解決するために本発明の回路基板は、前記突出部を複数の絶縁層に設け、その絶縁層ごとに突出部のサイズをそれぞれ異ならせてなる。   In order to solve the above-mentioned problem, the circuit board of the present invention is configured such that the protrusions are provided in a plurality of insulating layers, and the sizes of the protrusions are different for each insulating layer.

このように複数の突出部を設け、それぞれの突出部の大きさを異ならせることにより、プローブを当接させる際にそれぞれの突出部同士が干渉せず、多くのプローブを同時に当接させることができる。   In this way, by providing a plurality of protrusions and varying the sizes of the protrusions, the protrusions do not interfere with each other when the probes are brought into contact with each other, and many probes can be brought into contact at the same time. it can.

また、上記課題を解決するために本発明の回路基板は、前記突出部を前記積層部との境界付近で切断し、その切断した面を絶縁材でコーティングしてなる。   In order to solve the above problems, the circuit board according to the present invention is formed by cutting the projecting portion near the boundary with the laminated portion and coating the cut surface with an insulating material.

このように突出部を切断することで基板(製品)サイズを抑制できる。また、その切断した面を絶縁材でコーティングすることで、モニタ電極の引出線の切断部分を絶縁でき、実際の製品として好適なものとなる。   The substrate (product) size can be suppressed by cutting the protruding portion in this way. Also, by coating the cut surface with an insulating material, the cut portion of the lead wire of the monitor electrode can be insulated, which is suitable as an actual product.

また、上記課題を解決するために本発明の回路基板製造方法は、回路基板を製造する工程と、前記検査用電極に検査用のプローブを当接して電気特性、結線状態、または電子部品実装状態を検査する工程と、を順に実行する。   In order to solve the above problems, a circuit board manufacturing method according to the present invention includes a circuit board manufacturing process, and an inspection probe abutting on the inspection electrode so that an electrical characteristic, a connection state, or an electronic component mounting state Are sequentially performed.

このように、突出部を備えた回路基板を製造し、さらにその突出部のコンタクト電極にプローブを当接させて基板仕上がり状態を検査することで、小型化と高密度化を実現した回路基板であっても、電気特性の検査や、結線状態または電子部品実装状態を確認した製品を製造できる。   In this way, a circuit board with a protrusion is manufactured, and further, the probe is brought into contact with the contact electrode of the protrusion to inspect the finished state of the circuit board, thereby reducing the size and increasing the density of the circuit board. Even if it exists, the product which checked the electrical property and confirmed the connection state or the electronic component mounting state can be manufactured.

また、上記課題を解決するために本発明の回路基板製造方法は、回路基板を製造する工程で、前記複数の絶縁層のうち所定の絶縁層に設けた検査用電極に検査用のプローブを当接して電気特性、結線状態、または電子部品実装状態を検査し、その後、前記検査用電極を設けた絶縁層に他の絶縁層を積層する。   In order to solve the above-described problem, the circuit board manufacturing method of the present invention applies a test probe to a test electrode provided on a predetermined insulating layer among the plurality of insulating layers in the process of manufacturing the circuit board. The electrical characteristics, the connection state, or the electronic component mounting state are inspected in contact with each other, and then another insulating layer is laminated on the insulating layer provided with the inspection electrode.

このように、回路基板を製造する工程中で、プロービングを行い、基板仕上がり状態を検査することで、小型化と高密度化を実現した回路基板を、電気特性、結線状態、または電子部品実装状態を確実に確認しながら製造するので基板製造歩留を向上できる。   In this way, in the process of manufacturing a circuit board, probing and inspecting the board finish state, the circuit board that has been reduced in size and increased in density, electrical characteristics, connection state, or electronic component mounting state Therefore, the substrate manufacturing yield can be improved.

また製造工程中に基板仕上がり状態の検査を行うため、不具合の発生を速やかに察知することができ、不具合箇所や不具合工程を容易に把握できるため対策が早い段階で行える。さらに、その後工程において、電子部品が無駄に消費されることを防いで、電子部品の利用効率を高めることができる。   In addition, since the substrate finish state is inspected during the manufacturing process, it is possible to quickly detect the occurrence of a defect and to easily grasp the defective part and the defective process, so that measures can be taken at an early stage. Further, in the subsequent process, it is possible to prevent the electronic components from being wasted and to increase the use efficiency of the electronic components.

また、上記課題を解決するために本発明の回路基板製造方法は、上述の工程の後で、前記突出部を切断し、その切断した面を絶縁材でコーティングする。   Moreover, in order to solve the said subject, the circuit board manufacturing method of this invention cut | disconnects the said protrusion part after the above-mentioned process, and coats the cut | disconnected surface with an insulating material.

このため、小型化と高密度化を実現した回路基板であっても、製造歩留が高く、かつ、製品形態として好適な回路基板を製造できる。   For this reason, even if it is a circuit board which implement | achieved size reduction and high density, a manufacturing yield is high and a circuit board suitable as a product form can be manufactured.

本発明によれば、回路基板の小型化や高密度化を実現し、高周波信号の伝搬する回路配線であっても検査用の引出線や電極の影響のない状態で高周波特性や結線状態、または電子部品実装状態を正確に検査することができる。また、基板製造工程中に仕上がり状態を検査するので、不具合箇所や不具合工程を容易に把握でき、早い段階で対策が行えるとともに、回路基板に搭載する電子部品の利用効率を高くすることができ、さらに製造工程から制約を除くことができる。   According to the present invention, the circuit board can be miniaturized and densified, and even in the case of circuit wiring through which a high-frequency signal propagates, high-frequency characteristics and connection state without being affected by the lead wire or electrode for inspection, or The electronic component mounting state can be accurately inspected. In addition, since the finished state is inspected during the board manufacturing process, it is possible to easily grasp the defective part and the defective process, to take measures at an early stage, and to increase the utilization efficiency of the electronic components mounted on the circuit board, Furthermore, restrictions can be removed from the manufacturing process.

本発明の第1の実施形態を図3〜6に基づいて説明する。
図3は、本実施形態の回路基板である。本実施形態の回路基板は、突出部を備えたフレキシブル基板を、2つの絶縁層により狭持した構成である。図3(A)は、この回路基板の積層方向の断面図(図3(B)のAA′断面図)であり、図3(B)は、その回路基板を積層方向(図3(A)上方向)から見た上面図であり、図3(C)は、その回路基板に用いられているフレキシブル基板のみを積層方向(図3(A)上方向)から見た上面図である。
なお、これらの図では絶縁層22Aについて主に記号を付して説明し、絶縁層22Bについては説明を省く。なお、絶縁層22Bは記号を付していないが、絶縁層22Aと類似の構成である。
A first embodiment of the present invention will be described with reference to FIGS.
FIG. 3 is a circuit board according to this embodiment. The circuit board of the present embodiment has a configuration in which a flexible board having a protruding portion is held between two insulating layers. 3A is a cross-sectional view of this circuit board in the stacking direction (cross-sectional view along AA ′ in FIG. 3B), and FIG. 3B is a cross-sectional view of the circuit board in the stacking direction (FIG. 3A). FIG. 3C is a top view of only the flexible substrate used in the circuit board as seen from the stacking direction (upward direction in FIG. 3A).
In these drawings, the insulating layer 22A is mainly described with reference symbols, and the insulating layer 22B is not described. The insulating layer 22B has no symbol, but has a configuration similar to that of the insulating layer 22A.

図3(A)に示すフレキシブル基板25は、エポキシ材やポリイミドなどの材料からなる薄板状の基材からなり、その両主面には、フレキシブル基板回路配線26(26A〜26C)を形成している。さらにその両主面のフレキシブル基板回路配線26(26A〜26C)を覆うように略全面に絶縁性の被膜を設け、この絶縁性の被膜の一部からフレキシブル基板回路配線26(26A〜26C)を露出させて、露出した部分をコンタクト電極27(27A,27B)および接続用電極29(29A〜29C)としている。また、フレキシブル基板25内部にはフレキシブル基板ビアホール35(35A,35B)を設けており、このフレキシブル基板ビアホール35(35A,35B)により上主面側と下主面側のフレキシブル基板回路配線26(26A〜26C)同士を導通する。   A flexible substrate 25 shown in FIG. 3A is made of a thin plate-like base material made of a material such as an epoxy material or polyimide, and flexible substrate circuit wirings 26 (26A to 26C) are formed on both main surfaces thereof. Yes. Further, an insulating film is provided on substantially the entire surface so as to cover the flexible substrate circuit wirings 26 (26A to 26C) on both main surfaces, and the flexible substrate circuit wiring 26 (26A to 26C) is formed from a part of the insulating coating. The exposed portions are used as contact electrodes 27 (27A, 27B) and connection electrodes 29 (29A to 29C). Further, flexible substrate via holes 35 (35A, 35B) are provided inside the flexible substrate 25, and the flexible substrate circuit wirings 26 (26A) on the upper main surface side and the lower main surface side by the flexible substrate via holes 35 (35A, 35B). ~ 26C) to conduct each other.

また、図3(B),図3(C)に示すように、このフレキシブル基板25では、複数のフレキシブル基板回路配線26(26A〜26C)をそれぞれ略一方向(突出部31Aと突出部31Bとを結ぶ方向)に延長し、略平行するように所定間隔で配置している。また、フレキシブル基板回路配線26(26A〜26C)やコンタクト電極27(27A,27B)、接続用電極29(29A,29B,29C)はフレキシブル基板25の両主面側にそれぞれ形成可能であり、一方の主面側にのみ設けたものや、対向するように両主面側にそれぞれ設けたものや、フレキシブル基板ビアホール35(35A,35B)により両主面間を接続するように設けたものなど、様々に配置している。このように両主面のそれぞれにフレキシブル基板回路配線26(26A〜26C),コンタクト電極27(27A,27B),接続用電極29(29A,29B,29C)を設けることで、このフレキシブル基板25を、回路基板21の中間層(絶縁層22A,22Bの中間)に設けることができ、回路基板の構成部として使用できる。また、これによりフレキシブル基板25の両主面に、ともにコンタクト電極27(27A,27B)を設けることができ、回路基板21全体として、より多くのコンタクト電極27(27A,27B)を設けることができる。   Further, as shown in FIGS. 3B and 3C, in the flexible substrate 25, a plurality of flexible substrate circuit wirings 26 (26A to 26C) are arranged in approximately one direction (protruding portion 31A and protruding portion 31B, respectively). Are arranged at predetermined intervals so as to be substantially parallel to each other. Further, the flexible substrate circuit wiring 26 (26A to 26C), the contact electrode 27 (27A, 27B), and the connection electrode 29 (29A, 29B, 29C) can be formed on both main surfaces of the flexible substrate 25, respectively. Those provided only on the main surface side, those provided on both main surface sides so as to face each other, those provided so as to connect the two main surfaces by the flexible substrate via hole 35 (35A, 35B), etc. Arranged in various ways. Thus, by providing the flexible substrate circuit wiring 26 (26A to 26C), the contact electrode 27 (27A, 27B), and the connection electrode 29 (29A, 29B, 29C) on each of the two main surfaces, the flexible substrate 25 is formed. And can be provided in an intermediate layer of the circuit board 21 (intermediate between the insulating layers 22A and 22B) and can be used as a component of the circuit board. In addition, the contact electrodes 27 (27A, 27B) can be provided on both main surfaces of the flexible substrate 25, and more contact electrodes 27 (27A, 27B) can be provided as the circuit board 21 as a whole. .

また、図3(A)に示す絶縁層22A,22Bは、薄板状の熱硬化材からなり、その内部に電子部品23(23A〜23C)を埋設し、さらにその表層面にあたる主面に表層面回路配線28(28A〜28F)を設ける。また、表層面に対向する接続面(フレキシブル基板25が接合する一面)に接続面回路配線34(34A〜34G)を設け、その表層面と接続面の回路配線同士を絶縁層ビアホール24(24A〜24D)により接続する。   In addition, the insulating layers 22A and 22B shown in FIG. 3 (A) are made of a thin plate-like thermosetting material, in which an electronic component 23 (23A to 23C) is embedded, and the surface layer surface is a main surface corresponding to the surface layer surface. Circuit wiring 28 (28A to 28F) is provided. Further, the connection surface circuit wiring 34 (34A to 34G) is provided on the connection surface (one surface to which the flexible substrate 25 is bonded) facing the surface layer surface, and the circuit wiring on the surface layer surface and the connection surface is connected to the insulating layer via hole 24 (24A to 24A). 24D).

ここでは、フレキシブル基板25の両主面を絶縁層22Aの接続面(下主面)と絶縁層22Bの接続面(上主面)とにより狭持し、フレキシブル基板25の接続用電極29(29A〜29C)を絶縁層22A,22Bの接続面回路配線34(34A〜34G)に接続して回路基板21を構成する。
ここで回路基板21の、フレキシブル基板25と絶縁層22A,22Bとが積層している部分を積層部32、フレキシブル基板25が積層部32よりも突出する部分を突出部31A,31Bとする。
突出部31A,31Bには、コンタクト電極27(27A,27B)を設けており、フレキシブル基板25に設けたフレキシブル基板回路配線26(26A〜26C)(本発明の、引出線の一部である。)と接続する。このフレキシブル基板回路配線26(26A〜26C)は、フレキシブル基板25の積層部32に設けた接続用電極29(29A〜29C)や、絶縁層22(22A,22B)に設けた接続面回路配線34(34A〜34G)などを介して電子部品23(23A〜23C)と接続する。
Here, both main surfaces of the flexible substrate 25 are held between the connection surface (lower main surface) of the insulating layer 22A and the connection surface (upper main surface) of the insulating layer 22B, and the connection electrodes 29 (29A of the flexible substrate 25) To 29C) are connected to the connection surface circuit wiring 34 (34A to 34G) of the insulating layers 22A and 22B to constitute the circuit board 21.
Here, a portion of the circuit board 21 where the flexible substrate 25 and the insulating layers 22A and 22B are laminated is referred to as a laminated portion 32, and portions where the flexible substrate 25 protrudes from the laminated portion 32 are referred to as protruding portions 31A and 31B.
The projecting portions 31A and 31B are provided with contact electrodes 27 (27A and 27B), and flexible substrate circuit wirings 26 (26A to 26C) provided on the flexible substrate 25 (part of the lead lines of the present invention). ). The flexible substrate circuit wiring 26 (26A to 26C) includes connection electrodes 29 (29A to 29C) provided on the laminated portion 32 of the flexible substrate 25 and connection surface circuit wiring 34 provided on the insulating layer 22 (22A and 22B). It connects with the electronic component 23 (23A-23C) via (34A-34G) etc.

また、表層面回路配線28(28A〜28F)には、一部にモニタ電極30(30A,30B)を設ける。モニタ電極30(30A,30B)は本来の回路配線に近接して引き出したところに設け、その大きさは所定面積とするが、この面積は当接させるプローブの先端を確実に当接できる大きさであれば良く、プローブ先端サイズやプロービング位置精度を考慮して定める。   Further, the monitor electrode 30 (30A, 30B) is partially provided on the surface layer circuit wiring 28 (28A to 28F). The monitor electrode 30 (30A, 30B) is provided where it is drawn close to the original circuit wiring, and its size is a predetermined area. This area is a size that can reliably contact the tip of the probe to be contacted. It is sufficient to determine the probe tip size and the probing position accuracy.

ここで、図3(A),図3(B)におけるAA′断面に位置する素子や回路を基にその接続構造について説明する。   Here, the connection structure will be described based on the elements and circuits located in the AA ′ cross section in FIG. 3 (A) and FIG. 3 (B).

AA′断面では、フレキシブル基板25の突出部31Aにコンタクト電極27Aを設けている。コンタクト電極27Aは、フレキシブル基板25の内層に設けたフレキシブル基板回路配線26Aの一端と接続している。フレキシブル基板回路配線26Aの他端は、接続用電極29Aと絶縁層22Aの接続面回路配線34Bとを介して、絶縁層22Aに埋設された電子部品23Aに接続している。また、フレキシブル基板25内のフレキシブル基板ビアホール35Aを介して絶縁層22B側の接続面回路配線や電子部品にも接続している。   In the AA ′ cross section, the contact electrode 27 </ b> A is provided on the protruding portion 31 </ b> A of the flexible substrate 25. The contact electrode 27A is connected to one end of a flexible substrate circuit wiring 26A provided in the inner layer of the flexible substrate 25. The other end of the flexible circuit board wiring 26A is connected to the electronic component 23A embedded in the insulating layer 22A via the connection electrode 29A and the connection surface circuit wiring 34B of the insulating layer 22A. Further, it is also connected to connection surface circuit wiring and electronic components on the insulating layer 22B side through a flexible substrate via hole 35A in the flexible substrate 25.

また、フレキシブル基板25の突出部31Bにはコンタクト電極27Bを設けている。コンタクト電極27Bは、フレキシブル基板25の内層に設けたフレキシブル基板回路配線26Cの一端に接続している。フレキシブル基板回路配線26Cの他端は、接続用電極29Cを介して、絶縁層22Aの接続面回路配線34Fに接続している。この接続面回路配線34Fはこの絶縁層22Aの接続面を通って他の回路配線や電子部品に接続している。   A contact electrode 27 </ b> B is provided on the protruding portion 31 </ b> B of the flexible substrate 25. The contact electrode 27B is connected to one end of a flexible substrate circuit wiring 26C provided in the inner layer of the flexible substrate 25. The other end of the flexible substrate circuit wiring 26C is connected to the connection surface circuit wiring 34F of the insulating layer 22A via the connection electrode 29C. The connection surface circuit wiring 34F is connected to other circuit wiring and electronic components through the connection surface of the insulating layer 22A.

また、図3(B)に示すように表層面回路配線28Cには、プローブを当接させて検査するために用いるモニタ電極30Aを本来の回路配線に近接して引き出したところに設けている。図3(A)に示すように表層面回路配線28Cは、AA′断面に位置する一端で絶縁層ビアホール24Bを介して接続面回路配線34Dに接続している。この接続面回路配線34Dには電子部品23Bと電子部品23Cとの端子を接続し、電子部品23Bの他の端子は接続面回路配線34Cを介してフレキシブル基板25の接続用電極29Bと接続し、さらに接続用電極29Bはフレキシブル基板ビアホール35Bを介して絶縁層22B側の接続面回路配線や電子部品に接続している。また、電子部品23Cの他の端子は、接続面回路配線34Eと絶縁層ビアホール24Cとを介して表層面回路配線28Eに接続している。図3(B)に示すように、この表層面回路配線28Eには、プロービングに用いるモニタ電極30Bを設けている。   Further, as shown in FIG. 3B, the surface layer circuit wiring 28C is provided with a monitor electrode 30A used for contacting and inspecting the probe in the vicinity of the original circuit wiring. As shown in FIG. 3A, the surface layer circuit wiring 28C is connected to the connection surface circuit wiring 34D through the insulating layer via hole 24B at one end located in the section AA ′. The connection surface circuit wiring 34D is connected to terminals of the electronic component 23B and the electronic component 23C, and the other terminals of the electronic component 23B are connected to the connection electrode 29B of the flexible substrate 25 via the connection surface circuit wiring 34C. Further, the connection electrode 29B is connected to connection surface circuit wiring and electronic components on the insulating layer 22B side through the flexible substrate via hole 35B. The other terminal of the electronic component 23C is connected to the surface layer circuit wiring 28E via the connection surface circuit wiring 34E and the insulating layer via hole 24C. As shown in FIG. 3B, the surface layer circuit wiring 28E is provided with a monitor electrode 30B used for probing.

また、絶縁層22Aの表層面回路配線28AはAA′断面において絶縁層ビアホール24Aを介して絶縁層22Aの接続面回路配線34Aに接続している。また、表層面回路配線28Bと表層面回路配線28Dとは、AA′断面では単に絶縁層22Aの表層面を通過する。また、表層面回路配線28Fは絶縁層ビアホール24Dを介して接続面回路配線34Gに接続している。   The surface layer circuit wiring 28A of the insulating layer 22A is connected to the connection surface circuit wiring 34A of the insulating layer 22A via the insulating layer via hole 24A in the section AA ′. Further, the surface layer circuit wiring 28B and the surface layer circuit wiring 28D simply pass through the surface layer of the insulating layer 22A in the section AA ′. The surface layer circuit wiring 28F is connected to the connection surface circuit wiring 34G through the insulating layer via hole 24D.

以上のような、回路配線と電子部品とにより回路基板21を構成している。
ここでは後述する電圧制御発振器の回路構成を例として、上述のような接続構造で回路基板21を構成している。なお、電圧制御発振器以外のどのような回路構成であっても本発明は実施できる。
The circuit board 21 is configured by the circuit wiring and the electronic components as described above.
Here, taking the circuit configuration of a voltage controlled oscillator described later as an example, the circuit board 21 is configured with the connection structure as described above. The present invention can be implemented with any circuit configuration other than the voltage controlled oscillator.

次に、この回路基板21に対してプロービングを行う例を図4を基に説明する。
図4(A)は、前記図3(A)と同様な回路基板21の積層方向の断面図(AA′断面図)であるが、ここでは仮想的に別の断面に位置するコンタクト電極27Cとモニタ電極30Aとを同断面上に位置するように表す。
図4(B)は、この回路基板21に内装した電圧制御発振器の回路図であり、ここでは全てのモニタ電極とコンタクト電極のうち、この例でプローブを当接するモニタ電極30Aとコンタクト電極27A,27B,27Cのみを端子として表示する。
Next, an example of probing the circuit board 21 will be described with reference to FIG.
4A is a cross-sectional view (AA ′ cross-sectional view) in the stacking direction of the circuit board 21 similar to FIG. 3A. Here, the contact electrode 27C virtually located on another cross-section is shown in FIG. The monitor electrode 30A is shown to be located on the same cross section.
FIG. 4B is a circuit diagram of the voltage controlled oscillator built in the circuit board 21. Here, among all the monitor electrodes and contact electrodes, the monitor electrode 30A and the contact electrodes 27A, which contact the probe in this example. Only 27B and 27C are displayed as terminals.

ここで電子部品の結線状態および電子部品実装状態の検査方法の一例を説明する。
この電圧制御発振器では、図4(B)に示すように増幅回路側では、増幅段として作用するトランジスタTR1のコレクタとバッファ段として作用するトランジスタTR2のエミッタとの間に引出線を介してコンタクト電極27Cを接続している。また、トランジスタTR2のベースに引出線を介してコンタクト電極27Aを接続している。
Here, an example of the inspection method of the connection state and electronic component mounting state of an electronic component will be described.
In this voltage controlled oscillator, as shown in FIG. 4B, on the amplifier circuit side, a contact electrode is provided between the collector of the transistor TR1 acting as an amplification stage and the emitter of the transistor TR2 acting as a buffer stage via a lead line. 27C is connected. Further, a contact electrode 27A is connected to the base of the transistor TR2 via a lead line.

図4(A)に示すように、この例では二つのコンタクト電極27A,27Cのそれぞれにプローブを当接してトランジスタTR2のベース−エミッタ間のpn接合ダイオード特性を測定する。なお、ここでは電子部品23Dは、トランジスタTR1とトランジスタTR2を一体の部品としたものであり、この電子部品23Dの複数の端子の内トランジスタTR2のベースに相当する端子を、コンタクト電極27Aにフレキシブル基板回路配線26Aやフレキシブル基板ビアホール35Aなどを介して接続し、トランジスタTR2のエミッタに相当する端子をコンタクト電極27Cにフレキシブル基板回路配線(図示せず。)や接続用電極(図示せず。)を介して接続しているものとする。   As shown in FIG. 4A, in this example, the probe is brought into contact with each of the two contact electrodes 27A and 27C, and the pn junction diode characteristic between the base and the emitter of the transistor TR2 is measured. Here, the electronic component 23D is an integral component of the transistor TR1 and the transistor TR2, and a terminal corresponding to the base of the transistor TR2 among the plurality of terminals of the electronic component 23D is connected to the contact electrode 27A as a flexible substrate. A terminal corresponding to the emitter of the transistor TR2 is connected to the contact electrode 27C via a flexible substrate circuit wiring (not shown) or a connection electrode (not shown). Connected.

このとき図4(C)に示すようなダイオード特性(電圧−電流特性)が確認できれば、このトランジスタTR2が正確に実装・結線されていることがわかる。   At this time, if the diode characteristics (voltage-current characteristics) as shown in FIG. 4C can be confirmed, it can be seen that the transistor TR2 is correctly mounted and connected.

なお、ここで例示していないが半導体の入力端子−グランド間、および電源ライン間に設けられているサージ保護ダイオードを利用して半導体素子の実装,結線状態を確認することもできる。   Although not illustrated here, the mounting and connection state of the semiconductor element can also be confirmed using a surge protection diode provided between the semiconductor input terminal and the ground and between the power supply lines.

なお、このような検査方法はトランジスタTR2のみではなく、トランジスタTR1のベース−エミッタ間のpn接合ダイオード特性の測定に用いることもできる。この場合にはトランジスタTR1のベースにつながる回路配線とトランジスタTR1のエミッタにつながる回路配線は、高周波信号が伝搬する回路部分(図4(B)注の破線で囲んだ回路部分)であるためコンタクト電極ではなくモニタ電極を積層部に設けプロービングする。   Such an inspection method can be used not only for measuring the transistor TR2, but also for measuring the pn junction diode characteristics between the base and emitter of the transistor TR1. In this case, the circuit wiring connected to the base of the transistor TR1 and the circuit wiring connected to the emitter of the transistor TR1 are circuit portions through which high-frequency signals propagate (circuit portions surrounded by broken lines in FIG. 4B). Instead, a monitor electrode is provided in the laminated portion for probing.

このトランジスタTR1のベースおよびエミッタにつながる回路部分に、仮に引出線を介して接続するようにコンタクト電極を設けた場合には、それらに起因する寄生成分が生じ、高周波特性に影響を与えてしまい、高周波特性を正確に測定できない。そこで、これらの部分にはコンタクト電極ではなく、引出線長を短くできるモニタ電極を設けてプロービングすることで、高周波特性を正確に測定する。   If a contact electrode is provided in a circuit portion connected to the base and emitter of the transistor TR1 so as to be connected via a lead line, a parasitic component resulting from them is generated, which affects the high frequency characteristics. High frequency characteristics cannot be measured accurately. Therefore, high frequency characteristics are accurately measured by probing these portions by providing monitor electrodes that can shorten the length of the lead lines instead of contact electrodes.

また、電子部品実装状態の検査方法の他の例として、ここで図4(B)に示すコンタクト電極27Bとモニタ電極30Aのそれぞれにプローブを当接してインダクタL1の導通インピーダンスを測定する検査方法を示す。コンタクト電極27Bは、インダクタL1と制御電圧入力端子Vcとの間に引出線を介して接続している。一方、モニタ電極30Aは、バラクタダイオードVD1のカソードとインダクタL1との間の表層面回路配線28Cに設けており、表層面回路配線28Cからの短い引出線と所定面積の電極により形成している。このコンタクト電極27B、モニタ電極30Aのそれぞれにプローブを当接してインダクタL1の導通インピーダンスを測定する。これによりインダクタL1の実装状態と結線状態とを確認する。   Further, as another example of the inspection method of the electronic component mounting state, an inspection method in which the probe is brought into contact with each of the contact electrode 27B and the monitor electrode 30A shown in FIG. 4B and the conduction impedance of the inductor L1 is measured. Show. The contact electrode 27B is connected between the inductor L1 and the control voltage input terminal Vc via a lead wire. On the other hand, the monitor electrode 30A is provided on the surface layer circuit wiring 28C between the cathode of the varactor diode VD1 and the inductor L1, and is formed by a short lead line from the surface layer circuit wiring 28C and an electrode having a predetermined area. A probe is brought into contact with each of the contact electrode 27B and the monitor electrode 30A, and the conduction impedance of the inductor L1 is measured. Thereby, the mounting state and the connection state of the inductor L1 are confirmed.

ここで、バラクタダイオードVD1のカソードに接続される回路配線とアノードに接続する回路部分(図4(B)中の破線で囲んだLC回路部分)の高周波特性をモニタする際に、仮に引出線とコンタクト電極によってモニタする場合には、引出線とコンタクト電極に起因する寄生成分が生じ、高周波特性に影響を与えてしまう。そこで、これらの部分にはコンタクト電極ではなく、モニタ電極を設けてプロービングすることで、高周波特性を正確に測定する。   Here, when monitoring the high-frequency characteristics of the circuit wiring connected to the cathode of the varactor diode VD1 and the circuit portion connected to the anode (the LC circuit portion surrounded by the broken line in FIG. 4B), When monitoring with a contact electrode, a parasitic component is generated due to the lead line and the contact electrode, which affects the high frequency characteristics. Therefore, high frequency characteristics are accurately measured by probing these portions by providing monitor electrodes instead of contact electrodes.

なお、この電圧制御発振器の回路構成を次に説明する。
増幅回路側には、増幅段トランジスタTR1とバッファ段トランジスタTR2にベースバイアス電圧を印加する抵抗R1,R2,R3からなるベースバイアス回路を設け、トランジスタTR1のコレクタとトランジスタTR2のエミッタとの間に、高周波バイパス用コンデンサC9を設けて、トランジスタTR1のエミッタに接地用のコンデンサC4と、出力電圧を得るための抵抗R4と、この出力電圧をトランジスタTR2のベースに印加するコンデンサC6と、トランジスタTR1のエミッタからベースへと信号を帰還させる帰還用のコンデンサC5とを設けている。
The circuit configuration of this voltage controlled oscillator will be described next.
On the amplifier circuit side, a base bias circuit including resistors R1, R2, and R3 for applying a base bias voltage to the amplification stage transistor TR1 and the buffer stage transistor TR2 is provided, and between the collector of the transistor TR1 and the emitter of the transistor TR2. A high-frequency bypass capacitor C9 is provided, a grounding capacitor C4 is provided at the emitter of the transistor TR1, a resistor R4 for obtaining an output voltage, a capacitor C6 for applying this output voltage to the base of the transistor TR2, and an emitter of the transistor TR1. And a feedback capacitor C5 for feeding back the signal from the base to the base.

また、トランジスタTR2のコレクタには、インダクタL3を介して電源端子Vbと高周波バイパス用コンデンサC10とを設け、また、高周波バイパス用コンデンサC7と、直流遮断用コンデンサC8を介して出力端子Voutを設けている。   Further, the collector of the transistor TR2 is provided with a power supply terminal Vb and a high frequency bypass capacitor C10 via an inductor L3, and an output terminal Vout is provided via a high frequency bypass capacitor C7 and a DC cutoff capacitor C8. Yes.

また、共振回路側では、バラクタダイオードVD1のアノードにインダクタL2を設け、バラクタダイオードVD1のカソードにコンデンサC2を設けている。また、コンデンサC2とインダクタL1との接続点に結合用のコンデンサC3を介して増幅回路に接続している。   On the resonance circuit side, an inductor L2 is provided at the anode of the varactor diode VD1, and a capacitor C2 is provided at the cathode of the varactor diode VD1. Further, a connection point between the capacitor C2 and the inductor L1 is connected to the amplifier circuit via a coupling capacitor C3.

ここで、増幅回路側ではトランジスタTR2のコレクタにはインダクタL3を介して電源電圧Vbを印加するように構成し、コレクタに接続されたコンデンサC8を介して発振信号を出力電圧Voutとして出力するように構成している。また、共振回路側ではインダクタL1を介してバラクタダイオードVD1のカソードに制御電圧Vcを印加するように構成し、トランジスタTR1のベースに、コンデンサC3を介して共振信号を入力するように構成している。   Here, on the amplification circuit side, the power supply voltage Vb is applied to the collector of the transistor TR2 via the inductor L3, and the oscillation signal is output as the output voltage Vout via the capacitor C8 connected to the collector. It is composed. On the resonance circuit side, the control voltage Vc is applied to the cathode of the varactor diode VD1 via the inductor L1, and the resonance signal is input to the base of the transistor TR1 via the capacitor C3. .

以上のような回路構成の電圧制御発振器を回路基板21に内装している。そして、高周波特性に影響を与える回路配線にはコンタクト電極ではなく、積層部32上にモニタ電極を設けてプロービングすることで、本来の回路配線に影響を与えること無く高周波特性を正確に検査する。また、図中の破線で囲んでいない部分は低周波信号もしくは直流信号が伝搬する回路配線であり、回路配線の引き回しレイアウトにより、モニタ電極とコンタクト電極を使い分けることで、回路基板の面積を抑制できる。   The voltage controlled oscillator having the circuit configuration as described above is built in the circuit board 21. The circuit wiring that affects the high frequency characteristics is not contact electrodes but is provided with a monitor electrode on the laminated portion 32 and probing, thereby accurately inspecting the high frequency characteristics without affecting the original circuit wiring. In addition, the portion not surrounded by the broken line in the figure is a circuit wiring through which a low frequency signal or a direct current signal propagates, and the area of the circuit board can be suppressed by properly using the monitor electrode and the contact electrode according to the layout of the circuit wiring. .

また、積層部32に設けるモニタ電極30は、本来の回路配線から引き出したところに設け、特性評価するコンタクト電極の面積は、プロービングが確実に行える(プローブ先端サイズ、プロービング位置精度によって定まる。)大きさにする。このようにすることで、プローブによるプローブ痕がモニタ電極に発生しても、本来の回路配線、回路特性に影響を与えることがない。また、基板(製品)サイズを抑制できる。   In addition, the monitor electrode 30 provided in the laminated portion 32 is provided where it is pulled out from the original circuit wiring, and the area of the contact electrode whose characteristics are evaluated can be reliably probed (determined by the probe tip size and the probing position accuracy). Say it. By doing so, even if probe traces due to the probe occur on the monitor electrode, the original circuit wiring and circuit characteristics are not affected. Further, the size of the substrate (product) can be suppressed.

また、突出部はフレキシブル基板であるために、突出部の部分を屈曲させることができる。また、計測点にモニタ電極を設けるか、引出線を介してコンタクト電極を接続するかは自由に設定できるが、高周波回路部だけは、引出線長を短くできるモニタ電極とし、低周波回路部ではコンタクト電極とモニタ電極とを、回路配線の引き回しレイアウトにより使い分けると好適である。   In addition, since the protruding portion is a flexible substrate, the protruding portion can be bent. In addition, it is possible to freely set whether to provide a monitor electrode at the measurement point or to connect the contact electrode via a leader line, but only the high frequency circuit part is a monitor electrode that can shorten the leader line length. It is preferable that the contact electrode and the monitor electrode are properly used according to the circuit wiring routing layout.

次に、本実施形態の部品内蔵絶縁層22Aの製造工程の例を図5に示す。
(A) 本実施形態の部品内蔵絶縁層22Aの製造工程においては、まず支持板33上に接続面回路配線34(34A〜34G)となる導体層パターンを形成する。接続面回路配線34(34A〜34G)の形成は、支持板33に銅箔(Cu箔)を貼付け、あるいは銅めっき(Cuめっき)を形成し、これを所望のパターンにエッチングすることで行う。
Next, FIG. 5 shows an example of the manufacturing process of the component built-in insulating layer 22A of this embodiment.
(A) In the manufacturing process of the component built-in insulating layer 22 </ b> A of this embodiment, first, a conductor layer pattern to be the connection surface circuit wiring 34 (34 </ b> A to 34 </ b> G) is formed on the support plate 33. The connection surface circuit wiring 34 (34A to 34G) is formed by sticking a copper foil (Cu foil) on the support plate 33 or forming a copper plating (Cu plating) and etching it to a desired pattern.

(B) 次に接続面回路配線34(34A〜34G)上の所定位置に、電子部品23(23A〜23C)を載置、接続する。 (B) Next, the electronic component 23 (23A to 23C) is placed and connected to a predetermined position on the connection surface circuit wiring 34 (34A to 34G).

(C) 次に、前述の接続面回路配線34(34A〜34G)および電子部品23(23A〜23C)を封止するように導体層つきの絶縁シートをラミネートし、絶縁層22Aを略構成する。 (C) Next, an insulating sheet with a conductor layer is laminated so as to seal the connection surface circuit wiring 34 (34A to 34G) and the electronic component 23 (23A to 23C), and the insulating layer 22A is substantially configured.

(D) 次に、ラミネートにより設けられた絶縁層22Aに絶縁層ビアホール24(24A〜24D)となる孔を形成するとともに、その孔に導体を充填して絶縁層ビアホール24(24A〜24D)を形成し、さらに導体層をエッチングして表層面回路配線28(28A〜28F)となるパターンを形成する。この工程では導体層には表層面回路電極28(28A〜28F)のみではなく、後の検査時にプローブを当接させる検査用電極となるモニタ電極30(30A,30B)(図示せず。)も形成する。 (D) Next, a hole to be the insulating layer via hole 24 (24A to 24D) is formed in the insulating layer 22A provided by lamination, and the hole is filled with a conductor to form the insulating layer via hole 24 (24A to 24D). Then, the conductor layer is further etched to form a pattern that becomes the surface layer circuit wiring 28 (28A to 28F). In this step, not only the surface layer circuit electrodes 28 (28A to 28F) but also monitor electrodes 30 (30A, 30B) (not shown), which serve as inspection electrodes with which the probe comes into contact in the subsequent inspection, are formed in the conductor layer. Form.

(E) 次に、前述の支持板33を除去する。これにより絶縁層22Aを形成する。 (E) Next, the support plate 33 is removed. Thereby, the insulating layer 22A is formed.

以上のような各工程により、本実施形態の絶縁層22Aを製造する。なお、この絶縁層22Aのみではなく、絶縁層22Bも類似の工程により製造する。   The insulating layer 22A of this embodiment is manufactured through the above steps. Not only the insulating layer 22A but also the insulating layer 22B are manufactured by a similar process.

結線状態や部品実装状態や高周波特性などの基板仕上がり状態の検査は、各基板構造が完成する工程段階(例えば図3や図6(B)や図7(B))で行う。そのことにより、不具合の発生を速やかに察知することができ、不具合箇所や不具合工程を容易に把握できる。そして、不具合発生箇所には、この後工程で電子部品を搭載しないようにプログラムすることで、電子部品が無駄に消費されることを防いで、電子部品の利用効率を高めることができる。   The inspection of the substrate finish state such as the connection state, the component mounting state, and the high frequency characteristics is performed at a process stage (for example, FIG. 3, FIG. 6B, or FIG. 7B) at which each substrate structure is completed. As a result, it is possible to quickly detect the occurrence of a defect, and it is possible to easily grasp the defect location and the defect process. Then, by programming so that the electronic component is not mounted in the subsequent process at the defect occurrence location, it is possible to prevent the electronic component from being wasted and to increase the use efficiency of the electronic component.

次に、図6に上記の工程により製造された絶縁層をフレキシブル基板25に積層する工程と、さらにビルドアップ配線板を形成した構成と、さらに突出部を切断して、その切断面に絶縁材をコーティングした構造図を示す。   Next, in FIG. 6, the step of laminating the insulating layer manufactured by the above-described steps on the flexible substrate 25, the configuration in which the build-up wiring board is further formed, and the protruding portion are further cut, and the insulating material is formed on the cut surface. FIG.

(A) 前述の工程により製造された絶縁層22Aと、同様な工程により製造された絶縁層22Bと、フレキシブル基板25を用意する。フレキシブル基板回路配線26(26A〜26C)の露出した接続用電極となる位置の部分に、接合および導通用の導電性接着剤を塗布して、絶縁層22B、フレキシブル基板25、絶縁層22Aを接合する。 (A) An insulating layer 22A manufactured by the above process, an insulating layer 22B manufactured by the same process, and a flexible substrate 25 are prepared. A conductive adhesive for bonding and conduction is applied to the exposed portion of the flexible circuit board wiring 26 (26A to 26C) where the connection electrode is exposed, and the insulating layer 22B, the flexible substrate 25, and the insulating layer 22A are bonded. To do.

(B) 前述の絶縁層22Bの下に、さらにビルドアップ配線板(絶縁層22C、電極パターン)を形成して回路基板21とする。この回路基板21は突出部31A,31Bにコンタクト電極27(27A,27B)を備えるとともに、積層部32にモニタ電極30(図示せず。)を備えるために、電子部品23(23A〜23C)を回路基板21に搭載、埋設した後であってもコンタクト電極27(27A,27B)とモニタ電極30(30A,30B)に検査用のプローブを当接して検査を行うことができ、部分的な電気特性や結線状態、または電子部品実装状態の確認ができる。 (B) A build-up wiring board (insulating layer 22C, electrode pattern) is further formed under the insulating layer 22B to form the circuit board 21. Since the circuit board 21 includes the contact electrodes 27 (27A, 27B) on the projecting portions 31A, 31B and the monitor electrode 30 (not shown) on the laminated portion 32, the electronic component 23 (23A-23C) is provided. Even after mounting and embedding on the circuit board 21, it is possible to perform inspection by contacting the contact electrode 27 (27A, 27B) and the monitor electrode 30 (30A, 30B) with an inspection probe. You can check the characteristics, connection status, and electronic component mounting status.

(C) プロービング実施後に、前述の絶縁層22Aの上に、さらにビルドアップ配線板(絶縁層22D)を形成するとともに、突出部のフレキシブル基板25を切断して回路基板21をブロック状に形成する。さらに、その切断を行った側面および上面を絶縁材でコーティングしてコーティング層36を形成する。このようにすることで外部環境の影響を受けにくくできる。なお、一般的にフレキシブル基板25は加工が容易であるため、突出部を容易に除去できる。そして、突出部を切断することで回路基板21全体の回路基板面積を小さくすることができる。 (C) After the probing is performed, a build-up wiring board (insulating layer 22D) is further formed on the insulating layer 22A, and the protruding flexible substrate 25 is cut to form the circuit board 21 in a block shape. . Further, the side surface and the upper surface that have been cut are coated with an insulating material to form a coating layer 36. By doing so, it is difficult to be affected by the external environment. Since the flexible substrate 25 is generally easy to process, the protruding portion can be easily removed. And the circuit board area of the circuit board 21 whole can be made small by cut | disconnecting a protrusion part.

以上で示したように、突出部を備えた回路基板21を製造し、さらにその突出部のコンタクト電極にプローブを当接させて電気特性や結線状態、または電子部品実装状態を検査し、最後に突出部を削除することで、小型化と高密度化を実現した回路基板21であっても、電気特性の検査や、結線状態または電子部品実装状態を確認した製品を製造できる。   As described above, the circuit board 21 having the protrusion is manufactured, and the probe is brought into contact with the contact electrode of the protrusion to inspect the electrical characteristics, the connection state, or the electronic component mounting state. By removing the protrusions, it is possible to manufacture a product in which the electrical characteristics are inspected and the connection state or the electronic component mounting state is confirmed even with the circuit board 21 that has been reduced in size and increased in density.

また、回路基板21を製造する工程中で、プロービングを行い電気特性や結線状態、または電子部品実装状態を検査することで、小型化と高密度化を実現し、高周波特性に影響を与えないモニタ電極30(30A,30B)を積層部32に設けることで、高周波特性や結線状態、または電子部品実装状態を確実に確認しながら回路基板21を製造できる。   Also, in the process of manufacturing the circuit board 21, by performing probing and inspecting the electrical characteristics, the connection state, or the electronic component mounting state, a monitor that does not affect the high-frequency characteristics by realizing miniaturization and high density. By providing the electrode 30 (30A, 30B) in the laminated portion 32, the circuit board 21 can be manufactured while reliably confirming the high frequency characteristics, the connection state, or the electronic component mounting state.

なお、単一の電子部品23(23A〜23C)にコンタクト電極27(27A,27B)とモニタ電極30(30A,30B)とをともに設ける場合には、突出部31A,31Bのコンタクト電極27(27A,27B)を形成する前の製造工程中であっても、電子部品23(23A〜23C)に近接して引き出したところに設けたモニタ電極30(30A,30B)を用いて電気特性を検査できる。その後で、さらに他の絶縁層を積層してモニタ電極30(30A,30B)が埋設されてしまったとしても、その際にはコンタクト電極27(27A,27B)を用いてプロービングを行うと、回路基板21の新たな表層面にモニタ電極30(30A,30B)が必要でなくなるために、面積を抑制したままプロービングを行うことができる。このように、プロービングを行う工程がコンタクト電極27(27A,27B)を形成する工程よりも前工程でもよく、工程表から制約を減らすことができる。   When both the contact electrode 27 (27A, 27B) and the monitor electrode 30 (30A, 30B) are provided on a single electronic component 23 (23A-23C), the contact electrode 27 (27A of the protruding portions 31A, 31B is provided. 27B), the electrical characteristics can be inspected using the monitor electrode 30 (30A, 30B) provided in the vicinity of the electronic component 23 (23A to 23C). . After that, even if another insulating layer is laminated and the monitor electrode 30 (30A, 30B) is buried, if probing is performed using the contact electrode 27 (27A, 27B) at that time, Since the monitor electrode 30 (30A, 30B) is not required on the new surface layer of the substrate 21, the probing can be performed while the area is suppressed. As described above, the probing process may be performed prior to the process of forming the contact electrodes 27 (27A, 27B), and restrictions can be reduced from the process table.

次に、本発明の第2の実施形態を説明する。
本実施形態の回路基板は、複数のフレキシブル基板と複数の回路基板を積層した構成である。また、その複数のフレキシブル基板はその突出部の突出方向の長さがそれぞれ異なる構成である。
Next, a second embodiment of the present invention will be described.
The circuit board of this embodiment has a configuration in which a plurality of flexible boards and a plurality of circuit boards are stacked. Further, the plurality of flexible substrates are configured such that the protruding portions have different lengths in the protruding direction.

この本実施形態の回路基板の製造工程について図7に基づいて説明する。   The manufacturing process of the circuit board of this embodiment will be described with reference to FIG.

(A) まず、前述の第1の実施形態で示した製造工程と類時の工程により、絶縁層42Aと絶縁層42Bとによってフレキシブル基板45Aが狭持された第1の回路基板41Aを製造するとともに、絶縁層42Cとフレキシブル基板45Bが接合した第2の回路基板41Bを製造する。ここで、フレキシブル基板45Aと、フレキシブル基板45Bはそれぞれ突出部部分のサイズが異なり、フレキシブル基板45Bがより幅広な形状である。 (A) First, the first circuit board 41A in which the flexible board 45A is sandwiched by the insulating layer 42A and the insulating layer 42B is manufactured by the manufacturing process and the similar process shown in the first embodiment. At the same time, the second circuit board 41B in which the insulating layer 42C and the flexible board 45B are joined is manufactured. Here, the flexible substrate 45A and the flexible substrate 45B have different projecting portion sizes, and the flexible substrate 45B has a wider shape.

(B) 次に、第2の回路基板41Bのフレキシブル基板45Bの接続用電極となる位置の回路配線の露出部分に、接合および導通用の導電性接着剤を塗布して、第1の回路基板41Aの絶縁層42B側の当該箇所に接合する。 (B) Next, a conductive adhesive for bonding and conduction is applied to an exposed portion of the circuit wiring at a position to be a connection electrode of the flexible board 45B of the second circuit board 41B, so that the first circuit board It joins to the location on the insulating layer 42B side of 41A.

この第1の回路基板41Aと第2の回路基板41Bを接合してなる回路基板41はフレキシブル基板45Aとフレキシブル基板45Bのそれぞれに突出部を備えているために、それぞれの突出部のコンタクト電極と、積層部のモニタ電極とにより、前述のプロービングを実施することができる。   Since the circuit board 41 formed by joining the first circuit board 41A and the second circuit board 41B is provided with a protruding portion on each of the flexible substrate 45A and the flexible substrate 45B, the contact electrode of each protruding portion and The above-mentioned probing can be performed by the monitor electrode of the laminated portion.

(C) このプロービングにおいて、フレキシブル基板45Aとフレキシブル基板45Bとはそれぞれ突出部部分のサイズが異なり、フレキシブル基板45Bがより幅広な形状であるために、プローブを当接させる際にそれぞれの突出部同士が干渉せず、多くのプローブを同時に当接させることができる。 (C) In this probing, the flexible substrate 45A and the flexible substrate 45B have different sizes of the protruding portions, and the flexible substrate 45B has a wider shape. Many probes can be brought into contact with each other at the same time without interference.

なお、プロービング後に、フレキシブル基板45Aおよびフレキシブル基板45Bの突出部を切断して回路基板41をブロック状に形成するとともに、その切断した面を絶縁材でコーティングしてもよい。   After probing, the protruding portions of the flexible substrate 45A and the flexible substrate 45B may be cut to form the circuit board 41 in a block shape, and the cut surface may be coated with an insulating material.

以上の各実施形態で示したように、本発明は回路基板に積層する回路基板やフレキシブル基板の数によらずに実施できる。   As shown in the above embodiments, the present invention can be implemented regardless of the number of circuit boards and flexible boards stacked on the circuit board.

従来の回路基板の構成例を示す図である。It is a figure which shows the structural example of the conventional circuit board. 従来のフレキシブル基板の構成例を示す図である。It is a figure which shows the structural example of the conventional flexible substrate. 第1の実施形態の回路基板の構成例を示す図である。It is a figure which shows the structural example of the circuit board of 1st Embodiment. プロービングを行う例を説明する図である。It is a figure explaining the example which performs probing. 絶縁層の製造工程例を示す図である。It is a figure which shows the example of a manufacturing process of an insulating layer. 第1の実施形態の回路基板の他の構成例を説明する図である。It is a figure explaining the other structural example of the circuit board of 1st Embodiment. 第2の実施形態の回路基板の製造工程例を示す図である。It is a figure which shows the example of a manufacturing process of the circuit board of 2nd Embodiment.

符号の説明Explanation of symbols

1,2,32−積層部(リジッド部)
3,31−突出部(フレックス部)
4,27−コンタクト電極
5,6,7,8,13,23−電子部品
11,21,41−回路基板
12,22,42−絶縁層
14,24−絶縁層ビアホール
25,45−フレキシブル基板
26−フレキシブル基板回路配線
28−積層部表層面回路配線
29−接続用電極
30−モニタ電極
33−支持板
34−積層部接続面回路配線
35−フレキシブル基板ビアホール
36−(絶縁材)コーティング層
1,2,32-Laminated part (rigid part)
3,31-protruding part (flex part)
4,27-Contact electrode 5,6,7,8,13,23-Electronic component 11,21,41-Circuit board 12,22,42-Insulating layer 14,24-Insulating layer via hole 25,45-Flexible board 26 -Flexible substrate circuit wiring 28-Laminate surface layer circuit wiring 29-Connection electrode 30-Monitor electrode 33-Support plate 34-Laminate connection surface circuit wiring 35-Flexible substrate via hole 36-(insulating material) coating layer

Claims (10)

複数の絶縁層を積層した積層部を備え、前記積層部の絶縁層間に回路配線を設けた回路基板であって、
前記複数の絶縁層のうち少なくとも1つの絶縁層に、その面方向に前記積層部から突出する突出部を設け、前記回路配線に接続された検査用電極を、前記突出部および前記積層部のそれぞれの表面に設けたことを特徴とする回路基板。
A circuit board comprising a laminated portion in which a plurality of insulating layers are laminated, and circuit wiring is provided between the insulating layers of the laminated portion,
At least one insulating layer of the plurality of insulating layers is provided with a protruding portion that protrudes from the stacked portion in the surface direction, and the inspection electrode connected to the circuit wiring is connected to each of the protruding portion and the stacked portion. A circuit board characterized by being provided on the surface of the board.
前記回路配線は、高周波信号が伝搬する高周波回路部と、低周波信号が伝搬する低周波回路部とを備え、
高周波回路部用の検査用電極を前記積層部の表面にのみ設け、低周波回路部用の検査用電極を前記突出部の表面、または前記積層部と前記突出部の両方の表面に設けたことを特徴とする請求項1に記載の回路基板。
The circuit wiring includes a high-frequency circuit unit through which a high-frequency signal propagates and a low-frequency circuit unit through which a low-frequency signal propagates,
The inspection electrode for the high frequency circuit part is provided only on the surface of the laminated part, and the inspection electrode for the low frequency circuit part is provided on the surface of the projecting part or both surfaces of the laminated part and the projecting part. The circuit board according to claim 1.
前記回路配線に接続した電子部品を備え、該電子部品を前記積層部に埋設した請求項1または2に記載の回路基板。   The circuit board according to claim 1, further comprising an electronic component connected to the circuit wiring, wherein the electronic component is embedded in the stacked portion. 前記突出部を設けた絶縁層は、可撓性基板からなる請求項1〜3のいずれか1項に記載の回路基板。   The circuit board according to claim 1, wherein the insulating layer provided with the projecting portion is made of a flexible substrate. 前記突出部を設けた絶縁層の両主面に前記回路配線を配し、前記突出部に前記両主面の回路配線間を接続するビアホールを設けた請求項1〜4のいずれか1項に記載の回路基板。   5. The method according to claim 1, wherein the circuit wiring is arranged on both main surfaces of the insulating layer provided with the projecting portion, and a via hole is provided in the projecting portion to connect between the circuit wirings on the two main surfaces. Circuit board as described. 前記突出部を複数の絶縁層に設け、その絶縁層ごとに突出部のサイズを異ならせてなる請求項1〜5のいずれか1項に記載の回路基板。   The circuit board according to claim 1, wherein the protrusion is provided on a plurality of insulating layers, and the size of the protrusion is different for each insulating layer. 前記突出部を前記積層部との境界付近で切断し、その切断した面を絶縁材でコーティングした請求項1〜6のいずれか1項に記載の回路基板。   The circuit board according to claim 1, wherein the projecting portion is cut in the vicinity of the boundary with the laminated portion, and the cut surface is coated with an insulating material. 請求項1〜6のいずれか1項に記載の回路基板を製造する工程と、前記検査用電極に検査用のプローブを当接して電気特性、結線状態、または電子部品実装状態を検査する工程と、を順に実行することを特徴とする回路基板製造方法。   A step of manufacturing the circuit board according to any one of claims 1 to 6, and a step of inspecting an electrical property, a connection state, or an electronic component mounting state by contacting an inspection probe to the inspection electrode; Are sequentially executed. A circuit board manufacturing method comprising: 請求項1〜6のいずれか1項に記載の回路基板を製造する工程で、前記複数の絶縁層のうち所定の絶縁層に設けた検査用電極に、検査用のプローブを当接して電気特性、結線状態、または電子部品実装状態を検査し、その後、前記検査用電極を設けた絶縁層に他の絶縁層を積層することを特徴とする回路基板製造方法。   In the process of manufacturing the circuit board according to claim 1, an inspection probe is brought into contact with an inspection electrode provided on a predetermined insulating layer among the plurality of insulating layers, so that electric characteristics are obtained. A circuit board manufacturing method comprising: inspecting a connection state or an electronic component mounting state, and then laminating another insulating layer on the insulating layer provided with the inspection electrode. 請求項8または9に記載の工程の後で、前記突出部を切断し、その切断した面を絶縁材でコーティングすることを特徴とする回路基板製造方法。   A method for manufacturing a circuit board, comprising: cutting the projecting portion after the step according to claim 8 or 9, and coating the cut surface with an insulating material.
JP2005213756A 2005-07-25 2005-07-25 Circuit board and circuit board manufacturing method Expired - Fee Related JP4839713B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005213756A JP4839713B2 (en) 2005-07-25 2005-07-25 Circuit board and circuit board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005213756A JP4839713B2 (en) 2005-07-25 2005-07-25 Circuit board and circuit board manufacturing method

Publications (2)

Publication Number Publication Date
JP2007035739A true JP2007035739A (en) 2007-02-08
JP4839713B2 JP4839713B2 (en) 2011-12-21

Family

ID=37794661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005213756A Expired - Fee Related JP4839713B2 (en) 2005-07-25 2005-07-25 Circuit board and circuit board manufacturing method

Country Status (1)

Country Link
JP (1) JP4839713B2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007305674A (en) * 2006-05-09 2007-11-22 Denso Corp Part built-in substrate, and method of inspecting failure of its wiring
JP2008218441A (en) * 2007-02-28 2008-09-18 Micronics Japan Co Ltd Multilayer wiring board and its inspection method
JP2013077842A (en) * 2013-01-17 2013-04-25 Dainippon Printing Co Ltd Wiring board, and method of inspecting wiring board
JP2015192144A (en) * 2014-03-27 2015-11-02 インテル・コーポレーション Electric circuit on flexible substrate
CN105575932A (en) * 2014-11-05 2016-05-11 英飞凌科技奥地利有限公司 Electronic component, system and method
KR20170034934A (en) * 2014-11-12 2017-03-29 인텔 코포레이션 Wearable electronic devices and components thereof
US10064287B2 (en) 2014-11-05 2018-08-28 Infineon Technologies Austria Ag System and method of providing a semiconductor carrier and redistribution structure
WO2018159839A1 (en) * 2017-03-02 2018-09-07 株式会社村田製作所 Resin multilayer substrate and electronic device
US10192846B2 (en) 2014-11-05 2019-01-29 Infineon Technologies Austria Ag Method of inserting an electronic component into a slot in a circuit board

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03283599A (en) * 1990-03-30 1991-12-13 Ngk Insulators Ltd Inspecting method for continuity of ceramic multilayer board
JPH0412679A (en) * 1990-05-01 1992-01-17 Nippondenso Co Ltd Ultrasonic motor
JPH0423158A (en) * 1990-05-18 1992-01-27 Nec Corp On-line network system
JPH05275852A (en) * 1992-03-24 1993-10-22 Toppan Printing Co Ltd Metal cored printed circuit board and manufacture thereof
JP2000059032A (en) * 1998-08-04 2000-02-25 Canon Inc Flexible multilayer wiring board
JP2000077810A (en) * 1998-08-27 2000-03-14 Sharp Corp Manufacture of partially flexible printed wiring board
JP2000091722A (en) * 1998-09-16 2000-03-31 Ibiden Co Ltd Printed wiring board and its manufacture
JP2001313227A (en) * 2000-04-28 2001-11-09 Matsushita Electric Ind Co Ltd Manufacturing method of laminate and electronic component, and electronic component
JP2003283131A (en) * 2002-03-26 2003-10-03 Matsushita Electric Ind Co Ltd Laminated circuit and its manufacturing method
JP2004222087A (en) * 2003-01-16 2004-08-05 Ngk Spark Plug Co Ltd High frequency parts
JP2004363425A (en) * 2003-06-06 2004-12-24 Hitachi Ltd Passive element incorporating board

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03283599A (en) * 1990-03-30 1991-12-13 Ngk Insulators Ltd Inspecting method for continuity of ceramic multilayer board
JPH0412679A (en) * 1990-05-01 1992-01-17 Nippondenso Co Ltd Ultrasonic motor
JPH0423158A (en) * 1990-05-18 1992-01-27 Nec Corp On-line network system
JPH05275852A (en) * 1992-03-24 1993-10-22 Toppan Printing Co Ltd Metal cored printed circuit board and manufacture thereof
JP2000059032A (en) * 1998-08-04 2000-02-25 Canon Inc Flexible multilayer wiring board
JP2000077810A (en) * 1998-08-27 2000-03-14 Sharp Corp Manufacture of partially flexible printed wiring board
JP2000091722A (en) * 1998-09-16 2000-03-31 Ibiden Co Ltd Printed wiring board and its manufacture
JP2001313227A (en) * 2000-04-28 2001-11-09 Matsushita Electric Ind Co Ltd Manufacturing method of laminate and electronic component, and electronic component
JP2003283131A (en) * 2002-03-26 2003-10-03 Matsushita Electric Ind Co Ltd Laminated circuit and its manufacturing method
JP2004222087A (en) * 2003-01-16 2004-08-05 Ngk Spark Plug Co Ltd High frequency parts
JP2004363425A (en) * 2003-06-06 2004-12-24 Hitachi Ltd Passive element incorporating board

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007305674A (en) * 2006-05-09 2007-11-22 Denso Corp Part built-in substrate, and method of inspecting failure of its wiring
JP4697037B2 (en) * 2006-05-09 2011-06-08 株式会社デンソー Component built-in board and wiring defect inspection method thereof
JP2008218441A (en) * 2007-02-28 2008-09-18 Micronics Japan Co Ltd Multilayer wiring board and its inspection method
JP2013077842A (en) * 2013-01-17 2013-04-25 Dainippon Printing Co Ltd Wiring board, and method of inspecting wiring board
US9930793B2 (en) 2014-03-27 2018-03-27 Intel Corporation Electric circuit on flexible substrate
JP2015192144A (en) * 2014-03-27 2015-11-02 インテル・コーポレーション Electric circuit on flexible substrate
CN105575932A (en) * 2014-11-05 2016-05-11 英飞凌科技奥地利有限公司 Electronic component, system and method
KR20160053817A (en) * 2014-11-05 2016-05-13 인피니언 테크놀로지스 오스트리아 아게 Electronic component, system and method
US10064287B2 (en) 2014-11-05 2018-08-28 Infineon Technologies Austria Ag System and method of providing a semiconductor carrier and redistribution structure
KR101941738B1 (en) * 2014-11-05 2019-01-23 인피니언 테크놀로지스 오스트리아 아게 Electronic component, system and method
US10192846B2 (en) 2014-11-05 2019-01-29 Infineon Technologies Austria Ag Method of inserting an electronic component into a slot in a circuit board
US10553557B2 (en) 2014-11-05 2020-02-04 Infineon Technologies Austria Ag Electronic component, system and method
KR20170034934A (en) * 2014-11-12 2017-03-29 인텔 코포레이션 Wearable electronic devices and components thereof
KR101884144B1 (en) 2014-11-12 2018-07-31 인텔 코포레이션 Wearable electronic devices and components thereof
US10394280B2 (en) 2014-11-12 2019-08-27 Intel Corporation Wearable electronic devices and components thereof
WO2018159839A1 (en) * 2017-03-02 2018-09-07 株式会社村田製作所 Resin multilayer substrate and electronic device

Also Published As

Publication number Publication date
JP4839713B2 (en) 2011-12-21

Similar Documents

Publication Publication Date Title
JP4839713B2 (en) Circuit board and circuit board manufacturing method
TWI389269B (en) Wiring board and probe card
US8053878B2 (en) Substrate, semiconductor device using the same, method for inspecting semiconductor device, and method for manufacturing semiconductor device
JP5071084B2 (en) Wiring substrate, laminated semiconductor device and laminated semiconductor module using the same
TW201415037A (en) Fine pitch probe card interface and probe card
TWI416121B (en) Probe card
US8289728B2 (en) Interconnect board, printed circuit board unit, and method
JPH11191577A (en) Tape carrier, semiconductor assembly and semiconductor device, and manufacturing method therefor and electronic equipment
TW439162B (en) An integrated circuit package
KR20090064314A (en) Semiconductor device
US5806178A (en) Circuit board with enhanced rework configuration
US9502378B1 (en) Printed circuit boards having blind vias, method of testing electric current flowing through blind via thereof and method of manufacturing semiconductor packages including the same
TWI448707B (en) Semiconductor test apparatus
JP2018166171A (en) Method of manufacturing semiconductor device, semiconductor device and inspection equipment for semiconductor device
JP2020088318A (en) Inspection method for wiring board and manufacturing method for wiring board
JP5107431B2 (en) Probe card
CN101241901A (en) Buried chip encapsulation structure and its making method
JP5774332B2 (en) Ceramic substrate for probe card and manufacturing method thereof
TW200529346A (en) Fabrication method of semiconductor integrated circuit device
US20110080717A1 (en) Interconnect board, printed circuit board unit, and method
KR20090070017A (en) Interposer and manufacturing method
JP2007134427A (en) Module package and its manufacturing method
JP2008060208A (en) Multilayer printed circuit board, and probe card using the same
KR102276512B1 (en) Jig for electric inspection and method of manufacturing the same
JP4860761B2 (en) Adapter board, semiconductor device using the same, and method for measuring input / output signals between printed circuit boards

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080417

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101019

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101109

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110104

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20110104

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110621

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110818

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110906

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110919

R150 Certificate of patent or registration of utility model

Ref document number: 4839713

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20141014

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees