JP2003121500A - Test device and test method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test device and a test method capable of properly testing other semiconductor devices even if one of plural semiconductor devices distributed and connected is a defective of a short circuit mode. SOLUTION: This test device is provided with: a test signal generation- determination device 2 having plural signal terminals and used for generating test signals for the semiconductor devices 1A and 1B from the respective signal terminals and for executing determination from response signals from the semiconductor devices; plural signal lines 3 connected to the respective signal terminals and respectively having plural parallel connection wires 4; and serial connection bodies each comprising a resistor 7 and a probe 5 and connected to the respective signal lines 3 and parallel connection wires 4. The probes connected to the respective signal lines and connection wires are respectively connected to corresponding pads of the plural semiconductor devices 1A and 1B to simultaneously test the plural semiconductor devices.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device test apparatus and test method, and more particularly to a test apparatus and test method for simultaneously testing a plurality of semiconductor devices.

[0002]

2. Description of the Related Art FIG. 3 is a schematic view showing the structure of a conventional device of this type. In this figure, 1A and 1B are a plurality of semiconductor devices to be tested at the same time, and the figure shows a case where there are two semiconductor devices. IN1 to IN4 are test signal receiving terminals provided in the semiconductor device, GND is a ground terminal, I / O is a terminal for the semiconductor device receiving the test signal to return a signal according to the internal conditions, and VCC is a power supply This is a voltage terminal. Reference numeral 2 denotes a test signal generation / determination device that generates a test signal (high-frequency signal) to be given to the semiconductor devices 1A and 1B, and that receives a return signal from each semiconductor device to determine pass / fail.
Although not shown, it has a plurality of signal terminals for signal supply and reception.

Reference numeral 3 denotes a plurality of signal lines connected to the respective signal terminals. Signal lines for supplying signals to the receiving terminals IN1 to IN4 of the semiconductor devices 1A and 1B and terminal I / O of the semiconductor devices 1A and 1B.
The signal line for receiving the signal from is composed of a high frequency coaxial line, and the signal line for supplying the potential to the ground terminal GND and the voltage terminal VCC is composed of a normal signal line. Reference numeral 4 denotes a parallel connection line provided to each signal line that gives a signal to the reception terminals IN1 to IN4 and the ground terminal GND. The parallel connection line of the signal lines connected to the reception terminal IN1 of the semiconductor device 1A is the same as that of the semiconductor device 1B. It is connected to the corresponding receiving terminal IN1. Other parallel connection lines are similarly connected to the corresponding terminals of the semiconductor devices 1A and 1B, respectively. Reference numeral 5 is a probe that is connected to each signal line and is connected to each terminal of the semiconductor devices 1A and 1B during a test, and 6 is a known probe card that holds each probe fixedly.

In the test, the probe 5 of the signal line 3 and the probe 5 of the parallel connection line 4 are connected to a plurality of target semiconductor devices (two in FIG. 3) as shown in FIG. By applying a predetermined high frequency signal from the generation / determination device 2, the two semiconductor devices 1A and 1B are simultaneously tested. From the semiconductor devices 1A and 1B, signals corresponding to the internal conditions of each semiconductor device are returned to the test signal generation / judgment device 2 via the respective terminal I / O, so that the test results corresponding to each test signal Is determined.

[0005]

Since the conventional semiconductor device testing apparatus and testing method are as described above,
For example, when the logic connected to the reception terminal IN1 of the semiconductor device 1A is in a short circuit failure mode such as a metal short circuit, a large current flows out from the probe 5 connected to the reception terminal IN1, and therefore the parallel connection line is connected. The logic connected to the corresponding reception terminal IN1 of the semiconductor device 1B connected to the same signal terminal as the reception terminal IN1 of the semiconductor device 1A by 4 cannot be tested.

The present invention has been made to solve the above-mentioned problems, and even if one semiconductor device among a plurality of semiconductor devices connected in a distributed manner is a defective product in a short circuit mode, another semiconductor device can be used. An object of the present invention is to provide a semiconductor device testing apparatus and a testing method capable of testing a semiconductor device normally.

[0007]

A semiconductor device testing apparatus according to the present invention has a plurality of signal terminals, and generates a test signal for the semiconductor device from each signal terminal.
A test signal generator / judgment device for making a judgment based on a return signal from a semiconductor device, a plurality of signal lines each connected to each signal terminal, each having a plurality of parallel connection lines, and connected to each signal line and the parallel connection line. And a series connection body of a probe and a probe connected to each connection line and a parallel connection line are respectively connected to corresponding pads of a plurality of semiconductor devices to simultaneously test a plurality of semiconductor devices. Is.

A semiconductor device testing apparatus according to the present invention is
Also, when setting the resistance value of the resistor, if the semiconductor device has a short circuit failure, the current flowing through the probe will generate a test signal.
The lower limit of the resistance value is the current supply capacity of the determination device, and the upper limit is the resistance value that does not impair the high-frequency follow-up property during the test.

A semiconductor device testing apparatus according to the present invention is
Further, the resistance value of the resistor is set within the range of 10Ω to 10KΩ.

A semiconductor device testing apparatus according to the present invention comprises:
Further, the resistor and the probe are integrally formed.

The semiconductor device testing apparatus according to the present invention is
In addition, a test signal generation / determination device that has a plurality of signal terminals and that generates a test signal for a semiconductor device from each signal terminal and that makes a determination by a return signal from the semiconductor device is connected to each signal terminal. , A plurality of signal lines each having a plurality of parallel connection lines, and a high resistance probe connected to each connection line and parallel connection line, a plurality of high resistance probes connected to each connection line and parallel connection line The semiconductor device is connected to the corresponding pads, and a plurality of semiconductor devices are simultaneously tested.

A method of testing a semiconductor device according to the present invention is
A test signal generation / determination device that has a plurality of signal terminals and that generates a test signal for a semiconductor device from each signal terminal and that makes a determination by a return signal from the semiconductor device, and is connected to each signal terminal, respectively. A plurality of signal lines having a plurality of parallel connection lines, and a series connection body of a resistor and a probe connected to each connection line and parallel connection line, a probe connected to each connection line and parallel connection line. The semiconductor device is connected to corresponding pads of a plurality of semiconductor devices, and a plurality of semiconductor devices are simultaneously tested.

A method of testing a semiconductor device according to the present invention is
In addition, a test signal generation / determination device that has a plurality of signal terminals, generates a test signal for the semiconductor device from each signal terminal, and makes a determination based on a return signal from the semiconductor device, and is connected to each signal terminal. , A plurality of signal lines each having a plurality of parallel connection lines, and a high resistance probe connected to each connection line and parallel connection line, a plurality of high resistance probes connected to each connection line and parallel connection line The semiconductor device is connected to the corresponding pads, and a plurality of semiconductor devices are simultaneously tested.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing the configuration and test method of the first embodiment. In this figure, 1A and 1B are a plurality of semiconductor devices to be tested at the same time, and the figure shows a case where there are two semiconductor devices.
IN1 to IN4 are test signal receiving terminals provided on the semiconductor device, GND is a ground terminal, I / O is a terminal for the semiconductor device receiving the test signal to return a signal according to the internal condition, VCC
Is a terminal for power supply voltage. 2 is the semiconductor device 1A,
A test signal generation / judgment device that generates a test signal (high-frequency signal) to be given to 1B and judges whether the signal is good or bad by receiving a return signal from each semiconductor device. It has a signal terminal.

Reference numeral 3 denotes a plurality of signal lines connected to the respective signal terminals. The signal lines supply signals to the receiving terminals IN1 to IN4 of the semiconductor devices 1A and 1B and the terminal I / O of the semiconductor devices 1A and 1B.
The signal line for receiving the signal from is composed of a high frequency coaxial line, and the signal line for supplying the potential to the ground terminal GND and the voltage terminal VCC is composed of a normal signal line. Reference numeral 4 denotes a parallel connection line provided to each signal line that gives a signal to the reception terminals IN1 to IN4 and the ground terminal GND. The parallel connection line of the signal lines connected to the reception terminal IN1 of the semiconductor device 1A is the same as that of the semiconductor device 1B. It is connected to the corresponding receiving terminal IN1. Other parallel connection lines are similarly connected to the corresponding terminals of the semiconductor devices 1A and 1B, respectively. Reference numeral 5 is a probe that is connected to each signal line and is connected to each terminal of the semiconductor devices 1A and 1B during a test, and 6 is a known probe card that holds each probe fixedly.

Reference numeral 7 is a reception terminal IN1 of the semiconductor devices 1A and 1B.
In the case where the semiconductor device 1A, 1B has a short circuit failure, the current flowing through the probe 5 is a test signal when a resistor is inserted and connected to the signal line 3 connected to the IN4 so as to form a series connection body with the probe 5. The resistance value is set so that the lower limit is a resistance value that is equal to or lower than the current supply capacity of the generation / determination device 2 and the upper limit is a resistance value that does not impair the high frequency follow-up property during a test. That is, when the semiconductor device 1A is a defective product in the short circuit failure mode, a short circuit current flows from the signal line 3 toward the semiconductor device 1A, and this current is limited by the resistor 7. Generates test signal
The lower limit of the resistance value is set so as to be equal to or less than the current supply capacity of the determination device 2.

If the resistance value is increased, the semiconductor device 1A
The maximum supply current to the IC is reduced, and the short-circuit failure mode countermeasure effect is sufficiently obtained. The resistance value that does not exist is set as the upper limit resistance value. Specifically, the resistance value of the resistor 7 is set within the range of 10Ω to 10KΩ.

The grounds for setting the lower limit of the resistance value to 10Ω are as follows. Test signal generation / determination device 2 to semiconductor device 1
The maximum voltage of the high-frequency voltage VI applied to the receiving terminals IN1 to IN4 of A and 1B is 1 [V], the current supply capacity is 100 [mA], the defective pad voltage of the semiconductor device is 0 [V] (GND), the number of distributions Assuming that (the number of connected semiconductor devices) is 2, and calculating the resistance value R to provide a margin for supplying the current to the target pad even if the current flows from the defective pad, R ≧ (1 [V ] -0 [V]) ÷ {100 [mA] ÷ (2 distribution-1 line)} =
It becomes 10Ω.

The grounds for setting the upper limit of the resistance value to 10 KΩ are as follows. When a slew rate of 20 [nS] is required for a semiconductor device having an input capacitance of 10 [pF], the charging current I is I = 10 [pF] / 20 [nS] = 0.5 [mA], and the voltage VI When the maximum and minimum difference of 5 [V] is satisfied and the path resistance R satisfying this is calculated, R ≦ 5 [V] ÷ 0.5 [mA] = 10 KΩ.

When the resistance value is 300Ω which is an intermediate value between the upper limit value and the lower limit value, the applied voltage Va is
In the case of 3.3 [V], the short circuit current Is is Is = Va / R = 3.3 / 300 = 11 [mA]. In addition, the input capacitance Ca (= 10 [pF]) rises,
The falling time Tr is the applied voltage Va (= 3.3 [V]), and the AC current Ic is Ic = Va / R = 11 [mA], so Tr = Ca ÷ Ic = 10 ÷ 11 ≒ 1 [nS] Become. With this value, the short-circuit current value and the high frequency followability do not become a big problem, and it is a practical means for increasing the number of simultaneous tests by distributing and supplying the signal source of the test signal generation / determination device 2 to a plurality of semiconductor devices. obtain.

Embodiment 2. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 shows the second embodiment.
2 is a schematic diagram showing the configuration and test method of FIG. In this figure, parts that are the same as or equivalent to those in FIG. The difference from FIG. 1 is that semiconductor devices 1A, 1
The probe connected to the receiving terminals IN1 to IN4 of B is integrated with the resistor. That is, in the figure, reference numeral 50 denotes a probe connected to the receiving terminals IN1 to IN4 of the semiconductor devices 1A and 1B, which is configured by integrating the probe 5 and the resistor 7 shown in FIG. Specifically, the probe 5 and the resistor 7 shown in FIG. 1 may be directly joined and fixed by an appropriate means, but preferably, the probe 50 is formed of a high resistance material such as ceramic, It is preferable to construct a high resistance probe and use the portion of the probe that becomes the current path as a resistor.

[0022]

The semiconductor device test apparatus and test method according to the present invention have a plurality of signal terminals, generate test signals for the semiconductor device from the respective signal terminals, and use a return signal from the semiconductor device. A test signal generation / judgment device for making a judgment, a plurality of signal lines connected to each signal terminal and each having a plurality of parallel connection lines, and a series of a resistor and a probe connected to each signal line and the parallel connection line. A connecting body is provided, and the probes connected to each connection line and the parallel connection line are respectively connected to corresponding pads of a plurality of semiconductor devices,
Since a plurality of semiconductor devices are tested at the same time, even if one semiconductor device among the plurality of semiconductor devices distributed and connected to the test signal generation / judgment device is a defective product in the short circuit mode, other semiconductor devices are normally operated. Can be tested.

The semiconductor device testing apparatus and the testing method according to the present invention, when the resistance value of the resistor is set,
When the semiconductor device has a short circuit failure, the lower limit is the resistance value that keeps the current flowing through the probe below the current supply capacity of the test signal generation / judgment device, and the upper limit is the resistance value that does not impair the high-frequency follow-up during testing. Therefore, even if a semiconductor device in the short-circuit failure mode occurs, other semiconductor devices can be tested without any trouble, and the high-frequency followability during the test is not impaired.

In the semiconductor device test apparatus and test method according to the present invention, since the resistor and the probe are integrated or the probe is configured as a high resistance probe, the test apparatus can be compactly configured. .

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration and a test method according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a configuration and a testing method according to a second embodiment of the present invention.

FIG. 3 is a schematic diagram showing a configuration of a conventional semiconductor device test apparatus.

[Explanation of symbols]

1A, 1B semiconductor device, 2 test signal generation / determination device, 3 signal lines, 4 parallel connection lines, 5 probes,
6 probe card, 7 resistor, 50 high resistance probe.

Claims (7)

[Claims] 1. A test signal generation / judgment device having a plurality of signal terminals, each of which generates a test signal for a semiconductor device, and which makes a judgment by a return signal from the semiconductor device; A plurality of signal lines connected to signal terminals, each having a plurality of parallel connection lines, and a series connection body of a resistor and a probe connected to each of the signal lines and the parallel connection lines, and each of the connection lines and A semiconductor device testing apparatus, wherein probes connected to parallel connection lines are respectively connected to corresponding pads of a plurality of semiconductor devices so as to simultaneously test a plurality of semiconductor devices. 2. The lower limit of the resistance value of the resistor is such that the current flowing through the probe when the semiconductor device has a short circuit failure is below the current supply capacity of the test signal generating / determining device. 2. The semiconductor device testing apparatus according to claim 1, wherein the resistance value is set within a range in which a resistance value that does not impair the high frequency follow-up property during testing is set as an upper limit. 3. The resistance value of the resistor is 10Ω to 10KΩ.
The semiconductor device test apparatus according to claim 2, wherein the test apparatus is set within the range. 4. The semiconductor device testing apparatus according to claim 1, wherein the resistor and the probe are integrated with each other. 5. A test signal generation / judgment device having a plurality of signal terminals, each of which generates a test signal for a semiconductor device, and which makes a judgment by a return signal from the semiconductor device; A plurality of signal lines connected to signal terminals, each having a plurality of parallel connection lines, and a high resistance probe connected to each of the connection lines and the parallel connection lines, and connected to each of the connection lines and the parallel connection lines The test apparatus for a semiconductor device, wherein the high resistance probe is connected to corresponding pads of a plurality of semiconductor devices, respectively, and the plurality of semiconductor devices are simultaneously tested. 6. A test signal generation / judgment device having a plurality of signal terminals, each of which generates a test signal for a semiconductor device, and which makes a judgment based on a return signal from the semiconductor device; A plurality of signal lines connected to signal terminals, each having a plurality of parallel connection lines, and a series connection body of a resistor and a probe connected to each of the connection lines and the parallel connection lines, and each of the connection lines and A method for testing a semiconductor device, wherein probes connected to parallel connection lines are respectively connected to corresponding pads of a plurality of semiconductor devices so that the plurality of semiconductor devices are tested simultaneously. 7. A test signal generation / judgment device having a plurality of signal terminals, each of which generates a test signal for a semiconductor device from each signal terminal, and which makes a judgment by a return signal from the semiconductor device; A plurality of signal lines connected to signal terminals, each having a plurality of parallel connection lines, and a high resistance probe connected to each of the connection lines and the parallel connection lines, and connected to each of the connection lines and the parallel connection lines The method for testing a semiconductor device is characterized in that the high resistance probe is connected to corresponding pads of a plurality of semiconductor devices, respectively, and the plurality of semiconductor devices are simultaneously tested.