JP2006310495A - Semiconductor integrated circuit wafer, method of testing it and method of manufacturing semiconductor integrated circuit components - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify a wafer inspection by simply predicting a modulus of excellent article by putting in the block leakage test of a plurality of chips in a wafer stage without reducing the number of picking of a semiconductor device from the wafer. <P>SOLUTION: Wiring 31a for a control signal, wiring 31b for a power supply and wiring 31c for earth are arranged on a scribe line 3. These are connected to each terminals 21a-21c of a plurality of semiconductor devices 2 in blocks, respectively, connected with terminals 41a-41c for each measuring in a TEG 4 provided in the block, respectively, and bundled up for every block. Accordingly, a leakage current is measured. When the leakage current is under set point, it is judged that the modulus of excellent article of the semiconductor device in the block is high, and the individual test of the semiconductor device of each wafer state is omitted. When the leakage current is beyond predetermined values, it is judged that the modulus of excellent article of the semiconductor device in the block is low, and the individual test of the semiconductor device of each wafer state is performed from each terminals 21a-21c of the semiconductor device 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention is used in, for example, a system LSI such as a liquid crystal driver, and a semiconductor integrated circuit wafer capable of executing a leak test of a plurality of semiconductor elements in a wafer state, a test method thereof, and a semiconductor integrated circuit component using the same The present invention relates to a method for manufacturing a semiconductor integrated circuit component.

  Conventionally, in this type of semiconductor integrated circuit component manufacturing method, a device comprising a large number of semiconductor elements is formed on a silicon wafer. However, silicon wafers have crystal defects, and not all devices formed on a semiconductor integrated circuit wafer are non-defective due to dust and scratches generated during manufacturing.

  Therefore, as shown in FIG. 3, a non-defective product test in a wafer state (wafer test; step S11), and this wafer is diced (divided) into a plurality of semiconductor chips (semiconductor elements) in a dicing assembly process in step S12. Then, it is necessary to perform two non-defective product tests including a non-defective product test (final test; step S13) in a packaged state in which it is assembled.

  In recent years, the crystal defects of silicon wafers have been reduced to be close to “0”, and the percentage of non-defective products of semiconductor integrated circuit wafers manufactured by improving the manufacturing process has approached 100%. It may be possible to omit the final test and reduce the number of wafer test steps.

  However, sudden failures in the manufacturing process cannot be avoided, and if all wafer tests are omitted, semiconductor integrated circuit wafers with a poor yield rate are mixed in the assembly process, resulting in a lower yield rate in the final test. Become.

  Defective products in the final test will be defective including the assembly package, and the loss will be too great in the finished product. Therefore, it is necessary to remove as much as possible the factors that reduce the final test yield rate.

  However, in the conventional wafer test method, as shown in FIG. 3, since all the semiconductor elements on the semiconductor integrated circuit wafer are individually tested, it takes about several hours per wafer. There is a problem of taking too much. As described above, as the wafer test, the final test is sequentially performed after the dicing / assembling after the individual test of the chip in the wafer state.

  On the other hand, Patent Document 1 discloses a method of connecting each pad with a fuse in order to perform a leakage current test on each pad (terminal) of a semiconductor chip (semiconductor element) in a wafer state. In this method, a plurality of pads are short-circuited by a disconnectable short-circuit means such as a fuse, and when a probe is brought into contact with one pad from the outside, the other pads also have the same potential via the fuse. Leakage current can be collectively measured for pads connected to the other pads not connected to the probe.

  Patent Document 2 discloses a configuration in which a TEG (Test Element Group) circuit is provided for each semiconductor element on a wafer. In this configuration, the wafer test of each semiconductor element is performed by a built-in test circuit provided in the TEG circuit during the wafer test, and the wiring between the TEG circuit and the semiconductor element is cut during dicing.

In Patent Document 3, for each semiconductor element on the wafer, an inspection wiring pattern is formed outside the bonding pad formation region by the same manufacturing process as the semiconductor element, and the leakage current or resistance of the wiring pattern is measured. Thus, a method for detecting a wiring defect in the semiconductor element inside the semiconductor device is disclosed. In this method, the wiring defect for each semiconductor element can be detected from the wiring defect of the inspection wiring pattern on the outside.
Japanese Patent Laid-Open No. 10-284554 JP 2001-85480 A JP 2000-332077 A

  However, in Patent Document 1, it is necessary to connect each pad in advance with a fuse, and it is necessary to cut the fuse after a non-defective product is confirmed. .

  In Patent Document 2, it is possible to perform a complicated test on each semiconductor element by the built-in test circuit of the TEG circuit. However, since a large number of TEG circuits are installed, the number of semiconductor elements taken from the same wafer. Will decrease.

  In Patent Document 3, an inspection wiring pattern (TEG) is inspected, and the actual leakage current or wiring resistance of a semiconductor element cannot be accurately measured.

  The present invention solves the above-mentioned conventional problems, and does not reduce the number of semiconductor elements taken from the wafer, and performs a leak test on a plurality of chips at the wafer stage to easily predict the yield rate, and the wafer. An object of the present invention is to provide a semiconductor integrated circuit wafer capable of simplifying the test, a test method thereof, and a method of manufacturing a semiconductor integrated circuit component using the same.

  The semiconductor integrated circuit wafer of the present invention is a semiconductor integrated circuit wafer in which a plurality of semiconductor elements are formed and a scribe line portion is provided between each semiconductor element of the plurality of semiconductor elements. At least a power supply wiring and a ground wiring are provided, the plurality of semiconductor elements are divided into one or a plurality of blocks, and the power supply terminals and the ground terminals of the plurality of semiconductor elements in the blocks are respectively connected to the power supply. The power supply wiring and the ground wiring are respectively connected to the power supply measurement terminal and the ground measurement terminal of the block, respectively. Achieved.

  Preferably, in the semiconductor integrated circuit wafer of the present invention, a control signal wiring is further provided on the scribe line portion, and control signal terminals of a plurality of semiconductor elements in the block are connected to the control signal wiring. The control signal wiring is connected to the control signal measurement terminal of the block.

  Further, preferably, a connection switching element that is controlled to be opened and closed by a control signal from the control signal wiring is provided between the power supply terminal and the power supply wiring in the semiconductor integrated circuit wafer of the present invention.

  Further preferably, the connection switching element in the semiconductor integrated circuit wafer of the present invention is a transistor.

  Further preferably, in the semiconductor integrated circuit wafer of the present invention, when measuring leakage currents of a plurality of semiconductor elements in the block, the power supply measurement terminal and the power supply terminal are connected to the power supply wiring and the connection opening / closing. The grounding measurement terminal and the grounding terminal are electrically connected through the grounding wiring and are electrically connected through the element, and the power supply terminal is used in the individual test for each semiconductor element. The connection opening / closing element can be controlled to be opened and closed so that the power supply wiring is electrically disconnected from the power supply wiring.

  Further preferably, each wiring on the scribe line portion in the semiconductor integrated circuit wafer of the present invention is made of a metal material, and the lead-in wiring connected between each wiring and each terminal of the semiconductor element is a non-metallic material. It consists of

  Further preferably, the non-metallic material in the semiconductor integrated circuit wafer of the present invention is a polysilicon material.

  Furthermore, it is preferable that a leakage of a plurality of semiconductor elements in the block is controlled by a control signal from the control signal wiring in an input part such as a logic signal input part of the semiconductor element in the semiconductor integrated circuit wafer of the present invention. An input terminal potential fixing element for fixing a potential of an input terminal such as a logic signal input terminal of the semiconductor element to a power supply potential or a ground potential at the time of current measurement is provided.

  Further, preferably, when the input portion of the semiconductor element in the semiconductor integrated circuit wafer of the present invention is in an open state, an input terminal potential fixing element is provided for fixing the potential of the input terminal of the semiconductor element to the power supply potential or the ground potential. It has been.

  Further preferably, the input terminal potential fixing element in the semiconductor integrated circuit wafer of the present invention is electrically connected between the logic signal input terminal and the power supply terminal or the grounding terminal by the control signal at the time of the leakage current measurement. In the normal operation of the semiconductor element, the logic signal input terminal and the power supply terminal or the ground terminal are electrically disconnected by the control signal.

  Further preferably, the input terminal potential fixing element in the semiconductor integrated circuit wafer of the present invention is a transistor.

  Further preferably, the measurement terminals in the semiconductor integrated circuit wafer of the present invention are provided in a test element group in the block.

  The method for testing a semiconductor integrated circuit wafer according to the present invention is the semiconductor integrated circuit wafer according to the present invention, wherein the semiconductor integrated circuit wafer is connected from the measurement terminal of the block to be measured via each wiring on the scribe line portion. A leakage current measurement step for collectively measuring the leakage current of a plurality of semiconductor elements in the block, and comparing the measured leakage current with a predetermined value set in advance, and the measured leakage current is less than the predetermined value In this case, it is determined that the non-defective rate of the plurality of semiconductor elements in the block is high, and the non-defective rate of the plurality of semiconductor elements in the block is low when the measured leakage current is equal to or higher than the predetermined value. And the non-defective product rate determining step.

  The method for testing a semiconductor integrated circuit wafer according to the present invention is the above-described semiconductor integrated circuit wafer according to the present invention, wherein the connection switching element of the block to be measured is closed and the scribe line is connected to the measurement terminal of the block. A leakage current measurement step for collectively measuring a leakage current of a plurality of semiconductor elements in the block connected via each wiring on the unit, and comparing the measured leakage current with a predetermined value set in advance, When the measured leakage current is less than the predetermined value, it is determined that the percentage of non-defective products of the plurality of semiconductor elements in the block is high, and when the measured leakage current is greater than or equal to the predetermined value, A non-defective product rate determining step for determining that the non-defective product rate of the plurality of semiconductor elements in the block is low; And an individual test step for conducting an individual test for each semiconductor element in a wafer state by electrically disconnecting the power supply wiring provided on the scribe line and thereby achieving the above object. The

  Preferably, the predetermined value in the method for testing a semiconductor integrated circuit wafer of the present invention is set based on a result obtained by measuring a correlation between the leakage current and the yield in advance.

  Further preferably, in the method for testing a semiconductor integrated circuit wafer of the present invention, a power supply potential and a ground potential are respectively supplied to the measurement terminal for power supply and the measurement terminal for ground via each measurement end, The leakage current is measured by measuring the current flowing through each measurement end.

  A method for manufacturing a semiconductor integrated circuit component according to the present invention comprises: a leak test step for collectively measuring a leakage current in the block from the measurement terminal with respect to the semiconductor integrated circuit wafer according to the present invention; When the current is less than a preset predetermined value, it is determined that the non-defective rate of the plurality of semiconductor elements in the block is high, and when the measured leakage current is equal to or greater than a preset predetermined value A wafer test step for performing an individual test for each semiconductor element in a wafer state when it is determined that the non-defective product ratio of the plurality of semiconductor elements in the block is low and the non-defective product ratio is low, and a semiconductor integrated circuit wafer after the wafer test A dicing assembly step in which the semiconductor integrated circuit package is manufactured by dicing and dividing into each semiconductor element, and performing assembly. Those having a final test step of performing a good test for the circuit package, the object is achieved.

  The operation of the present invention will be described below with the above configuration.

  In the semiconductor integrated circuit wafer of the present invention, at least the power supply wiring and the grounding wiring among the power supply wiring, the grounding wiring, and the control signal wiring are arranged on the scribe line portion, and a plurality of semiconductors in the block Connect to at least the power supply terminal and grounding terminal of the element, and connect each wiring on the scribe line section to each measurement terminal provided in the block, thereby measuring the leak current for each block at once. I can do it.

  For example, the power supply voltage Vcc is supplied to each measurement terminal provided in the TEG of each block via a measurement probe as a measurement end, or connected to the ground voltage GND, so that the power supply terminal of the semiconductor element or By supplying the power supply voltage or the ground voltage to the grounding terminal and measuring the current flowing through the power supply wiring or the grounding wiring, it becomes possible to collectively measure the leakage currents of a plurality of semiconductor elements in the block. .

  The measured leakage current is compared with a predetermined value, and if the measured leakage current is less than the predetermined value, it is judged that the non-defective rate of the plurality of semiconductor elements in the block is high, and the wafer state The testing of individual semiconductor devices in can be omitted.

  When the measured leakage current is equal to or greater than a predetermined value, it is determined that the non-defective product rate of the plurality of semiconductor elements in the block is low, and the test of each semiconductor element in the wafer state is performed.

  Furthermore, a connection switching element is provided between the power supply terminal of the semiconductor element and the power supply wiring provided on the scribe line portion, and a control signal supplied via the control signal wiring provided on the scribe line portion. By controlling the opening / closing of the connection opening / closing element by means of this, it becomes possible to electrically connect or disconnect (cut off) the power supply terminal and the power supply wiring.

  When testing individual semiconductor elements in the wafer state, the connection open / close element is opened to electrically disconnect the power supply terminals of the semiconductor elements from the power supply wiring provided on the scribe line portion.

  Further, when the leak current in the block is collectively measured, the connection switching element is closed, and the power supply terminal of the semiconductor element and the power supply wiring provided on the scribe line portion are electrically connected.

Since this connection open / close element can be composed of, for example, one transistor, it is not necessary to increase the scribe line width.
An input terminal potential fixing element is provided between the logic signal input terminal of the semiconductor element and the power supply terminal or the grounding terminal, and the control signal supplied via the control signal wiring provided on the scribe line portion By controlling the opening and closing of the input terminal potential fixing element, the potential of the logic signal input terminal can be fixed to the power supply potential or the ground potential.

  During normal operation, the input terminal potential fixing element is opened, and the logic signal input terminal of the semiconductor element and the power supply potential or ground potential of the semiconductor element are electrically disconnected, and the potential of the logic signal input terminal is not fixed.

  Also, when measuring the leakage current in the block in a lump, the input terminal potential fixing element is closed, and the logic signal input terminal of the semiconductor element and the power supply terminal or grounding terminal are electrically connected to each other. The potential of the logic signal input terminal of the element is fixed to the power supply potential or the ground potential.

  Furthermore, by using a non-metallic wiring material (for example, polysilicon material) that does not cause corrosion, the lead-in wiring connected to the terminal (pad) of the semiconductor element (chip) can be separated by dicing. There is no risk of corrosion from the cross section, and there is no problem in reliability.

  As described above, according to the present invention, it is possible to perform a leak test in units of blocks without increasing the width of the scribe line portion and reducing the number of semiconductor elements obtained in units of wafers. Moreover, if the non-defective product rate of a plurality of semiconductor elements for each block is estimated from the leakage current of each block and the estimated good product rate is high, the subsequent individual test can be omitted, and the semiconductor integrated circuit wafer The time required for the leak test can be shortened (reduction of man-hours).

  In this case, a connection switching element is provided on the scribe line section, and the connection switching element is closed to electrically connect the power supply wiring on the scribe line section and the power supply terminal of the semiconductor element. The leakage current can be measured at once. Also, if the semiconductor elements in the block are estimated to have a low yield, the connection open / close element is opened and the power supply wiring on the scribe line and the power supply terminal of the semiconductor element are electrically disconnected to individually Since the leakage current for each semiconductor element can be measured, a non-defective semiconductor element can be selected from the blocks estimated to have a low yield.

  In this way, a plurality of semiconductor elements are blocked in the wafer test, and the yield rate of the semiconductor elements is estimated based on the leakage current of the block, thereby shortening the time for the wafer test and the subsequent final test. The yield rate can be improved. Furthermore, by performing a function test or the like in the final test, it is possible to achieve both a reduction in test time and elimination of defective products.

  Furthermore, by using a non-metallic wiring material (for example, polysilicon material) as the lead-in wiring connected to the terminal (pad) of the semiconductor element (chip), the problem of corrosion is solved and the deterioration of reliability is prevented. Can do.

  Hereinafter, embodiments of a semiconductor integrated circuit wafer, a test method thereof, and a method of manufacturing a semiconductor integrated circuit component using the same will be described in detail with reference to the drawings.

  FIG. 1A is a plan view showing a configuration example of a main part of a semiconductor integrated circuit wafer according to an embodiment of the present invention, and FIG. 1B is a partial enlarged view of a portion A surrounded by a dotted line in FIG. 1C is a partially enlarged view of a portion B surrounded by a dotted line in FIG. 1B, and FIG. 1D is a partially enlarged view of a portion C surrounded by a dotted line in FIG. is there.

  1A to 1D, a semiconductor integrated circuit wafer 1 is formed with a plurality of semiconductor elements 2 (semiconductor chips) such as a liquid crystal driver, and a scribe line portion is formed between the semiconductor elements 2. The scribe lines 3 are formed in a matrix in the vertical and horizontal (or matrix). The plurality of semiconductor elements 2 are divided into one or a plurality of blocks (here, block 1 to block 3), and each block includes one or a plurality of TEG (Test Element Group). Group) 4 is originally arranged in place of the semiconductor element 2 where the semiconductor element 2 is to be formed.

  Here, the upper two stages of the plurality of semiconductor elements 2 arranged in a matrix in the vertical and horizontal directions are divided into blocks 1, the middle three stages are divided into blocks 2, and the lower two stages are divided into blocks 3. Has been. Further, since the TEG 4 is used for comparative evaluation of wafer characteristics and transistor characteristics, the TEG 4 may be arranged for each block. As shown in FIG. 1A, the characteristics are stabilized. It is desirable that each block is arranged at a substantially central position of the wafer.

  Next, as shown in the enlarged view of part A of FIG. 1B, on the scribe line 3, a control signal wiring 31a, a power supply wiring 31b and a ground wiring 31c are arranged. The wiring 31a, the wiring 31b, and the wiring 31c on the scribe line 3 are, as shown in the enlarged view of portion B in FIG. 1C, the control signal terminals 21a and the power supply terminals of the plurality of semiconductor elements 2 in each block. The wires 32a to 32c are connected to the terminal 21b and the grounding terminal 21c, respectively. The lead-in connection from the wirings 32a to 32c to the semiconductor element 2 (semiconductor chip) is made of polysilicon of a nonmetallic material in order to prevent corrosion. Further, the wiring 31a, the wiring 31b, and the wiring 31c on the scribe line 3 are made of metal in consideration of resistance.

  Further, as shown in FIG. 1B, the upper and lower semiconductor elements 2 in each block are connected by vertical wirings 31a to 31c. Further, the left and right semiconductor elements 2 in each block are connected to each other by respective horizontal wirings as shown in FIG. Furthermore, each wiring in the vertical direction is not provided between the blocks, and the blocks are separated from each other from the beginning.

  As shown in the enlarged view of part B of FIG. 1C, the power supply terminal 31b is connected to the power supply wiring 32b via a MOS transistor 33 as a connection switching element (switching element) provided on the scribe line 3. It is connected. As will be described later, the MOS transistor 33 is used in an open state (OFF) to measure a leakage current, a resistance value, and the like of each semiconductor element 2.

  Further, the power supply voltage Vcc level or the GND level is supplied to the control signal terminal 21a, and is used to control the opening / closing of the MOS transistor 33 and the internal state of the semiconductor element 2. The internal state of the semiconductor element 2, for example, the control signal terminal 21a is connected to the reset signal terminal or the logic signal input terminal of the semiconductor element 2, and these are forcibly raised to the power supply voltage Vcc and fixed. Alternatively, it is connected to the control signal wiring 31a in order to lower the ground voltage GND and fix it. The input portion of the semiconductor element 2 is configured such that all the logic signal input terminals are fixed to the ground voltage GND or the power supply voltage Vcc by the control signal from the control signal wiring 31a. For example, the logic signal input portion of the semiconductor element 2 includes a MOS (not shown) as an input terminal potential fixing element between the power supply voltage Vcc (power supply terminal 21b) and the input terminal or between the input terminal and the ground voltage GND (grounding terminal 21c). A transistor is arranged and this MOS transistor is closed (ON) by a control signal at the time of leak measurement, and the potential of the input terminal is fixed to the power supply voltage Vcc or the ground voltage GND. During normal operation, this MOS transistor is turned on by the control signal. In the open (OFF) state, the potential of the input terminal can be prevented from being fixed.

  Further, as shown in the TEG enlarged view of the C part in FIG. 1D, elements for comparative evaluation of wafer characteristics and transistor characteristics are arranged in the TEG4. In FIG. 1 (d), the test relationships are combined into one, and measurement terminals 41 a to 41 c for leak measurement are provided as each wiring 41 in the TEG 4. The wirings 31a to 31c on the scribe line 3 are respectively connected to measurement terminals 41a to 41c provided in the TEG 4 of each block. Since the configuration of the TEG 4 itself is not directly related to the present invention, the description thereof is omitted here.

  As described above, in the semiconductor integrated circuit wafer 1 of this embodiment, the control signal wiring 31a, the power supply wiring 31b and the ground wiring 31c, and the MOS transistor 33 serving as a connection switching element are provided on the scribe line 3. The leak current in each block can be collectively measured.

  The test method of the semiconductor integrated circuit wafer 1 of the present invention having the above configuration will be described in detail below.

  FIG. 2 is a flowchart for explaining a test method of the semiconductor integrated circuit wafer 1 according to the embodiment of the present invention.

  As shown in FIG. 2, first, in step S1, the test probe as one measurement end is brought into contact with the measurement terminals 41a to 41c provided in the TEG 4 of the block to be measured on the semiconductor integrated circuit wafer 1. The power supply voltage (for example, Vcc) is supplied through the test probe, and the ground voltage GND is connected through the test probe as the other measurement terminal. By measuring the current flowing through the wiring externally, it is possible to collectively measure the leakage current of a desired block.

  In this step S1, the leakage current between the power supply terminal 21b and the grounding terminal 21c of the plurality of semiconductor elements 2 is measured. At the time of this leakage current measurement, a connection switching element provided on the scribe line 3 (FIG. 1 (c ) Is closed by a control signal supplied from the control signal wiring 31a, and the power supply terminal 21b of the semiconductor element 2 and the power supply wiring 31b on the scribe line 3 are electrically connected. . Further, it is necessary to fix the input terminal of the semiconductor element 2 to the power supply voltage Vcc or the ground voltage GND by a control signal to prevent the input of the CMOS circuit from being opened. This is because if the input of the CMOS circuit is in an open state, a through current may flow through the circuit, and the leak measurement in step S1 cannot be performed normally. The input is fixed to Vcc or GND depending on the convenience of the internal circuit of the semiconductor element 2, and the fixing direction may be set so that no leakage current flows. With this state setting, it is desirable that the leakage current of the semiconductor 2 be substantially “0”. As an input fixing method, for example, there is a method in which a switch that is turned on / off by a control signal is provided at an input terminal, and the switch is turned on in step S1 to fix the potential to Vcc or GND. Further, a pull-up resistor or a pull-down resistor may be provided at the input, and when the input is open, the potential may be fixed by the pull-up resistor or the pull-down resistor.

  Next, in step S2, the magnitude relation is determined by comparing the measured leakage current with a predetermined value set in advance. The predetermined value can be set in advance by measuring the correlation between the leakage current and the yield in advance.

  In the process of step S2, if the measured leakage current is less than the predetermined value, it is determined that the non-defective product rate of the semiconductor elements 2 in the block is high, and the test of the individual semiconductor elements 2 in the wafer state is omitted. The process proceeds to step S4.

  On the other hand, if the measured leakage current is greater than or equal to the predetermined value in the process of step S2, it is determined that the non-defective product ratio of the semiconductor elements in the block is low, and the process proceeds to the next step S3, where The test of the semiconductor element 2 is performed.

  In the process of step S3, unlike the measurement of step S1, a probe is applied to the pad of the semiconductor 2 and measurement is performed one by one. In FIG. 1, probing is performed for 21a to 23c. In order to measure the semiconductor 2 alone, it is necessary to disconnect the power source connected to the semiconductor 2 of the entire block. For this reason, the connection open / close element (MOS transistor 33 shown in FIG. 1C) provided on the scribe line 3 is opened by the control signal supplied from the pad 21a, and the power supply terminal 21b of the semiconductor element 2 is scribed. The power supply wiring 31b on the line 3 is electrically disconnected. Further, the test for the semiconductor 2 is performed by opening the input fixing switch described in step S1 by the control signal so that the test signal given to the semiconductor 2 by the probing becomes valid. By discriminating non-defective products, it is possible to test individual semiconductor elements 2 as usual.

  Thereafter, in the process of step S4, the wafer is diced (divided) into a plurality of semiconductor elements 2 by the scribe line 3, assembled (assembled), and a non-defective product test (final test) in the package state is performed in step S5. Do. Thereby, the manufacture of the semiconductor integrated circuit component such as the liquid crystal driver of the present embodiment is completed.

  As described above, according to the present embodiment, the leakage current of the semiconductor elements 2 in the block can be collectively measured, and when the measured leakage current is less than a predetermined value, the yield rate (yield) is high. Therefore, by omitting the test of individual semiconductor elements in the wafer test and performing only the final test, the test time and cost can be significantly reduced. Also, if the measured leakage current is greater than or equal to a predetermined value, it is judged that the non-defective product rate is low, and each semiconductor element is individually tested as in the conventional case, thus preventing a decrease in the non-defective product rate in the final test. be able to.

  Although not specifically described in the present embodiment, a connection switching element is disposed on the scribe line 3. This connection switching element includes, for example, a MOS transistor 33 as a semiconductor element as shown in FIG. One for each 21 is sufficient, and is very small, so it is not a factor for increasing the scribe line width.

The wirings 31a to 31c on the scribe line 3 can be a metal wiring such as aluminum or a non-metallic wiring such as a polysilicon wiring. However, considering resistance, it is preferable to use a metal wiring. On the other hand, the wirings 32a to 32c that connect the wirings 31a to 31c on the scribe line 3 and the terminals 21a to 21c of the semiconductor element 2 are preferably non-metallic wirings such as polysilicon wiring. This is because when the wafer is diced and the semiconductor element (semiconductor chip) is separated, the cross section of the metal wiring is exposed, so there is a risk of corrosion due to moisture in the atmosphere, and there is no concern about corrosion. It is desirable to use a wiring made of a nonmetallic material. Since the wirings 32a to 32c in this portion are short, there is no problem that the resistance greatly increases even if it is a polysilicon wiring.
In this embodiment, the leakage measurement of the semiconductor element 2 is performed in units of blocks, but the entire wafer may be measured in a lump.
Further, a connection open / close element such as a MOS transistor may be provided between the blocks for the power supply wiring, and the upper and lower blocks may be electrically disconnected (blocked) by a control signal. In this case, if the leakage is measured over the entire wafer, and the measured leakage current is greater than or equal to a predetermined value, the blocks are separated and the leakage current is measured again in each block, so that it can be determined which block has a low yield rate. Only a block with a low yield rate needs to be tested normally, leading to a reduction in test time.

  Furthermore, in this embodiment, the control signal wiring 31a is provided on the scribe line 3, and the control signal terminals 21a of the plurality of semiconductor elements 2 in the block are connected to the control signal wiring 31a. 31a is connected to a measurement terminal 41a for the control signal of the block, and a MOS as a connection switching element that is controlled to be opened and closed by a control signal from the control signal wiring 31a between the power supply terminal 21b and the power supply wiring 31b. Although the transistor 33 is provided, the present invention is not limited thereto, and the leakage current of the present invention is also provided when the control signal terminal 21a, the control signal wiring 31a, the MOS transistor 33, and the control signal measurement terminal 41a are not provided. Tests can be performed to estimate the yield rate. In this case, in the semiconductor integrated circuit wafer of the present invention, only the power wiring 31b and the ground wiring 31c are disposed on the scribe line 3, and the plurality of semiconductor elements 2 are divided into one or a plurality of blocks. The power supply terminal 21b and the grounding terminal 21c of the plurality of semiconductor elements 2 in the block are respectively connected to the power supply wiring 31b and the grounding wiring 31c, and the power supply wiring 31b and the grounding wiring 31c are respectively connected in the block. The power supply measurement terminal 41b and the ground measurement terminal 41c are respectively connected.

  In this case, the semiconductor integrated circuit wafer is tested using a plurality of semiconductor elements 2 in the block connected from the measurement terminals 41b and 41c of the measurement target block via the respective wirings 31b and 31c on the scribe line 3. A leakage current measuring step for collectively measuring the leakage current of the block, and comparing the measured leakage current with a predetermined value set in advance, and if the measured leakage current is less than the predetermined value, The non-defective product is determined that the non-defective product rate of the plurality of semiconductor elements 2 is high and the non-defective product rate of the plurality of semiconductor elements 2 in the block is low when the measured leakage current is equal to or greater than the predetermined value. A rate determining step.

  In this embodiment, as described above and further repeatedly, when measuring the leakage current of a plurality of semiconductor elements in a block, the power supply measurement terminal and the power supply terminal are electrically connected through the power supply wiring and the connection switching element. In addition, the measurement terminal for grounding and the grounding terminal are electrically connected through the grounding wiring, and the power supply terminal and the power supply wiring are connected and opened during individual testing for each semiconductor element. The connection opening / closing element can be controlled to be opened / closed so as to be electrically disconnected by the element. In the individual test, signals such as power, GND, and control signals are supplied from pads of the individual device (semiconductor 2). The grounding terminal may be connected to the grounding measurement terminal through the grounding wiring, but the connection is not necessarily required. In addition, the TEG part on which the measurement pad is placed is not used after dicing, so it has nothing to do with corrosion. In step S3, the ground does not need to be connected to the measurement terminal during the individual test. Further, during the measurement of the individual chip in step S3, all signals are given from the pads of the chip to be measured.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention is used in, for example, a system LSI such as a liquid crystal driver, and a semiconductor integrated circuit wafer capable of executing a leak test of a plurality of semiconductor elements in a wafer state, a test method thereof, and a semiconductor integrated circuit component using the same In the field of semiconductor integrated circuit component manufacturing methods, it is possible to perform a leak test on a block basis without increasing the width of the scribe line portion and reducing the number of semiconductor elements taken on a wafer basis. Moreover, if the non-defective product rate of a plurality of semiconductor elements for each block is estimated from the leakage current of each block and the estimated good product rate is high, the subsequent individual test can be omitted, and the semiconductor integrated circuit wafer The time required for the leak test can be shortened (reduction of man-hours).

  In this case, a connection switching element is provided on the scribe line section, and the connection switching element is closed to electrically connect the power supply wiring on the scribe line section and the power supply terminal of the semiconductor element. The leakage current can be measured at once. Also, if the semiconductor elements in the block are estimated to have a low yield, the connection open / close element is opened and the power supply wiring on the scribe line and the power supply terminal of the semiconductor element are electrically disconnected to individually Since the leakage current for each semiconductor element can be measured, a non-defective semiconductor element can be selected from the blocks estimated to have a low yield.

  In this way, a plurality of semiconductor elements are blocked in the wafer test, and the yield rate of the semiconductor elements is estimated based on the leakage current of the block, thereby shortening the time for the wafer test and the subsequent final test. The yield rate can be improved. Furthermore, by performing a function test or the like in the final test, it is possible to achieve both a reduction in test time and elimination of defective products.

  Furthermore, by using a non-metallic wiring material (for example, polysilicon material) as the lead-in wiring connected to the terminal (pad) of the semiconductor element (chip), the problem of corrosion is solved and the deterioration of reliability is prevented. Can do.

(A) is a top view which shows the principal part structural example of the semiconductor integrated circuit wafer which concerns on embodiment of this invention, (b) is the elements on larger scale of A part enclosed with the dotted line of (a), (c) is (B) is the elements on larger scale of the part B enclosed with the dotted line, (d) is the elements on larger scale of the C part enclosed with the dotted line of (a). 3 is a flowchart for explaining a test method for the semiconductor integrated circuit wafer of FIG. 1. It is a flowchart for demonstrating the testing method of the conventional semiconductor integrated circuit wafer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit wafer 2 Semiconductor element 21a Control signal terminal of semiconductor element 21b Power supply terminal of semiconductor element 21c Ground terminal of semiconductor element 3 Scribe line 31a Control signal wiring on scribe line 31b Power supply wiring on scribe line 31c Grounding wiring on the scribe line
32a to 32c Wiring for connecting the wiring on the scribe line and the terminal of the semiconductor element 33 MOS transistor 4 TEG
41, 41a to 41c Measuring terminals in the TEG

Claims (17)

In a semiconductor integrated circuit wafer in which a plurality of semiconductor elements are formed and a scribe line portion is provided between each semiconductor element of the plurality of semiconductor elements,
At least power supply wiring and grounding wiring are disposed on the scribe line portion,
The plurality of semiconductor elements are divided into one or a plurality of blocks, and a power supply terminal and a ground terminal of the plurality of semiconductor elements in the block are respectively connected to the power supply wiring and the ground wiring,
A semiconductor integrated circuit wafer in which the power supply wiring and the ground wiring are respectively connected to a power supply measurement terminal and a ground measurement terminal of the block.   A control signal wiring is further provided on the scribe line section, control signal terminals of a plurality of semiconductor elements in the block are connected to the control signal wiring, and the control signal wiring is used for the control signal of the block. The semiconductor integrated circuit wafer according to claim 1, wherein the semiconductor integrated circuit wafer is connected to a measurement terminal.   The semiconductor integrated circuit wafer according to claim 2, wherein a connection switching element that is controlled to be opened and closed by a control signal from the control signal wiring is provided between the power supply terminal and the power supply wiring.   The semiconductor integrated circuit wafer according to claim 3, wherein the connection switching element is a transistor.   At the time of measuring leakage currents of a plurality of semiconductor elements in the block, the measurement terminal for power supply and the power supply terminal are electrically connected through the power supply wiring and the connection switching element, and the grounding The measurement terminal and the grounding terminal are electrically connected through the grounding wiring, and the individual power supply terminal and the power supply wiring are electrically connected by the connection switching element in the individual test for each semiconductor element. The semiconductor integrated circuit wafer according to claim 3, wherein the connection opening / closing element is capable of being controlled to be opened and closed so as to be interrupted.   Each wiring on the said scribe line part is comprised with a metal material, The lead-in wiring connected between each said wiring and each terminal of the said semiconductor element is comprised with the nonmetallic material. A semiconductor integrated circuit wafer according to claim 1.   The semiconductor integrated circuit wafer according to claim 6, wherein the non-metallic material is a polysilicon material.   The input terminal of the semiconductor element is controlled by a control signal from the control signal wiring, and when measuring leakage currents of a plurality of semiconductor elements in the block, the potential of the input terminal of the semiconductor element is set to a power supply potential or a ground potential. 6. The semiconductor integrated circuit according to claim 2, further comprising an input terminal potential fixing element for fixing the input terminal to the semiconductor integrated circuit.   6. The input terminal potential fixing element for fixing the potential of the input terminal of the semiconductor element to a power supply potential or a ground potential when the input portion of the semiconductor element is in an open state. Semiconductor integrated circuit according to claim   The input terminal potential fixing element is electrically connected between the logic signal input terminal and the power supply terminal or the grounding terminal by the control signal during the leakage current measurement, and during the normal operation of the semiconductor element. 10. The semiconductor integrated circuit wafer according to claim 8, wherein the logic signal input terminal and the power supply terminal or the ground terminal are electrically disconnected by the control signal.   The semiconductor integrated circuit wafer according to claim 8, wherein the input terminal potential fixing element is a transistor.   The semiconductor integrated circuit wafer according to claim 1, wherein the measurement terminal is provided in a test element group in the block. For the semiconductor integrated circuit wafer according to claim 1 or 2,
A leakage current measurement step for collectively measuring the leakage currents of a plurality of semiconductor elements in the block connected from the measurement terminals of the block to be measured via the wirings on the scribe line section;
Comparing the measured leakage current with a predetermined value set in advance, if the measured leakage current is less than the predetermined value, it is determined that the non-defective rate of the plurality of semiconductor elements in the block is high, A method for testing a semiconductor integrated circuit wafer, comprising: a non-defective product rate determining step for determining that a non-defective product rate of a plurality of semiconductor elements in the block is low when the measured leakage current is equal to or greater than the predetermined value. For the semiconductor integrated circuit wafer according to claim 3,
The connection open / close elements of the block to be measured are closed, and the leakage currents of a plurality of semiconductor elements in the block connected from the measurement terminals of the block via the wires on the scribe line portion are collectively displayed. Measuring the leakage current,
Comparing the measured leakage current with a predetermined value set in advance, if the measured leakage current is less than the predetermined value, it is determined that the non-defective rate of the plurality of semiconductor elements in the block is high, A non-defective rate determination step for determining that the non-defective rate of the plurality of semiconductor elements in the block is low when the measured leakage current is equal to or greater than the predetermined value;
When it is determined that the non-defective product rate is low, the connection open / close element is opened, and the power supply terminal of the semiconductor element and the power supply wiring provided on the scribe line are electrically cut off. A test method for a semiconductor integrated circuit wafer, comprising: an individual test step for performing an individual test for each semiconductor element.   15. The method for testing a semiconductor integrated circuit wafer according to claim 13, wherein the predetermined value is set based on a result of previously measuring a correlation between the leakage current and a yield.   Leakage current is measured by supplying a power supply potential and a ground potential to each of the measurement terminal for power supply and the measurement terminal for grounding via each measurement end, and measuring the current flowing through each measurement end. The method for testing a semiconductor integrated circuit wafer according to claim 13. A leak test step for measuring the leak current in the block at a time from the measurement terminal for the semiconductor integrated circuit wafer according to any one of claims 1 to 12,
If the measured leakage current is less than a predetermined value set in advance, it is determined that the non-defective product ratio of the plurality of semiconductor elements in the block is high, and the measured leakage current is greater than or equal to a predetermined value set in advance. In this case, it is determined that the non-defective product rate of the plurality of semiconductor elements in the block is low, and when the non-defective product rate is low, a wafer test step for performing an individual test for each semiconductor device in the wafer state,
After the wafer test, a dicing assembly step of dicing the semiconductor integrated circuit wafer to divide each semiconductor element and performing assembly to produce a semiconductor integrated circuit package;
A method of manufacturing a semiconductor integrated circuit component, comprising: a final test step for performing a non-defective test on the semiconductor integrated circuit package.

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