KR100894787B1 - Non volatile memory device - Google Patents

Abstract

A non volatile memory device is provided to increase the reliability of a test by configuring the memory cells under the same environment condition which is used in a real memory cell. A plane areas(211,212) are arranged in the neighboring of a decoder area, and a pad area(250) is arranged in the scribe region. The test block region(261,262) are arranged at the lower part of the plane area and is connected to the pad area. The block selection transistor region(230) is arranged in the decoder area.

Description

Nonvolatile memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device in which test blocks for testing a memory cell are configured to allow a memory cell to be closer to the environment and to perform a test using more test cells.

One type of nonvolatile memory device is that NAND flash memory devices are gradually decreasing in size of unit cell transistors, and difficulty in analyzing cell characteristics is increasing.

In general, it is necessary to evaluate the operation of memory cells under various voltage conditions and various measurement modes for evaluating memory cells of a NAND flash memory device. In order to accurately analyze the basic characteristics of each unit cell and each operation, a test pattern is used. Unit cell evaluation must be preceded.

1 is a diagram illustrating a general NAND flash memory device.

Referring to FIG. 1, the NAND flash memory device 100 may include the first and second planes 111 and 112, the first and second page buffers 121 and 122, the X decoder 130 and the peripheral circuit unit ( 140 and an input / output pad 150.

In addition, FIG. 1 further illustrates a scribe line 160 as an area remaining around the flash memory device 100 that is cut for actually using a product in the process of manufacturing the NAND flash memory device 100.

The first and second planes 111 and 112 each include a plurality of memory cells. Each of the memory cells is configured of a memory block, and each plane includes a plurality of memory blocks. In addition, the plurality of memory cells are connected to a word line and a bit line.

First and second page buffer units 121 and 122 are connected to the first and second planes 111 and 112, respectively, and each page buffer unit is connected to bit lines of the first and second planes to form a memory cell. It operates for reading a program or data.

The X decoder 130 selects memory blocks of the first and second planes 111 and 112 according to an input address, selects each word line, and the peripheral circuitry 240 selects peripheral circuits for operation. In one block, data is input and output to and from the outside through the input / output pad 250.

And a power line is constructed as shown in FIG. In addition, the scribe lines 160 are configured with the same memory cells as the memory cells of the first and second planes 111 and 112.

The flash memory device 100 uses a test pattern on the scribe line 160 to check the characteristics of the memory cell. However, the decrease in the size of the unit memory cell transistor due to the high integration causes a large variation in the basic characteristics under the influence of the surroundings, which widens the threshold voltage distribution of the memory cell.

Therefore, if the test pattern formed on the scribe line 160 does not reflect the characteristics of the memory device becoming highly integrated, the analysis of the memory cell transistor through the test pattern may not represent the entire memory.

In addition, since the configuration of the test pattern is located in a narrow area of the scribe line 160, it has a process environment different from that of the actual memory cell, which causes the cell characteristic of the test pattern to be different from that of the actual memory cell. .

Normally, the test pattern is located on the scribe line 160 having a width of 80 to 100 μm, and since the node to which the voltage can be applied is limited due to the characteristics of the measuring equipment, only less than 100 unit cell transistors can be evaluated per test pattern. . These small cell transistors cannot accurately characterize memory cell characteristics of flash memory devices ranging from 2 to 16G bytes.

Accordingly, an aspect of the present invention is to provide a nonvolatile memory device capable of analyzing characteristics of a memory cell of a nonvolatile memory device using a test block similar to an actual environment.

Nonvolatile memory device according to a feature of the present invention,

A plane region disposed around the decoder region; A pad area disposed in the scribe area; A test block area disposed below the plane area and connected to the pad area; And a block select transistor region disposed in the decoder region.

The plane region is characterized in that a plurality of memory blocks are arranged.

The bit line of the memory block positioned between the plane area and the test block area is not generated.

The block selection transistor region includes the plane region and block transistors for selecting the test block region, respectively.

The pad area may include pads connected to bit lines of the test block area, respectively.

Nonvolatile memory device according to another aspect of the present invention,

A nonvolatile memory device including a memory cell array having a plurality of memory cells comprising a word line and a bit line, the test block including a memory block including a plurality of memory cells connected to the memory cell array. ; An X decoder for selecting memory blocks included in the memory cell array or memory blocks of the test block unit by a control signal; And a pad part formed in the scribe area and including pads connected to bit lines of the test block part, respectively.

The X decoder may include a plurality of block switch circuits for selecting memory blocks of the memory cell array or the test block unit, respectively.

The bit line of one memory block positioned between the test block unit and the memory cell array is not formed.

The test block unit may be configured in a dummy pattern area generated around the memory cell array.

The pad unit may include pads connected to a switch circuit for selecting a memory block of a test block unit among the block switch circuits of the X decoder.

The apparatus may further include a page buffer unit including page buffer circuits configured to temporarily store data to be programmed in the memory cell array or to read and temporarily store data stored in the memory cell array.

A voltage for operation is provided to word lines of a memory block selected by the block switch circuit.

The data stored in the test block unit may be read through the pads of the pad unit.

Nonvolatile memory device according to another aspect of the present invention,

A nonvolatile memory device including a memory cell array in which a plurality of memory cells are composed of a word line and a bit line, the test block including a memory block including a plurality of memory cells connected to the memory cell array. ; An X decoder for selecting memory blocks included in the memory cell array or memory blocks of the test block unit by a control signal; Page buffer circuits are formed adjacent to one side of the memory cell array in which the test block unit is not formed, and temporarily store data to be programmed in the memory cell array, or read and temporarily store data stored in the memory cell array. And a pad portion including pads formed in a scribe area formed around the nonvolatile memory chip, the pads being respectively connected to bit lines of the test block portion. do.

The scribe area may be cut after the test of the memory chip is completed.

As described above, the nonvolatile memory device according to the present invention can increase the reliability of the test result by configuring the memory cells for the test in the same environment as the actual memory cells.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

2A illustrates a flash memory device according to an embodiment of the present invention.

Referring to FIG. 2A, a flash memory device 200 according to an exemplary embodiment may include first and second planes 211 and 212, first and second page buffer units 221 and 222, and an X decoder. And a peripheral circuit portion 240, input / output pads 250, and first to second test blocks 261 and 262, and a scribe line around the flash memory device 200 during its creation. 270 is present.

First and second pad portions 281 and 282 are formed in the scribe line 270.

The first and second planes 211 and 212 each include a plurality of memory cells. Each of the memory cells is configured of a memory block, and each plane includes a plurality of memory blocks. In addition, the plurality of memory cells are connected to a word line and a bit line.

In a typical flash memory device, a power line for supplying a voltage is disposed around the first and second planes 211 and 212. Since power lines are mainly composed of metal lines, other regions are filled with dummy patterns similar to memory cells.

The first and second test blocks 261 and 252 are configured using the dummy patterns, and the first and second test blocks 261 and 262 are memory of the first and second planes 211 and 212. Like a block, the memory device includes a plurality of memory cells connected to bit lines and word lines. However, the bit lines may not be connected to the bit lines of the memory cells of the first and second planes 211 and 212.

First and second page buffer units 221 and 222 are connected to the first and second planes 211 and 212, respectively, and each page buffer unit is a bit line of the first and second planes 211 and 212. Is connected to the memory cell and operates for reading a program or data into a memory cell.

The X decoder 230 selects memory blocks of the first and second planes 211 and 212 according to an input address, and allows an operating voltage to be input to word lines of the selected memory block. In addition, the X decoder 230 may select the first and second test blocks 261 and 262.

The peripheral circuit unit 240 displays peripheral circuits for operation as one block, and data is input and output to the outside through the input / output pad 250.

The first and second pad units 281 and 282 are formed of pads PAD connected to bit lines of the first and second test blocks 281 and 282, respectively. Through the pad PAD, a bit line voltage is applied to test a memory cell or a test result is read.

The flash memory device 200 uses test blocks other than the first and second planes 211 and 212 to test the memory cell. The test blocks may be selected by the X decoder 230 to receive an operating voltage on a word line, and may also receive a bit line voltage through a bit line through a pad unit. The data may be read into the memory cell through the pass unit.

Since the first and second test blocks 261 and 262 are not connected to the first and second planes 211 and 212 through bit lines, various problems may be prevented. For example, a problem that occurs when a bit line is connected between the first and second planes 211 and 212 and the first and second test blocks 261 and 262 may be caused by an increase in the total length of the bit lines. ) Increases, resulting in slower cell operation. In addition, leakage current generated in the bit lines of the first and second test blocks 261 and 262 may affect the first and second planes 211 and 212. Therefore, the bit lines between the first and second planes 211 and 212 and the first and second test blocks 261 and 262 are cut off.

The connection relationship between the first and second planes 211 and 212 and the first and second test blocks 261 and 262 and the block selection switch of the X decoder 230 are described in detail as follows.

FIG. 2B is a detailed circuit diagram of the X decoder of FIG. 2A.

2B illustrates a portion of second plane 212, second test block 262, and X decoder 230. As shown in FIG. 2B, it may be confirmed that the bit line BL is not formed between the second plane 212 and the second test block 262. However, except for the bit line, the active and word lines are formed in the same manner, and the second plane 212 and the second test block 262 are separated because the bit lines are broken.

The X decoder 230 includes an N-th block switch 231, an M-th block switch 232, and a connection unit 233. The X decoder 230 includes a plurality of block switches, and only the Nth block switch 231 and the Mth block switch 232 are shown in FIG. 2B.

The N-th block switch 231 may be a block switch for selecting an N-th memory block among the memory blocks of the second plane 212, and the M-th block switch 232 may select the second test block 262. .

When the second test block 262 is selected by the M-th block switch 232, an operating voltage may be supplied to the word lines of the second test block 262 by the connection unit 233. The word lines are connected to gates of respective memory cells.

When the test block includes a plurality of test blocks including the second test block 262, block switches of the X decoder 230 are also provided according to the blocks. By using a block switch, one node can select the entire test block. Therefore, even if the block switch is connected to the pad portion of the scribe line 270 in addition to the X decoder 230, the entire test block can be selected with one pad, thereby reducing the number of pads. As such, the structure in which the test block is selected and operated may provide an operating environment similar to an actual memory cell, thereby increasing a test effect.

The connection between the bit lines of the second test block 262 and the pad unit 282 is as follows.

FIG. 2C shows the plane and test block of FIG. 2A.

Referring to FIG. 2C, the second test block 262 is configured in the same manner as the memory cell of the second plane 212. The active lines are connected and the word lines WL are identical.

The bit lines BL of the second test block 262 are respectively connected to the pads PAD of the pad unit 282. The bit line voltage may be input to the bit line of the second test block 262 by connecting to the pads PAD. In addition, the pads PAD may measure the state of the memory cell of the second test block 262.

At this time, as shown in FIG. 2C, bit lines are not formed in the memory block between the second plane 212 and the second test block 262, so that the bit lines of the second plane 212 and the second test block 262 are not included. Hang up.

2B and 2C illustrate the second test block 262, but the first test block 261 is configured in the same manner.

After the characteristics of the memory cell are tested using the test block as described above, the scribe line 270 is cut to separate the flash memory device 200, so that the test blocks are no longer used. In this case, as mentioned above, the test blocks are not connected to the plane by bit lines, and thus, the operation of the flash memory device 200 is not affected.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a diagram illustrating a general NAND flash memory device.

2A illustrates a flash memory device according to an embodiment of the present invention.

FIG. 2B is a detailed circuit diagram of the X decoder of FIG. 2A.

FIG. 2C shows the plane and test block of FIG. 2A.

* Brief description of the main parts of the drawings *

211, 212: first and second plane

221 and 222: first and second page buffer units

230: X decoder

240: peripheral circuit

250: input / output pad

261 and 162: first and second test blocks

270: disk drive area

281 and 282: first and second pad portions

Claims (14)

A plane region disposed around the decoder region; A pad area disposed in the scribe area; A test block area disposed below the plane area and connected to the pad area; And And a block select transistor region disposed in the decoder region. The method of claim 1, The plane region is a nonvolatile memory device, characterized in that a plurality of memory blocks are arranged. The method of claim 1, And not generating a bit line of a memory block positioned between the plane region and the test block region. The method of claim 1, And the block select transistor region includes block planes for selecting the plane region and the test block region, respectively. The method of claim 1, The pad area may include pads connected to bit lines of the test block area, respectively. A nonvolatile memory device including a memory cell array in which a plurality of memory cells are composed of a word line and a bit line. A test block unit including memory blocks including a plurality of memory cells connected to the memory cell array; An X decoder for selecting memory blocks included in the memory cell array or memory blocks of the test block unit by a control signal; And A pad part formed in a scribe area and including pads connected to bit lines of the test block part, respectively; Nonvolatile memory device comprising a. The method of claim 6, And the X decoder includes a plurality of block switch circuits for selecting memory blocks of the memory cell array or the test block unit, respectively. The method of claim 6, And not forming a bit line of one memory block positioned between the test block unit and the memory cell array. The method of claim 6, The test block unit, And a dummy pattern area formed around the memory cell array. The method of claim 7, wherein The pad unit, And pads connected to a switch circuit for selecting a memory block of a test block unit among the block switch circuits of the X decoder. The method of claim 6, And a page buffer unit for temporarily storing data to be programmed in the memory cell array or for reading and temporarily storing data stored in the memory cell array. The method of claim 7, wherein And a voltage for operation is provided to word lines of a memory block selected by the block switch circuit. The method of claim 6, And reading data stored in the test block unit through pads of the pad unit. A nonvolatile memory device including a memory cell array in which a plurality of memory cells are composed of a word line and a bit line. A test block unit including memory blocks including a plurality of memory cells connected to the memory cell array; An X decoder for selecting memory blocks included in the memory cell array or memory blocks of the test block unit by a control signal; Page buffer circuits formed to be adjacent to one side of the memory cell array in which the test block unit is not formed, and temporarily store data to be programmed in the memory cell array, or read and temporarily store data stored in the memory cell array. A nonvolatile memory chip including a page buffer unit to include; And a pad portion formed in a scribe area formed around the nonvolatile memory chip, the pad portion including pads connected to bit lines of the test block portion, respectively.

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