KR20000008137A - Teg pattern formation method of semiconductor devices - Google Patents

Abstract

PURPOSE: A forming method of TEG(test element group) patterns is provided to increase a number of net die of semiconductor devices by forming a portion of TEG patterns to a main chip formation part instead of a scribe line. CONSTITUTION: When a bonding pad(200) of a main chip is formed, an individual device(210) for monitoring is formed at lower part of the bonding pad(200) in the main chip, and a first and a second pad terminals(220a, 220b) are located in a scribe line. A routing metal line(230) is electrically connected between the individual device(210) and the first and second pad terminals(220a,220b). Since the first and second pad terminals(220a,220b) are formed only on the scribe line, the pitch between the first and second pad terminals is decreased. Thereby, the number of net die is increased.

Description

Tag pattern formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a test element group (TEG) pattern of a semiconductor device, and more particularly, to form a part of a test element group pattern in a main chip forming portion instead of a scribe line. The present invention relates to a method for forming a TEG pattern of a semiconductor device by forming a specific portion (for example, a portion where a bonding pad is to be formed), thereby increasing the number of net dies of the semiconductor device during device fabrication.

With the miniaturization and high integration of semiconductor devices, in recent years, the area of scribe lines can be reduced by reducing the TEG pattern or reducing the photo align key to increase the number of net dies on wafers of the same standard. Technological developments are underway to minimize them.

FIG. 1 is a plan view showing a layout structure of a conventional semiconductor device including a bonding pad and a TEG of a main chip manufactured based on such a criterion. As an example, a description will be given of tag pattern formation during a unit process for bonding pad formation.

Referring to FIG. 1, in the formation of a pad of a conventional semiconductor device, typically, only a bonding pad 10 having a multi-layer stack structure forming a semiconductor chip is formed in a main chip forming portion, and a TEG pattern is formed on a scribe line for sawing between chips. It can be seen that the process proceeds to form the individual elements 20 (eg, TEG pads) for monitoring and the first and second pad terminals 30a and 30b for measuring the individual elements.

At this time, the TEG pattern is configured such that the first and second pad terminals 30a and 30b are arranged in a line with one monitoring individual element 20 interposed therebetween, and the individual element 20 and The first and second pad terminals 30a and 30b are configured to be electrically connected by a route metal 40.

Therefore, in the TEG pattern having the above structure, it is determined whether the unit process is properly performed in the following manner immediately after the bonding pad 10 forming process is completed.

That is, after applying a voltage into the individual element 20 through the first pad terminal 30a connected to one side of the individual element 20 for monitoring, the second pad terminal 30b connected to the other side of the individual element 20. By monitoring the data output through) to determine whether or not the process failure occurs by determining whether the data value is consistent with the predetermined setting value (setting value).

However, when the individual elements 20 for monitoring and the first and second pad terminals 30a and 30b constituting the TEG pattern are formed in the scribe line for sawing as described above, they are formed to monitor process variables. Due to the relationship that the size of the individual elements 20 occupy a considerable area in terms of the wafer side, there is a problem that the number of net dies is reduced when manufacturing a semiconductor device, an improvement for this is urgently required.

Accordingly, an object of the present invention is to provide a TEG pattern such that the individual elements for monitoring during the unit process for manufacturing a semiconductor device are located under the bonding pads of the main chip forming portion, and the first and second pad terminals connected thereto are located in the scribe line. The present invention provides a method for forming a TEG of a semiconductor device, which can increase the number of net dies during device fabrication.

1 is a plan view illustrating a layout structure of a semiconductor device having a bonding pad and a TEG pattern of a main chip according to the related art;

2 is a plan view illustrating a layout structure of a semiconductor device having a bonding pad and a TEG pattern of a main chip as a first embodiment of the present invention;

3 is a plan view illustrating a layout structure of a semiconductor device having a bonding pad and a TEG pattern of a main chip as a second embodiment of the present invention.

In the first embodiment of the present invention, in order to achieve the above object, in the method for forming a TEG pattern of a semiconductor device, the individual elements for monitoring forming the TEG pattern are formed so as to be placed under a bonding pad in a main chip, and are connected to each other. A method for forming a TEG pattern of a semiconductor device is provided, wherein the first and second pad terminals are formed to lie in a scribe line.

In the second embodiment of the present invention, in order to achieve the above object, in the method for forming a TEG pattern of a semiconductor device, the individual elements for monitoring forming the TEG pattern are overlapped with predetermined bonding pads adjacent to each other in the main chip, respectively. A method of forming a TEG pattern of a semiconductor device is provided below the bonding pad, and the first and second pad terminals connected to the bonding pad are formed to lie in the scribe line.

When the TEG pattern is formed as described above, part of the TEG pattern (for example, an individual device for monitoring) is placed in the main chip forming portion instead of the scribe line, so that the pitch between the first and second pad terminals may be changed during device manufacturing. pitch) can reduce the area occupied by the scrabble lines on the wafer.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

According to the present invention, a part of the TEG pattern (for example, an individual element for monitoring) formed in the scribe line is formed in a specific portion of the main chip forming portion (for example, a portion in which a bonding pad is to be formed), instead of a scribe line, This technology focuses on increasing the number of net dies of a semiconductor device by reducing the area.

2 and 3 are plan views showing the layout structure of the semiconductor device according to the first and second embodiments of the present invention, in which a bonding pad and a TEG pattern of a main chip manufactured based on these standards are provided. .

First, a first embodiment of the present invention will be described with reference to the plan view of FIG. 2.

Referring to FIG. 2, in the first embodiment of the present invention, when the bonding pads 200 of the semiconductor device are formed, the monitoring individual elements 210 are placed under the bonding pads 200 of the main chip forming unit, while the first and the first elements are formed. It can be seen that the two pad terminals 220a and 220b form a TEG pattern so as to lie in the scribe line.

At this time, the individual device 210 for monitoring and the first and second pad terminals 220a, 220b are formed to be electrically connected by the route metal wire 230.

When the bonding pad 200 of the main chip and the individual monitoring device 210 are formed in the same manner as described above, only the first and second pad terminals 220a and 220b are placed on the scribe line. The pitch between the second pad terminals 220a and 220b can be significantly reduced than in the conventional case. As a result, the area occupied by the scribe line on the wafer can also be taken small, thereby increasing the number of net dies of the semiconductor device during device fabrication.

Next, a second embodiment of the present invention will be described with reference to the top view of FIG. 3.

Referring to FIG. 3, in the second embodiment of the present invention, in the formation of the bonding pads 200 of the semiconductor device, the monitoring individual elements 210 are bonded to each other by overlapping the bonding pads 200 adjacent to each other in the main chip. It can be seen that the first and second pad terminals 220a and 220b form a TEG pattern so as to lie under the pad 200, while the first and second pad terminals 220a and 220b lie in a scribe line.

At this time, the individual device 210 for monitoring and the first and second pad terminals 220a, 220b are formed to be electrically connected by the route metal wire 230.

In this case as well, since the area occupied by the scribe line on the wafer can be made smaller than in the conventional case, the number of net dies of the semiconductor device can be increased during device manufacturing.

As described above, according to the present invention, a portion of the TEG pattern (for example, an individual device for monitoring) is formed to be positioned below the bonding pad of the main chip rather than a scribe line during each unit process of the semiconductor device. It is possible to minimize the area occupied by the scrabble lines in the phase, thereby increasing the number of net dies of the semiconductor device.

Claims (6)

In the method of forming a TEG pattern of a semiconductor device, The individual element for monitoring forming the TEG pattern is formed to be placed under the bonding pad in the main chip, and the first and second pad terminals connected thereto are formed to be placed in the scribe line. . The method of claim 1, wherein the monitoring element and the first and second pad terminals are electrically connected to each other by a metal wire. The method of claim 1, wherein the first and second pad terminals are formed of a conductive film. In the method of forming a TEG pattern of a semiconductor device, The individual elements for monitoring forming the TEG pattern are formed under the bonding pads so as to partially overlap with the bonding pads adjacent to each other in the main chip, and the first and second pad terminals connected thereto are placed in the scribe line. A method for forming a TEG pattern of a semiconductor device. 5. The method of claim 4, wherein the monitoring element and the first and second pad terminals are electrically connected by metal wires. The method of claim 4, wherein the first and second pad terminals are formed of a conductive film.